1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/amd/versal2 8 9# A78 Erratum for SoC 10ERRATA_A78_AE_1941500 := 1 11ERRATA_A78_AE_1951502 := 1 12ERRATA_A78_AE_2376748 := 1 13ERRATA_A78_AE_2395408 := 1 14ERRATA_ABI_SUPPORT := 1 15 16# Platform Supports Armv8.2 extensions 17ARM_ARCH_MAJOR := 8 18ARM_ARCH_MINOR := 2 19 20override PROGRAMMABLE_RESET_ADDRESS := 1 21PSCI_EXTENDED_STATE_ID := 1 22SEPARATE_CODE_AND_RODATA := 1 23override RESET_TO_BL31 := 1 24PL011_GENERIC_UART := 1 25IPI_CRC_CHECK := 0 26GIC_ENABLE_V4_EXTN := 0 27GICV3_SUPPORT_GIC600 := 1 28 29override CTX_INCLUDE_AARCH32_REGS := 0 30 31ifdef MEM_BASE 32 $(eval $(call add_define,MEM_BASE)) 33 34 ifndef MEM_SIZE 35 $(error "MEM_BASE defined without MEM_SIZE") 36 endif 37 $(eval $(call add_define,MEM_SIZE)) 38 39 ifdef MEM_PROGBITS_SIZE 40 $(eval $(call add_define,MEM_PROGBITS_SIZE)) 41 endif 42endif 43 44ifdef BL32_MEM_BASE 45 $(eval $(call add_define,BL32_MEM_BASE)) 46 47 ifndef BL32_MEM_SIZE 48 $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE") 49 endif 50 $(eval $(call add_define,BL32_MEM_SIZE)) 51endif 52 53ifdef IPI_CRC_CHECK 54 $(eval $(call add_define,IPI_CRC_CHECK)) 55endif 56 57USE_COHERENT_MEM := 0 58HW_ASSISTED_COHERENCY := 1 59 60VERSAL2_CONSOLE ?= pl011 61ifeq (${VERSAL2_CONSOLE}, $(filter ${VERSAL2_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 62 else 63 $(error "Please define VERSAL2_CONSOLE") 64 endif 65 66$(eval $(call add_define_val,VERSAL2_CONSOLE,VERSAL2_CONSOLE_ID_${VERSAL2_CONSOLE})) 67 68# Runtime console in default console in DEBUG build 69ifeq ($(DEBUG), 1) 70CONSOLE_RUNTIME ?= pl011 71endif 72 73# Runtime console 74ifdef CONSOLE_RUNTIME 75ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 76$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 77else 78 $(error "Please define CONSOLE_RUNTIME") 79endif 80endif 81 82 83ifdef XILINX_OF_BOARD_DTB_ADDR 84$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 85endif 86 87PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 88 -Iplat/xilinx/common/include/ \ 89 -Iplat/xilinx/common/ipi_mailbox_service/ \ 90 -I${PLAT_PATH}/include/ \ 91 -Iplat/xilinx/versal/pm_service/ 92 93# Include GICv3 driver files 94include drivers/arm/gic/v3/gicv3.mk 95include lib/xlat_tables_v2/xlat_tables.mk 96include lib/libfdt/libfdt.mk 97 98PLAT_BL_COMMON_SOURCES := \ 99 drivers/arm/dcc/dcc_console.c \ 100 drivers/delay_timer/delay_timer.c \ 101 drivers/delay_timer/generic_delay_timer.c \ 102 ${GICV3_SOURCES} \ 103 drivers/arm/pl011/aarch64/pl011_console.S \ 104 plat/common/aarch64/crash_console_helpers.S \ 105 plat/arm/common/arm_common.c \ 106 plat/common/plat_gicv3.c \ 107 ${PLAT_PATH}/aarch64/helpers.S \ 108 ${PLAT_PATH}/aarch64/common.c \ 109 ${PLAT_PATH}/plat_topology.c \ 110 ${XLAT_TABLES_LIB_SRCS} 111 112BL31_SOURCES += drivers/arm/cci/cci.c \ 113 lib/cpus/aarch64/cortex_a78_ae.S \ 114 lib/cpus/aarch64/cortex_a78.S \ 115 plat/common/plat_psci_common.c \ 116 drivers/scmi-msg/base.c \ 117 drivers/scmi-msg/entry.c \ 118 drivers/scmi-msg/smt.c \ 119 drivers/scmi-msg/clock.c \ 120 drivers/scmi-msg/power_domain.c \ 121 drivers/scmi-msg/reset_domain.c \ 122 ${PLAT_PATH}/scmi.c 123 124BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 125 126BL31_SOURCES += plat/xilinx/common/plat_fdt.c \ 127 common/fdt_wrappers.c \ 128 plat/xilinx/common/plat_fdt.c \ 129 plat/xilinx/common/plat_console.c \ 130 plat/xilinx/common/plat_startup.c \ 131 plat/xilinx/common/ipi.c \ 132 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 133 ${PLAT_PATH}/soc_ipi.c \ 134 plat/xilinx/common/versal.c \ 135 ${PLAT_PATH}/bl31_setup.c \ 136 common/fdt_fixup.c \ 137 common/fdt_wrappers.c \ 138 ${LIBFDT_SRCS} \ 139 ${PLAT_PATH}/sip_svc_setup.c \ 140 ${PLAT_PATH}/gicv3.c 141 142ifeq (${ERRATA_ABI_SUPPORT}, 1) 143# enable the cpu macros for errata abi interface 144CORTEX_A78_AE_H_INC := 1 145$(eval $(call add_define, CORTEX_A78_AE_H_INC)) 146endif 147