1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex_system_manager.h" 13 #include <lib/utils_def.h> 14 #include <platform_def.h> 15 16 /* Platform Setting */ 17 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX 18 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 19 #define PLAT_PRIMARY_CPU 0 20 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 21 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 22 23 /* FPGA config helpers */ 24 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 25 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 26 27 /* QSPI Setting */ 28 #define CAD_QSPIDATA_OFST 0xff900000 29 #define CAD_QSPI_OFFSET 0xff8d2000 30 31 /* Register Mapping */ 32 #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 33 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 34 35 #define SOCFPGA_MMC_REG_BASE 0xff808000 36 #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 37 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 38 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 39 #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 40 41 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 42 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 43 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 44 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 45 46 /******************************************************************************* 47 * Platform memory map related constants 48 ******************************************************************************/ 49 #define DRAM_BASE (0x0) 50 #define DRAM_SIZE (0x80000000) 51 52 #define OCRAM_BASE (0xFFE00000) 53 #define OCRAM_SIZE (0x00040000) 54 55 #define MEM64_BASE (0x0100000000) 56 #define MEM64_SIZE (0x1F00000000) 57 58 #define DEVICE1_BASE (0x80000000) 59 #define DEVICE1_SIZE (0x60000000) 60 61 #define DEVICE2_BASE (0xF7000000) 62 #define DEVICE2_SIZE (0x08E00000) 63 64 #define DEVICE3_BASE (0xFFFC0000) 65 #define DEVICE3_SIZE (0x00008000) 66 67 #define DEVICE4_BASE (0x2000000000) 68 #define DEVICE4_SIZE (0x0100000000) 69 70 #define BL2_BASE (0xffe00000) 71 #define BL2_LIMIT (0xffe2b000) 72 73 #define BL31_BASE (0x1000) 74 #define BL31_LIMIT (0x81000) 75 76 /******************************************************************************* 77 * UART related constants 78 ******************************************************************************/ 79 #define PLAT_UART0_BASE (0xFFC02000) 80 #define PLAT_UART1_BASE (0xFFC02100) 81 82 /******************************************************************************* 83 * WDT related constants 84 ******************************************************************************/ 85 #define WDT_BASE (0xFFD00200) 86 87 /******************************************************************************* 88 * GIC related constants 89 ******************************************************************************/ 90 #define PLAT_GIC_BASE (0xFFFC0000) 91 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 92 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 93 #define PLAT_GICR_BASE 0 94 95 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 96 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 97 98 /******************************************************************************* 99 * SDMMC related pointer function 100 ******************************************************************************/ 101 #define SDMMC_READ_BLOCKS mmc_read_blocks 102 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 103 104 /******************************************************************************* 105 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 106 * is done and HPS should trigger warm reset via RMR_EL3. 107 ******************************************************************************/ 108 #define L2_RESET_DONE_REG 0xFFD12218 109 110 /* Platform specific system counter */ 111 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 112 113 #endif /* PLAT_SOCFPGA_DEF_H */ 114