1 /* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat, mask) \ 16 ((unsigned int)(((reg) >> (feat)) & mask)) 17 18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 19 __attribute__((always_inline)) \ 20 static inline bool is_ ## name ## _supported(void) \ 21 { \ 22 if ((guard) == FEAT_STATE_DISABLED) { \ 23 return false; \ 24 } \ 25 if ((guard) == FEAT_STATE_ALWAYS) { \ 26 return true; \ 27 } \ 28 return read_func(); \ 29 } 30 31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 32 __attribute__((always_inline)) \ 33 static inline bool is_ ## name ## _present(void) \ 34 { \ 35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 36 ? true : false; \ 37 } 38 39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ 40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 41 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 42 43 44 /* +----------------------------+ 45 * | Features supported | 46 * +----------------------------+ 47 * | GENTIMER | 48 * +----------------------------+ 49 * | FEAT_PAN | 50 * +----------------------------+ 51 * | FEAT_VHE | 52 * +----------------------------+ 53 * | FEAT_TTCNP | 54 * +----------------------------+ 55 * | FEAT_UAO | 56 * +----------------------------+ 57 * | FEAT_PACQARMA3 | 58 * +----------------------------+ 59 * | FEAT_PAUTH | 60 * +----------------------------+ 61 * | FEAT_TTST | 62 * +----------------------------+ 63 * | FEAT_BTI | 64 * +----------------------------+ 65 * | FEAT_MTE2 | 66 * +----------------------------+ 67 * | FEAT_SSBS | 68 * +----------------------------+ 69 * | FEAT_NMI | 70 * +----------------------------+ 71 * | FEAT_GCS | 72 * +----------------------------+ 73 * | FEAT_EBEP | 74 * +----------------------------+ 75 * | FEAT_SEBEP | 76 * +----------------------------+ 77 * | FEAT_SEL2 | 78 * +----------------------------+ 79 * | FEAT_TWED | 80 * +----------------------------+ 81 * | FEAT_FGT | 82 * +----------------------------+ 83 * | FEAT_EC/ECV2 | 84 * +----------------------------+ 85 * | FEAT_RNG | 86 * +----------------------------+ 87 * | FEAT_TCR2 | 88 * +----------------------------+ 89 * | FEAT_S2POE | 90 * +----------------------------+ 91 * | FEAT_S1POE | 92 * +----------------------------+ 93 * | FEAT_S2PIE | 94 * +----------------------------+ 95 * | FEAT_S1PIE | 96 * +----------------------------+ 97 * | FEAT_AMU/AMUV1P1 | 98 * +----------------------------+ 99 * | FEAT_MPAM | 100 * +----------------------------+ 101 * | FEAT_HCX | 102 * +----------------------------+ 103 * | FEAT_RNG_TRAP | 104 * +----------------------------+ 105 * | FEAT_RME | 106 * +----------------------------+ 107 * | FEAT_SB | 108 * +----------------------------+ 109 * | FEAT_CSV2/CSV3 | 110 * +----------------------------+ 111 * | FEAT_SPE | 112 * +----------------------------+ 113 * | FEAT_SVE | 114 * +----------------------------+ 115 * | FEAT_RAS | 116 * +----------------------------+ 117 * | FEAT_DIT | 118 * +----------------------------+ 119 * | FEAT_SYS_REG_TRACE | 120 * +----------------------------+ 121 * | FEAT_TRF | 122 * +----------------------------+ 123 * | FEAT_NV/NV2 | 124 * +----------------------------+ 125 * | FEAT_BRBE | 126 * +----------------------------+ 127 * | FEAT_TRBE | 128 * +----------------------------+ 129 * | FEAT_SME/SME2 | 130 * +----------------------------+ 131 * | FEAT_PMUV3 | 132 * +----------------------------+ 133 * | FEAT_MTPMU | 134 * +----------------------------+ 135 * | FEAT_FGT2 | 136 * +----------------------------+ 137 * | FEAT_THE | 138 * +----------------------------+ 139 * | FEAT_SCTLR2 | 140 * +----------------------------+ 141 */ 142 143 __attribute__((always_inline)) 144 static inline bool is_armv7_gentimer_present(void) 145 { 146 /* The Generic Timer is always present in an ARMv8-A implementation */ 147 return true; 148 } 149 150 /* FEAT_PAN: Privileged access never */ 151 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 152 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN) 153 154 /* FEAT_VHE: Virtualization Host Extensions */ 155 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 156 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE) 157 158 /* FEAT_TTCNP: Translation table common not private */ 159 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 160 ID_AA64MMFR2_EL1_CNP_MASK, 1U) 161 162 /* FEAT_UAO: User access override */ 163 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 164 ID_AA64MMFR2_EL1_UAO_MASK, 1U) 165 166 /* If any of the fields is not zero, QARMA3 algorithm is present */ 167 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 168 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 169 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U) 170 171 /* PAUTH */ 172 __attribute__((always_inline)) 173 static inline bool is_armv8_3_pauth_present(void) 174 { 175 uint64_t mask_id_aa64isar1 = 176 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 177 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 178 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 179 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 180 181 /* 182 * If any of the fields is not zero or QARMA3 is present, 183 * PAuth is present 184 */ 185 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 186 is_feat_pacqarma3_present()); 187 } 188 189 /* FEAT_TTST: Small translation tables */ 190 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 191 ID_AA64MMFR2_EL1_ST_MASK, 1U) 192 193 /* FEAT_BTI: Branch target identification */ 194 CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 195 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED) 196 197 /* FEAT_MTE2: Memory tagging extension */ 198 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 199 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2) 200 201 /* FEAT_SSBS: Speculative store bypass safe */ 202 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 203 ID_AA64PFR1_EL1_SSBS_MASK, 1U) 204 205 /* FEAT_NMI: Non-maskable interrupts */ 206 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 207 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED) 208 209 /* FEAT_EBEP */ 210 CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 211 ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED) 212 213 /* FEAT_SEBEP */ 214 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 215 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED) 216 217 /* FEAT_SEL2: Secure EL2 */ 218 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 219 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2) 220 221 /* FEAT_TWED: Delayed trapping of WFE */ 222 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 223 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED) 224 225 /* FEAT_FGT: Fine-grained traps */ 226 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 227 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT) 228 229 /* FEAT_FGT2: Fine-grained traps extended */ 230 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 231 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2) 232 233 /* FEAT_ECV: Enhanced Counter Virtualization */ 234 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 235 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV) 236 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 237 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) 238 239 /* FEAT_RNG: Random number generator */ 240 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 241 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG) 242 243 /* FEAT_TCR2: Support TCR2_ELx regs */ 244 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 245 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2) 246 247 /* FEAT_S2POE */ 248 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 249 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE) 250 251 /* FEAT_S1POE */ 252 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 253 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE) 254 255 __attribute__((always_inline)) 256 static inline bool is_feat_sxpoe_supported(void) 257 { 258 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 259 } 260 261 /* FEAT_S2PIE */ 262 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 263 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE) 264 265 /* FEAT_S1PIE */ 266 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 267 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE) 268 269 /* FEAT_THE: Translation Hardening Extension */ 270 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 271 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE) 272 273 /* FEAT_SCTLR2 */ 274 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 275 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 276 ENABLE_FEAT_SCTLR2) 277 278 __attribute__((always_inline)) 279 static inline bool is_feat_sxpie_supported(void) 280 { 281 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 282 } 283 284 /* FEAT_GCS: Guarded Control Stack */ 285 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 286 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS) 287 288 /* FEAT_AMU: Activity Monitors Extension */ 289 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 290 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU) 291 292 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 293 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 294 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) 295 296 /* 297 * Return MPAM version: 298 * 299 * 0x00: None Armv8.0 or later 300 * 0x01: v0.1 Armv8.4 or later 301 * 0x10: v1.0 Armv8.2 or later 302 * 0x11: v1.1 Armv8.4 or later 303 * 304 */ 305 __attribute__((always_inline)) 306 static inline bool is_feat_mpam_present(void) 307 { 308 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 309 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 310 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 311 & ID_AA64PFR1_MPAM_FRAC_MASK)); 312 return ret; 313 } 314 315 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 316 317 /* 318 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 319 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 320 * Feat_Debug supported. The value of the field determines feature presence 321 * 322 * 0b0110 - Arm v8.0 debug 323 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 324 * 0x1000 - FEAT_Debugv8p2 is supported 325 * 0x1001 - FEAT_Debugv8p4 is supported 326 * 0x1010 - FEAT_Debugv8p8 is supported 327 * 0x1011 - FEAT_Debugv8p9 is supported 328 * 329 */ 330 CREATE_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, ID_AA64DFR0_DEBUGVER_SHIFT, 331 ID_AA64DFR0_DEBUGVER_MASK, DEBUGVER_V8P9_IMPLEMENTED, 332 ENABLE_FEAT_DEBUGV8P9) 333 334 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 335 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 336 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX) 337 338 /* FEAT_RNG_TRAP: Trapping support */ 339 CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 340 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED) 341 342 /* Return the RME version, zero if not supported. */ 343 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT, 344 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME) 345 346 /* FEAT_SB: Speculation barrier instruction */ 347 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 348 ID_AA64ISAR1_SB_MASK, 1U) 349 350 /* 351 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 352 * of id_aa64pfr0_el1 register and can be used to check for below features: 353 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 354 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 355 * 0b0000 - Feature FEAT_CSV2 is not implemented. 356 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 357 * are not implemented. 358 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 359 * implemented. 360 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 361 */ 362 363 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 364 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) 365 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 366 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) 367 368 /* FEAT_SPE: Statistical Profiling Extension */ 369 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 370 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS) 371 372 /* FEAT_SVE: Scalable Vector Extension */ 373 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 374 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS) 375 376 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 377 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 378 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS) 379 380 /* FEAT_DIT: Data Independent Timing instructions */ 381 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 382 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT) 383 384 /* FEAT_SYS_REG_TRACE */ 385 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT, 386 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS) 387 388 /* FEAT_TRF: TraceFilter */ 389 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 390 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS) 391 392 /* FEAT_NV2: Enhanced Nested Virtualization */ 393 CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 394 ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U) 395 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 396 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) 397 398 /* FEAT_BRBE: Branch Record Buffer Extension */ 399 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 400 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS) 401 402 /* FEAT_TRBE: Trace Buffer Extension */ 403 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 404 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS) 405 406 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 407 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 408 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U) 409 410 /* FEAT_SMEx: Scalar Matrix Extension */ 411 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 412 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS) 413 414 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 415 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) 416 417 /******************************************************************************* 418 * Function to get hardware granularity support 419 ******************************************************************************/ 420 421 __attribute__((always_inline)) 422 static inline bool is_feat_tgran4K_present(void) 423 { 424 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 425 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 426 return (tgranx < 8U); 427 } 428 429 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 430 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED) 431 432 __attribute__((always_inline)) 433 static inline bool is_feat_tgran64K_present(void) 434 { 435 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 436 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 437 return (tgranx < 8U); 438 } 439 440 /* FEAT_PMUV3 */ 441 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 442 ID_AA64DFR0_PMUVER_MASK, 1U) 443 444 /* FEAT_MTPMU */ 445 __attribute__((always_inline)) 446 static inline bool is_feat_mtpmu_present(void) 447 { 448 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 449 ID_AA64DFR0_MTPMU_MASK); 450 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 451 } 452 453 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 454 455 #endif /* ARCH_FEATURES_H */ 456