fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), th

fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), that's just a flush, but on FVP that also unregisters
the console. On HW_ASSISTED_COHERENCY=0 builds, this has the potential
to break and prevent any EL3 output after a SYSTEM_SUSPEND.

This happens because the calls to
console_unregister()/console_register() will overwrite the value of the
console_list variable in drivers/console/multi_console.c. They are
only called on a system level suspend. The bug happens when the core
wakes up. The console will be registered again as part of the
pwr_domain_suspend_finish() call. However, this call happens before the
data caches have been enabled in psci_do_pwrup_cache_maintenance(). As a
result, the write to console_list will not be reflected in the L2 cache
and other cores will not be able to read the new value.

The fix is to not unregister the console like other Arm platforms -
we don't need to reinitialise the console so there's nothing to do.

A nice side effect is that arm_console_runtime_end() no longer needs to
be weak.

Change-Id: Ibbdd4b22bad0d8f1dbd63c60ee0294d889a349a4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add

Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add DSU support
docs(rdaspen): introduce rdaspen docs
feat(rdaspen): enable tbb on rd-aspen platform
feat(gicv3): add GIC-720AE model id
feat(rdaspen): add BL31 for RD-Aspen platform
feat(rdaspen): introduce Arm RD-Aspen platform

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Merge "fix(gpt): fix fill_l1_cont_desc() function" into integration

feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the

feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the DSU-120AE TRM.
- Enable the `PRESERVE_DSU_PMU_REGS` flag to save and restore DSU
cluster PMU registers across cluster power cycles.

Change-Id: I7f820981cd164a689324a525b506c2979bddb572
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library in

feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library initialization for MbedTLS
library.

Change-Id: I7940952c152b0243a91b38804cf16d3050ec2d4b
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL ima

feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL image information that gets
used by BL2 to load the images

Change-Id: I5f389c4a6ef9bc106b3b29c9aecbd890d91d99b3
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* C

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)

It also adds:
* FW_CONFIG and HW_CONFIG device trees

Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always ret

feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always returns
success as currently no notification is required.

Change-Id: I0e0813327af4f55e0aef12bd80a472d103ea317d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when E

refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when ENABLE_FEAT_RAS=0 will not produce any side
effects and the code will never be called. So we can always build the
files to remove the circular check.

Change-Id: I44f90daa193c9b2c853f3fd9b54b67ccc7bace83
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPO

fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPORT will also be used so it must be set.

Change-Id: I0fed6ef40eee82a3624de7bc0c85f5662af4ca3a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SP

Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry
feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
feat(spmd): get spmc manifest from xferlist

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feat(tc): bump SPMC version to FF-A v1.3 TC platform

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I196a0eb1bedb8bcc35b4524f04ea75f8c832a7f9

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@ar

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I51d29832d8011dbdc9945f153805ba9b2b8663e7

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Merge "fix(spm): change the SMMUv3TestEngine being used" into integration

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
re

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
refactor: unify blx_setup() and blx_main()
fix(bl2): unify the BL2 EL3 and RME entrypoints

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feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR mac

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR macros.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0494738b9978ad72b3316a24d7811096c53f952b

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