1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 70 ENABLE_FEAT_CPA2 := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96ifeq (${ENABLE_RME},1) 97 ENABLE_FEAT_MEC := 2 98 RMMD_ENABLE_IDE_KEY_PROG := 1 99endif 100 101# The FVP platform depends on this macro to build with correct GIC driver. 102$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 103 104# Pass FVP_CLUSTER_COUNT to the build system. 105$(eval $(call add_define,FVP_CLUSTER_COUNT)) 106 107# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 108$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 109 110# Pass FVP_MAX_PE_PER_CPU to the build system. 111$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 112 113# Pass FVP_GICR_REGION_PROTECTION to the build system. 114$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 115 116# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 117$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 118 119# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 120# choose the CCI driver , else the CCN driver 121ifeq ($(FVP_CLUSTER_COUNT), 0) 122$(error "Incorrect cluster count specified for FVP port") 123else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 124FVP_INTERCONNECT_DRIVER := FVP_CCI 125else 126FVP_INTERCONNECT_DRIVER := FVP_CCN 127endif 128 129$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 130 131# Choose the GIC sources depending upon the how the FVP will be invoked 132ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 133USE_GIC_DRIVER := 3 134 135# The GIC model (GIC-600 or GIC-500) will be detected at runtime 136GICV3_SUPPORT_GIC600 := 1 137GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 138 139FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 140ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 141BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 142endif 143 144ifeq (${HW_ASSISTED_COHERENCY}, 0) 145FVP_DT_PREFIX := fvp-base-gicv3-psci 146else 147FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 148endif 149else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 150USE_GIC_DRIVER := 5 151ENABLE_FEAT_GCIE := 1 152BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 153FVP_DT_PREFIX := fvp-base-gicv5-psci 154ifneq ($(SPD),none) 155 $(error Error: GICv5 is not compatible with SPDs) 156endif 157ifeq ($(ENABLE_RME),1) 158 $(error Error: GICv5 is not compatible with RME) 159endif 160else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 161USE_GIC_DRIVER := 2 162 163# No GICv4 extension 164GIC_ENABLE_V4_EXTN := 0 165$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 166 167FVP_DT_PREFIX := fvp-base-gicv2-psci 168else 169$(error "Incorrect GIC driver chosen on FVP port") 170endif 171 172ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 173FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 174else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 175FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 176 plat/arm/common/arm_ccn.c 177else 178$(error "Incorrect CCN driver chosen on FVP port") 179endif 180 181FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 182 plat/arm/board/fvp/fvp_security.c \ 183 plat/arm/common/arm_tzc400.c 184 185 186PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 187 -Iinclude/lib/psa 188 189 190PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 191 192FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 193 194ifeq (${ARCH}, aarch64) 195 196# select a different set of CPU files, depending on whether we compile for 197# hardware assisted coherency cores or not 198ifeq (${HW_ASSISTED_COHERENCY}, 0) 199# Cores used without DSU 200 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 201 lib/cpus/aarch64/cortex_a53.S \ 202 lib/cpus/aarch64/cortex_a57.S \ 203 lib/cpus/aarch64/cortex_a72.S \ 204 lib/cpus/aarch64/cortex_a73.S 205else 206# Cores used with DSU only 207 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 208 # AArch64-only cores 209 # TODO: add all cores to the appropriate lists 210 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 211 lib/cpus/aarch64/cortex_a65ae.S \ 212 lib/cpus/aarch64/cortex_a76.S \ 213 lib/cpus/aarch64/cortex_a76ae.S \ 214 lib/cpus/aarch64/cortex_a77.S \ 215 lib/cpus/aarch64/cortex_a78.S \ 216 lib/cpus/aarch64/cortex_a78_ae.S \ 217 lib/cpus/aarch64/cortex_a78c.S \ 218 lib/cpus/aarch64/cortex_a710.S \ 219 lib/cpus/aarch64/cortex_a715.S \ 220 lib/cpus/aarch64/cortex_a720.S \ 221 lib/cpus/aarch64/cortex_a720_ae.S \ 222 lib/cpus/aarch64/neoverse_n1.S \ 223 lib/cpus/aarch64/neoverse_n2.S \ 224 lib/cpus/aarch64/neoverse_v1.S \ 225 lib/cpus/aarch64/neoverse_e1.S \ 226 lib/cpus/aarch64/cortex_x2.S \ 227 lib/cpus/aarch64/cortex_x4.S 228 endif 229 # AArch64/AArch32 cores 230 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 231 lib/cpus/aarch64/cortex_a75.S 232endif 233 234#Include all CPUs to build to support all-errata build. 235ifeq (${ENABLE_ERRATA_ALL},1) 236 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 237 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 238 lib/cpus/aarch64/cortex_a510.S \ 239 lib/cpus/aarch64/cortex_a520.S \ 240 lib/cpus/aarch64/cortex_a725.S \ 241 lib/cpus/aarch64/cortex_x1.S \ 242 lib/cpus/aarch64/cortex_x3.S \ 243 lib/cpus/aarch64/cortex_x925.S \ 244 lib/cpus/aarch64/neoverse_n3.S \ 245 lib/cpus/aarch64/neoverse_v2.S \ 246 lib/cpus/aarch64/neoverse_v3.S 247endif 248 249#Build AArch64-only CPUs with no FVP model yet. 250ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 251 ERRATA_SME_POWER_DOWN := 1 252 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 253 lib/cpus/aarch64/c1_nano.S \ 254 lib/cpus/aarch64/c1_ultra.S \ 255 lib/cpus/aarch64/c1_premium.S \ 256 lib/cpus/aarch64/canyon.S \ 257 lib/cpus/aarch64/veymont.S 258endif 259 260else 261FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 262 lib/cpus/aarch32/cortex_a57.S \ 263 lib/cpus/aarch32/cortex_a53.S 264endif 265 266BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 267 drivers/arm/sp805/sp805.c \ 268 drivers/delay_timer/delay_timer.c \ 269 drivers/io/io_semihosting.c \ 270 lib/semihosting/semihosting.c \ 271 lib/semihosting/${ARCH}/semihosting_call.S \ 272 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 273 plat/arm/board/fvp/fvp_bl1_setup.c \ 274 plat/arm/board/fvp/fvp_cpu_pwr.c \ 275 plat/arm/board/fvp/fvp_err.c \ 276 plat/arm/board/fvp/fvp_io_storage.c \ 277 plat/arm/board/fvp/fvp_topology.c \ 278 ${FVP_CPU_LIBS} \ 279 ${FVP_INTERCONNECT_SOURCES} 280 281ifeq (${USE_SP804_TIMER},1) 282BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 283else 284BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 285endif 286 287 288BL2_SOURCES += drivers/arm/sp805/sp805.c \ 289 drivers/io/io_semihosting.c \ 290 lib/utils/mem_region.c \ 291 lib/semihosting/semihosting.c \ 292 lib/semihosting/${ARCH}/semihosting_call.S \ 293 plat/arm/board/fvp/fvp_bl2_setup.c \ 294 plat/arm/board/fvp/fvp_err.c \ 295 plat/arm/board/fvp/fvp_io_storage.c \ 296 plat/arm/common/arm_nor_psci_mem_protect.c \ 297 ${FVP_SECURITY_SOURCES} 298 299 300ifeq (${COT_DESC_IN_DTB},1) 301BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 302endif 303 304ifeq (${ENABLE_RME},1) 305BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 306 plat/arm/board/fvp/fvp_cpu_pwr.c 307 308BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 309 plat/arm/board/fvp/fvp_realm_attest_key.c \ 310 plat/arm/board/fvp/fvp_el3_token_sign.c \ 311 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 312 plat/arm/common/plat_rmm_mem_carveout.c 313endif 314 315ifneq (${ENABLE_FEAT_RNG_TRAP},0) 316BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 317endif 318 319ifeq (${RESET_TO_BL2},1) 320BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 321 plat/arm/board/fvp/fvp_cpu_pwr.c \ 322 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 323 ${FVP_CPU_LIBS} \ 324 ${FVP_INTERCONNECT_SOURCES} 325endif 326 327ifeq (${USE_SP804_TIMER},1) 328BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 329endif 330 331BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 332 ${FVP_SECURITY_SOURCES} 333 334ifeq (${USE_SP804_TIMER},1) 335BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 336endif 337 338BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 339 drivers/arm/smmu/smmu_v3.c \ 340 drivers/delay_timer/delay_timer.c \ 341 drivers/cfi/v2m/v2m_flash.c \ 342 lib/utils/mem_region.c \ 343 plat/arm/board/fvp/fvp_bl31_setup.c \ 344 plat/arm/board/fvp/fvp_console.c \ 345 plat/arm/board/fvp/fvp_pm.c \ 346 plat/arm/board/fvp/fvp_topology.c \ 347 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 348 plat/arm/board/fvp/fvp_cpu_pwr.c \ 349 plat/arm/common/arm_nor_psci_mem_protect.c \ 350 ${FVP_CPU_LIBS} \ 351 ${FVP_INTERCONNECT_SOURCES} \ 352 ${FVP_SECURITY_SOURCES} 353 354# Support for fconf in BL31 355# Added separately from the above list for better readability 356ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 357BL31_SOURCES += lib/fconf/fconf.c \ 358 lib/fconf/fconf_dyn_cfg_getter.c \ 359 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 360 361BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 362 363ifeq (${SEC_INT_DESC_IN_FCONF},1) 364BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 365endif 366 367endif 368 369ifeq (${USE_SP804_TIMER},1) 370BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 371else 372BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 373endif 374 375# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 376FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 377 378FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 379$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 380HW_CONFIG := ${FVP_HW_CONFIG} 381 382HW_CONFIG_BASE ?= 0x82000000 383 384# Set default initrd base 128MiB offset of the default kernel address in FVP 385INITRD_BASE ?= 0x90000000 386 387# Kernel base address supports Linux kernels before v5.7 388# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 389ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 390 PRELOADED_BL33_BASE ?= 0x80080000 391 ifeq (${RESET_TO_BL31},1) 392 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 393 endif 394endif 395 396ifeq (${TRANSFER_LIST}, 0) 397FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 398 ${PLAT}_fw_config.dts \ 399 ${PLAT}_tb_fw_config.dts \ 400 ${PLAT}_soc_fw_config.dts \ 401 ${PLAT}_nt_fw_config.dts \ 402 ) 403 404FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 405FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 406FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 407FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 408 409ifeq (${SPD},tspd) 410FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 411FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 412 413# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 414$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 415endif 416 417# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 418$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 419# Add the NT_FW_CONFIG to FIP and specify the same to certtool 420$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 421endif 422 423ifeq (${SPD},spmd) 424 425ifeq ($(ARM_SPMC_MANIFEST_DTS),) 426ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 427endif 428 429FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 430FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 431 432# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 433$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 434endif 435 436# Add the HW_CONFIG to FIP and specify the same to certtool 437$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 438 439ifeq (${TRANSFER_LIST}, 1) 440 441ifeq ($(RESET_TO_BL31), 1) 442FW_HANDOFF_SIZE := 20000 443 444TRANSFER_LIST_DTB_OFFSET := 0x20 445$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 446endif 447endif 448 449ifeq (${HOB_LIST}, 1) 450include lib/hob/hob.mk 451endif 452 453# Enable dynamic mitigation support by default 454DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 455 456ifneq (${ENABLE_FEAT_AMU},0) 457BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 458 lib/cpus/aarch64/cpuamu_helpers.S 459 460ifeq (${HW_ASSISTED_COHERENCY}, 1) 461BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 462 lib/cpus/aarch64/neoverse_n1_pubsub.c 463endif 464endif 465 466ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 467 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 468 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 469 endif 470 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 471 plat/arm/board/fvp/aarch64/fvp_ea.c 472endif 473 474ifneq (${ENABLE_STACK_PROTECTOR},0) 475PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 476endif 477 478# Enable the dynamic translation tables library. 479ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 480 ifeq (${ARCH},aarch32) 481 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 482 else # AArch64 483 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 484 endif 485endif 486 487ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 488 ifeq (${ARCH},aarch32) 489 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 490 else # AArch64 491 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 492 ifeq (${SPD},tspd) 493 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 494 endif 495 endif 496endif 497 498ifeq (${USE_DEBUGFS},1) 499 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 500endif 501 502# Add support for platform supplied linker script for BL31 build 503$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 504 505ifneq (${RESET_TO_BL2}, 0) 506 override BL1_SOURCES = 507endif 508 509include plat/arm/board/common/board_common.mk 510include plat/arm/common/arm_common.mk 511 512ifeq (${MEASURED_BOOT},1) 513BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 514 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 515 lib/psa/measured_boot.c 516 517BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 518 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 519 lib/psa/measured_boot.c 520endif 521 522ifeq (${DRTM_SUPPORT}, 1) 523BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 524 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 525 plat/arm/board/fvp/fvp_drtm_err.c \ 526 plat/arm/board/fvp/fvp_drtm_measurement.c \ 527 plat/arm/board/fvp/fvp_drtm_stub.c \ 528 plat/arm/common/arm_dyn_cfg.c \ 529 plat/arm/board/fvp/fvp_err.c 530endif 531 532ifeq (${TRUSTED_BOARD_BOOT}, 1) 533BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 534BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 535 536# FVP being a development platform, enable capability to disable Authentication 537# dynamically if TRUSTED_BOARD_BOOT is set. 538DYN_DISABLE_AUTH := 1 539endif 540 541ifeq (${SPMC_AT_EL3}, 1) 542PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 543endif 544 545PSCI_OS_INIT_MODE := 1 546 547ifeq (${SPD},spmd) 548BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 549endif 550 551# Test specific macros, keep them at bottom of this file 552$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 553ifeq (${PLATFORM_TEST_EA_FFH}, 1) 554 ifeq (${FFH_SUPPORT}, 0) 555 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 556 endif 557 558endif 559 560PLATFORM_TEST_RAS_FFH ?= 0 561$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 562ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 563 ifeq (${ENABLE_FEAT_RAS}, 0) 564 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 565 endif 566 ifeq (${SDEI_SUPPORT}, 0) 567 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 568 endif 569 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 570 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 571 endif 572endif 573 574$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 575ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 576 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 577 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 578 endif 579 ifeq (${ENABLE_SPMD_LP}, 0) 580 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 581 endif 582 ifeq (${ENABLE_FEAT_RAS}, 0) 583 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 584 endif 585 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 586 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 587 endif 588endif 589 590ifeq (${ERRATA_ABI_SUPPORT}, 1) 591include plat/arm/board/fvp/fvp_cpu_errata.mk 592endif 593 594# Build macro necessary for running SPM tests on FVP platform 595$(eval $(call add_define,PLAT_TEST_SPM)) 596 597ifeq (${LFA_SUPPORT},1) 598BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 599endif 600 601# This is set to 1 by default when the firmware update 602# support is enabled. Since the BL2 image is not updatable 603ifeq ($(PSA_FWU_SUPPORT),1) 604 SEPARATE_BL2_FIP := 1 605endif 606 607ifeq (${TRANSFER_LIST}, 0) 608ifeq (${SEPARATE_BL2_FIP},1) 609$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 610$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 611else 612$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 613$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 614endif 615endif 616