fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_r

fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_reg() instead of the register offset which resulted in the
incorrect register being modified.

Change-Id: I1063b7d1e17037f60a745ceb6653cd3419ec6a67
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL

feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL32 build flag is set.

Enable decryption support for FVP through setting the DECRYPTION_SUPPORT
build flag. "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated
decryption using AES-GCM algorithm.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Iebc3b360b4a0dc0d933b816d28015ac551b79405

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fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platfor

fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platform.mk. That makes a circular dependency when a file needs to be
compiled based on the flag's value.

Well, FEAT_RAS is mandatory from v8.2 and platforms that set
ARM_ARCH_{MAJOR, MINOR} such need not check for its presence - it will
be present. So remove the check to remove the dependency.

Change-Id: I68db83347e6bc04b7ff3b67f6c3e54921641db23
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan

feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan

feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_trans

feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_transfer_list_dyn_cfg_init().

Since there is no standard tag_id defined for TB_FW_CONFIG in the
transfer list, define PLAT_ARM_TB_FW_CONFIG_TL_TAG as a platform-specific
identifier to load TB_FW_CONFIG.

With this change, BL2 can load the SP_PKGs specified in TB_FW_CONFIG.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I2470c1ef3bf2bf921d0de1fff541565df13eaee4

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fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off

fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd584172

chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd58417297507eaa9b24e55fc36de67bd16b716
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properti

fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properties of
Secure Partitions managed by SPMC. This happens even before the normal
world is booted.

Hafnium SPMC mistakes this as a FF-A invocation from NWd. As per FF-A
version negotiation protocol, Hafnium locks the version of NWd to v1.3
whereas the NWd never got an opportunity to register its own framework
version.

This patch performs early exit from the helper utility to give NWd
endpoint/Hypervisor an opportunity to register its FF-A version with
SPM. We intentionally do not remove the helper utility as it will be
used in a different patchset for a new anticipated feature.

Change-Id: I54087bd2ad53355afeb024c0e4df6a5ba7ab125a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare

fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an
unsigned value is never true. power_level < 0ULL.

Change-Id: Ia06f8729ac78b05046402e29e30f55c5f0b9e215
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boya

fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan

fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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Merge "docs: deprecate Arm RD1AE platform" into integration

docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst t

docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst to list RD1AE with deleted version set to
TBD.
Drop from the deprecated table platforms that were already deleted in
v2.13 (TC2, fvp_r, SGI-575, RD-N1-Edge, RD-V1, RD-V1-MC).

Change-Id: Ia334a1901fbf303e876e85c8075e2ac7e3fa0d67
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(el3-runtime): allow RNDR access at EL3 even when RNG_TRAP is enabled

RNG_TRAP will also trap RNDR accesses at EL3 which we don't want as we
have no way to handle nested exceptions. Clear the tra

fix(el3-runtime): allow RNDR access at EL3 even when RNG_TRAP is enabled

RNG_TRAP will also trap RNDR accesses at EL3 which we don't want as we
have no way to handle nested exceptions. Clear the trap with root
context to always allow access at EL3.

Change-Id: I6e4cd8b5a7730f6ffbeed912d9301877d271110d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(cpus): add support for venom cpu" into integration

Merge "fix(security): add clrbhb support" into integration

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)

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Merge "fix(arm): derive RMM bank size from payload" into integration

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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