feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the buil

feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the build switches from `cortex_a35.S` to
`cortex_a320.S`, maintaining compatibility with existing A35-based
designs.

Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM
on Cortex-A320 platforms so U-Boot and other non-secure software
can safely access these regions:

* **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB),
attrs `MT_DEVICE | MT_RW | MT_NS`
* **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB),
attrs `MT_MEMORY | MT_RW | MT_NS`

Enable GICv3 with GIC-600 when building for Cortex-A320 (retain
GICv2/GIC-400 for Cortex-A35):

* Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use
the Cortex-A320 MPIDR_EL1 affinity layout.
* Add an A320-specific core-position routine in assembly guarded by
`CORSTONE1000_CORTEX_A320`.
* Switch to the GICv3 driver with GIC-600 extensions: update GIC base
addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`,
`GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`.

These changes prepare the platform for Cortex-A320 integration and
ensure correct GIC configuration and secondary-core bring-up, while
preserving A35 behavior.

Change-Id: Ief03dd528e67918e160d5b42ad1344b0ba3440f8
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Signed-off-by: Michael Safwat <michael.safwat@arm.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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Merge changes I9375fad3,Ie072f9fe into integration

* changes:
refactor(fvp): use SZ_* defs fr event log
fix(rme): increase worst-case event size

Merge "fix(fvp): fully remove FVP_Foundation" into integration

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Sign

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <h

refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case siz

fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case size to account for this.

Change-Id: Ie072f9fe1ea5617c030556fae4c8c893cfefc4e0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "hm/evlog" into integration

* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile me

Merge changes from topic "hm/evlog" into integration

* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile measured boot
refactor(juno): use crypto-agile measured boot
refactor(rpi3): use crypto-agile measured boot
refactor(fvp): use crypto-agile measured boot
feat(measured-boot): enable dynamic hash provisioning
feat: add TPM/TCG hashing helper to crypto module
chore: bump event log library

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refactor(juno): use crypto-agile measured boot

Update the Juno measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selecti

refactor(juno): use crypto-agile measured boot

Update the Juno measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I9bca6c9f2a6f3507cea5ced7c2ab83ee5a4c1a91
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection

refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I4128a0c66a56df6c473c47a577d86cd38bf057f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(neoverse-rd): set the correct Arm version for rdn2" into integration

Merge "feat(fvp): load SP_PKGs with TRANSFER_LIST" into integration

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement

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Merge changes from topic "image_decryption" into integration

* changes:
feat(fvp): extend image decryption support for FVP
fix(io): add NULL check for spec io_open FIP

Merge "fix(tc): correct register write in rng trap handler" into integration

Merge "fix: remove circular dependency on ENABLE_FEAT_RAS" into integration

Merge changes from topic "tc-lsc-25-cpu-libs" into integration

* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri

feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.

Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f

feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f91
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters" into integration

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I1

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I15556fde3740056b1eb81138d19635b507064abf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(

Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(tspd): don't forward declare tsp_vectors_t
fix(cpufeat): drop feature_panic() as unused

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fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_r

fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_reg() instead of the register offset which resulted in the
incorrect register being modified.

Change-Id: I1063b7d1e17037f60a745ceb6653cd3419ec6a67
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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