1# 2# Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9ARM_ARCH_MAJOR := 8 10ARM_ARCH_MINOR := 2 11 12# platform configs 13ENABLE_CONSOLE_SPE := 1 14$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 15 16ENABLE_STRICT_CHECKING_MODE := 1 17$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) 18 19USE_GPC_DMA := 1 20$(eval $(call add_define,USE_GPC_DMA)) 21 22RESET_TO_BL31 := 1 23 24PROGRAMMABLE_RESET_ADDRESS := 1 25 26COLD_BOOT_SINGLE_CPU := 1 27 28# platform settings 29TZDRAM_BASE := 0x40000000 30$(eval $(call add_define,TZDRAM_BASE)) 31 32MAX_XLAT_TABLES := 25 33$(eval $(call add_define,MAX_XLAT_TABLES)) 34 35MAX_MMAP_REGIONS := 30 36$(eval $(call add_define,MAX_MMAP_REGIONS)) 37 38# enable RAS handling 39HANDLE_EA_EL3_FIRST_NS := 1 40 41# platform files 42PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ 43 -I${SOC_DIR}/drivers/include 44 45BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \ 46 drivers/ti/uart/aarch64/16550_console.S \ 47 lib/cpus/aarch64/denver.S \ 48 ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \ 49 ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \ 50 ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \ 51 ${TEGRA_DRIVERS}/smmu/smmu.c \ 52 ${SOC_DIR}/drivers/mce/mce.c \ 53 ${SOC_DIR}/drivers/mce/nvg.c \ 54 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 55 ${SOC_DIR}/drivers/se/se.c \ 56 ${SOC_DIR}/plat_memctrl.c \ 57 ${SOC_DIR}/plat_psci_handlers.c \ 58 ${SOC_DIR}/plat_setup.c \ 59 ${SOC_DIR}/plat_secondary.c \ 60 ${SOC_DIR}/plat_sip_calls.c \ 61 ${SOC_DIR}/plat_smmu.c \ 62 ${SOC_DIR}/plat_trampoline.S 63 64ifeq (${USE_GPC_DMA}, 1) 65BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c 66endif 67 68ifeq (${ENABLE_CONSOLE_SPE},1) 69BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S 70endif 71 72# RAS sources 73ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 74BL31_SOURCES += ${SOC_DIR}/plat_ras.c 75endif 76 77# SPM dispatcher 78ifeq (${SPD},spmd) 79include lib/libfdt/libfdt.mk 80# sources to support spmd 81BL31_SOURCES += plat/common/plat_spmd_manifest.c \ 82 ${LIBFDT_SRCS} 83 84BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 85endif 86