Merge "feat(pie/por): support permission indirection and overlay" into integration

feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the

feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the page
tables the PTEs contain indexes into an array of permissions stored in
system registers, allowing greater flexibility and density of encoding.

Enable access to these features for EL2 and below, context switching the
newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E
are separately discoverable we have separate build time options for
enabling them, but note that there is overlap in the registers that they
implement and the enable bit required for lower EL access.

Change the FVP platform to default to handling them as dynamic options so
the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Icf89e444e39e1af768739668b505661df18fb234

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fix(psci): potential array overflow with cpu on

Fix coverity finding in psci_cpu_on, in which target_idx is directly
assigned the return value from plat_core_pos_by_mpidr. If the latter
returns a ne

fix(psci): potential array overflow with cpu on

Fix coverity finding in psci_cpu_on, in which target_idx is directly
assigned the return value from plat_core_pos_by_mpidr. If the latter
returns a negative or large positive value, it can trigger an out of
bounds overflow for the psci_cpu_pd_nodes array.

>>>> CID 382009: (OVERRUN)
>>>> Overrunning callee's array of size 8 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_spin_lock_cpu".
> 80 psci_spin_lock_cpu(target_idx);

>>>> CID 382009: (OVERRUN)
>>>> Overrunning callee's array of size 8 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_spin_unlock_cpu".
> 160 psci_spin_unlock_cpu(target_idx);

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ibc46934e9ca7fdcaeebd010e5c6954dcf2dcf8c7

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feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

Change-Id: I4750e774732218ee669dceb734cd107f46b78492
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

C

feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(psci): remove unreachable switch/case blocks

The PSCI function dispatcher switch/case is split up between 32-bit and
64-bit function IDs, based on bit 30 of the encoding. This bit just
encodes t

fix(psci): remove unreachable switch/case blocks

The PSCI function dispatcher switch/case is split up between 32-bit and
64-bit function IDs, based on bit 30 of the encoding. This bit just
encodes the maximum size of the arguments, not necessarily whether they
are used from AArch64 or AArch32. So while some functions exist in both
worlds (CPU_ON, for instance), some functions take no or only 32-bit
arguments (CPU_OFF, PSCI_FEATURES), so they only exist as a 32-bit
function call.

Commit b88a4416b5e5 ("feat(psci): add support for PSCI_SET_SUSPEND_MODE"
, gerrit ID Iebf65f5f7846aef6b8643ad6082db99b4dcc4bef) and commit
9a70e69e0598 ("feat(psci): update PSCI_FEATURES", gerrit ID
I5da8a989b53419ad2ab55b73ddeee6e882c25554) introduced two "case"
sections for 32-bit function IDs in the 64-bit branch, which will never
trigger. The one small extra case caused the sun50i_a64 DEBUG build to
go beyond its RAM limit.

Removed the redundant switch/case blocks, to make sun50i_a64 build
again.

Change-Id: Ic65b7403d128837296a0c3af42c6f23f9f57778e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function

feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SVE specific setup.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I1caaba2216e8e2a651452254944a003607503216
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second fun

feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.

Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.

Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEA

Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEATURES
feat(psci): add support for OS-initiated mode
feat(psci): add support for PSCI_SET_SUSPEND_MODE
build(psci): add build option for OS-initiated mode
docs(psci): add design proposal for OS-initiated mode

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refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h)

refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h), which get updated to cover the v1p1 variant as well.

Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_A

refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.

Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.

Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
ref

Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor

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Merge "refactor(fvp): use RSS API to retrieve attestation token and key" into integration

fix(cpus): use hint instruction for "tsb csync"

The "tsb csync" instruction is part of the Armv8.4 architecture
extension, and is not supported by many older assemblers.
We already cater for this in

fix(cpus): use hint instruction for "tsb csync"

The "tsb csync" instruction is part of the Armv8.4 architecture
extension, and is not supported by many older assemblers.
We already cater for this in lib/extensions/trbe/trbe.c, where we use
the equivalent "hint #18" encoding for this, but use the new mnemonic
in the Cortex-A510 CPU support code.

Replace "tsb csync" with the hint encoding there as well, to support
building with older binutils versions.

Change-Id: Idf39f5c6c4dbf72802c3c120047b8bc499145e3b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): use RSS API to retrieve attestation token and key

Retrieved the platform attestation token and delegated realm attestation
key through the PSA delegated attestation layer.

Even thoug

refactor(fvp): use RSS API to retrieve attestation token and key

Retrieved the platform attestation token and delegated realm attestation
key through the PSA delegated attestation layer.

Even though FVP doesn't support RSS hardware today, it can still
leverage the RSS implementation of these PSA interfaces in their mocking
form (see PLAT_RSS_NOT_SUPPORTED).

Therefore, platform APIs now call these PSA interfaces instead of
directly providing these hardcoded values.

Change-Id: I31d0ca58f6f1a444f513d954da4e3e67757321ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(cpufeat): align FEAT_SEL2 to new feature handling

In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
ali

refactor(cpufeat): align FEAT_SEL2 to new feature handling

In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.

Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED

At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime

refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED

At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by
splitting get_armv8_4_feat_nv_support() into an ID register reading
function and a second function to report the support status. That
function considers both build time settings and runtime information
(if needed), and is used before we access the VNCR_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_nv2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED

At the moment we only support FEAT_TWED to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime d

refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED

At the moment we only support FEAT_TWED to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting
is_armv8_6_twed_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we set the trap delay time.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I58626230ef0af49886c0a197abace01e81f661d2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED

At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runti

refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED

At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting
is_armv8_0_feat_csv2_2_present() into an ID register reading function
and a second function to report the support status. That function
considers both build time settings and runtime information (if needed),
and is used before we access the SCXTNUM_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_csv2_2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED

At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED

At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting
is_feat_ecv_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access the CNTPOFF_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_ecv_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED

At the moment we only support access to the trace unit by system
registers (SYS_REG_TRACE) to be either unconditionally compiled in, or

refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED

At the moment we only support access to the trace unit by system
registers (SYS_REG_TRACE) to be either unconditionally compiled in, or
to be not supported at all.

Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by
adding is_feat_sys_reg_trace_supported(). That function considers both
build time settings and runtime information (if needed), and is used
before we access SYS_REG_TRACE related registers.

The FVP platform decided to compile in support unconditionally (=1),
even though this is an optional feature, so it is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.

Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 1827440

Cortex-A78C erratum 1827440 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set CPUACTLR2_EL1[2], w

fix(cpus): workaround for Cortex-A78C erratum 1827440

Cortex-A78C erratum 1827440 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set CPUACTLR2_EL1[2], which forces atomic store
operations to write-back memory to be performed in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7

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fix(cpus): workaround for Cortex-A78C erratum 1827430

Cortex-A78C erratum 1827430 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set the CPUECTLR_EL1[53

fix(cpus): workaround for Cortex-A78C erratum 1827430

Cortex-A78C erratum 1827430 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set the CPUECTLR_EL1[53] to 1, which disables
allocation of splintered pages in the L2 TLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426

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feat(psci): update PSCI_FEATURES

This patch updates the PSCI_FEATURES handler to indicate support for
OS-initiated mode per section 5.15.2 of the PSCI spec (DEN0022D.b) based
on the value of `FF_SUP

feat(psci): update PSCI_FEATURES

This patch updates the PSCI_FEATURES handler to indicate support for
OS-initiated mode per section 5.15.2 of the PSCI spec (DEN0022D.b) based
on the value of `FF_SUPPORTS_OS_INIT_MODE`, which is conditionally
enabled by the `PSCI_OS_INIT_MODE` build option.

Change-Id: I5da8a989b53419ad2ab55b73ddeee6e882c25554
Signed-off-by: Wing Li <wingers@google.com>

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feat(psci): add support for OS-initiated mode

This patch adds a `psci_validate_state_coordination` function that is
called by `psci_cpu_suspend_start` in OS-initiated mode.

This function validates

feat(psci): add support for OS-initiated mode

This patch adds a `psci_validate_state_coordination` function that is
called by `psci_cpu_suspend_start` in OS-initiated mode.

This function validates the request per sections 4.2.3.2, 5.4.5, and 6.3
of the PSCI spec (DEN0022D.b):
- The requested power states are consistent with the system's state
- The calling core is the last running core at the requested power level

This function differs from `psci_do_state_coordination` in that:
- The `psci_req_local_pwr_states` map is not modified if the request
were to be denied
- The `state_info` argument is never modified since it contains the
power states requested by the calling OS

This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.

Change-Id: I667041c842d2856e9d128c98db4d5ae4e4552df3
Signed-off-by: Wing Li <wingers@google.com>

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