1/* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20.globl cortex_a78_reset_func 21.globl cortex_a78_core_pwr_dwn 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 28 mrs x1, CORTEX_A78_ACTLR2_EL1 29 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 30 msr CORTEX_A78_ACTLR2_EL1, x1 31workaround_reset_end cortex_a78, ERRATUM(1688305) 32 33check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) 34 35workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 36 /* Set bit 2 in ACTLR2_EL1 */ 37 mrs x1, CORTEX_A78_ACTLR2_EL1 38 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 39 msr CORTEX_A78_ACTLR2_EL1, x1 40workaround_reset_end cortex_a78, ERRATUM(1821534) 41 42check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) 43 44workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 45 /* Set bit 8 in ECTLR_EL1 */ 46 mrs x1, CORTEX_A78_CPUECTLR_EL1 47 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 48 msr CORTEX_A78_CPUECTLR_EL1, x1 49workaround_reset_end cortex_a78, ERRATUM(1941498) 50 51check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) 52 53workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 54 msr S3_6_c15_c8_0, xzr 55 ldr x0, =0x10E3900002 56 msr S3_6_c15_c8_2, x0 57 ldr x0, =0x10FFF00083 58 msr S3_6_c15_c8_3, x0 59 ldr x0, =0x2001003FF 60 msr S3_6_c15_c8_1, x0 61 62 mov x0, #1 63 msr S3_6_c15_c8_0, x0 64 ldr x0, =0x10E3800082 65 msr S3_6_c15_c8_2, x0 66 ldr x0, =0x10FFF00083 67 msr S3_6_c15_c8_3, x0 68 ldr x0, =0x2001003FF 69 msr S3_6_c15_c8_1, x0 70 71 mov x0, #2 72 msr S3_6_c15_c8_0, x0 73 ldr x0, =0x10E3800200 74 msr S3_6_c15_c8_2, x0 75 ldr x0, =0x10FFF003E0 76 msr S3_6_c15_c8_3, x0 77 ldr x0, =0x2001003FF 78 msr S3_6_c15_c8_1, x0 79workaround_reset_end cortex_a78, ERRATUM(1951500) 80 81check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) 82 83workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 84 ldr x0,=0x5 85 msr S3_6_c15_c8_0,x0 86 ldr x0,=0xEEE10A10 87 msr S3_6_c15_c8_2,x0 88 ldr x0,=0xFFEF0FFF 89 msr S3_6_c15_c8_3,x0 90 ldr x0,=0x0010F000 91 msr S3_6_c15_c8_4,x0 92 ldr x0,=0x0010F000 93 msr S3_6_c15_c8_5,x0 94 ldr x0,=0x40000080023ff 95 msr S3_6_c15_c8_1,x0 96 ldr x0,=0x6 97 msr S3_6_c15_c8_0,x0 98 ldr x0,=0xEE640F34 99 msr S3_6_c15_c8_2,x0 100 ldr x0,=0xFFEF0FFF 101 msr S3_6_c15_c8_3,x0 102 ldr x0,=0x40000080023ff 103 msr S3_6_c15_c8_1,x0 104workaround_reset_end cortex_a78, ERRATUM(1952683) 105 106check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) 107 108workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 109 /* Apply the workaround. */ 110 mrs x1, CORTEX_A78_CPUECTLR_EL1 111 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV 112 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 113 msr CORTEX_A78_CPUECTLR_EL1, x1 114workaround_reset_end cortex_a78, ERRATUM(2132060) 115 116check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) 117 118workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 119 ldr x0, =0x5 120 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 121 ldr x0, =0x10F600E000 122 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 123 ldr x0, =0x10FF80E000 124 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 125 ldr x0, =0x80000000003FF 126 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 127workaround_reset_end cortex_a78, ERRATUM(2242635) 128 129check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) 130 131workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 132 /* Apply the workaround. */ 133 mrs x1, CORTEX_A78_ACTLR2_EL1 134 orr x1, x1, #BIT(0) 135 msr CORTEX_A78_ACTLR2_EL1, x1 136workaround_reset_end cortex_a78, ERRATUM(2376745) 137 138check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) 139 140workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 141 /* Apply the workaround. */ 142 mrs x1, CORTEX_A78_ACTLR2_EL1 143 orr x1, x1, #BIT(40) 144 msr CORTEX_A78_ACTLR2_EL1, x1 145workaround_reset_end cortex_a78, ERRATUM(2395406) 146 147check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) 148 149workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 150 /* Apply the workaround */ 151 mrs x1, CORTEX_A78_ACTLR5_EL1 152 bic x1, x1, #BIT(56) 153 orr x1, x1, #BIT(55) 154 msr CORTEX_A78_ACTLR5_EL1, x1 155workaround_reset_end cortex_a78, ERRATUM(2742426) 156 157check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) 158 159workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 160 /* dsb before isb of power down sequence */ 161 dsb sy 162workaround_runtime_end cortex_a78, ERRATUM(2772019) 163 164check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) 165 166workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 167 /* Apply the workaround */ 168 mrs x1, CORTEX_A78_ACTLR3_EL1 169 orr x1, x1, #BIT(47) 170 msr CORTEX_A78_ACTLR3_EL1, x1 171workaround_reset_end cortex_a78, ERRATUM(2779479) 172 173check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) 174 175workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 176#if IMAGE_BL31 177 /* 178 * The Cortex-X1 generic vectors are overridden to apply errata 179 * mitigation on exception entry from lower ELs. 180 */ 181 adr x0, wa_cve_vbar_cortex_a78 182 msr vbar_el3, x0 183#endif /* IMAGE_BL31 */ 184workaround_reset_end cortex_a78, CVE(2022, 23960) 185 186check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 187 188cpu_reset_func_start cortex_a78 189#if ENABLE_FEAT_AMU 190 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 191 mrs x0, actlr_el3 192 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 193 msr actlr_el3, x0 194 195 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 196 mrs x0, actlr_el2 197 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 198 msr actlr_el2, x0 199 200 /* Enable group0 counters */ 201 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 202 msr CPUAMCNTENSET0_EL0, x0 203 204 /* Enable group1 counters */ 205 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 206 msr CPUAMCNTENSET1_EL0, x0 207#endif 208cpu_reset_func_end cortex_a78 209 210 /* --------------------------------------------- 211 * HW will do the cache maintenance while powering down 212 * --------------------------------------------- 213 */ 214func cortex_a78_core_pwr_dwn 215 /* --------------------------------------------- 216 * Enable CPU power down bit in power control register 217 * --------------------------------------------- 218 */ 219 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 220 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 221 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 222 223 apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 224 225 isb 226 ret 227endfunc cortex_a78_core_pwr_dwn 228 229errata_report_shim cortex_a78 230 231 /* --------------------------------------------- 232 * This function provides cortex_a78 specific 233 * register information for crash reporting. 234 * It needs to return with x6 pointing to 235 * a list of register names in ascii and 236 * x8 - x15 having values of registers to be 237 * reported. 238 * --------------------------------------------- 239 */ 240.section .rodata.cortex_a78_regs, "aS" 241cortex_a78_regs: /* The ascii list of register names to be reported */ 242 .asciz "cpuectlr_el1", "" 243 244func cortex_a78_cpu_reg_dump 245 adr x6, cortex_a78_regs 246 mrs x8, CORTEX_A78_CPUECTLR_EL1 247 ret 248endfunc cortex_a78_cpu_reg_dump 249 250declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 251 cortex_a78_reset_func, \ 252 cortex_a78_core_pwr_dwn 253