1/* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a76ae.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24#if WORKAROUND_CVE_2022_23960 25 wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 26#endif /* WORKAROUND_CVE_2022_23960 */ 27 28check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 29 30workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31#if IMAGE_BL31 32 /* 33 * The Cortex-A76ae generic vectors are overridden to apply errata 34 * mitigation on exception entry from lower ELs. 35 */ 36 adr x0, wa_cve_vbar_cortex_a76ae 37 msr vbar_el3, x0 38 isb 39#endif /* IMAGE_BL31 */ 40workaround_reset_end cortex_a76ae, CVE(2022, 23960) 41 42cpu_reset_func_start cortex_a76ae 43cpu_reset_func_end cortex_a76ae 44 45errata_report_shim cortex_a76ae 46 47 /* ---------------------------------------------------- 48 * HW will do the cache maintenance while powering down 49 * ---------------------------------------------------- 50 */ 51func cortex_a76ae_core_pwr_dwn 52 /* --------------------------------------------------- 53 * Enable CPU power down bit in power control register 54 * --------------------------------------------------- 55 */ 56 mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 57 orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK 58 msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 59 isb 60 ret 61endfunc cortex_a76ae_core_pwr_dwn 62 63 /* --------------------------------------------- 64 * This function provides cortex_a76ae specific 65 * register information for crash reporting. 66 * It needs to return with x6 pointing to 67 * a list of register names in ascii and 68 * x8 - x15 having values of registers to be 69 * reported. 70 * --------------------------------------------- 71 */ 72.section .rodata.cortex_a76ae_regs, "aS" 73cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 74 .asciz "cpuectlr_el1", "" 75 76func cortex_a76ae_cpu_reg_dump 77 adr x6, cortex_a76ae_regs 78 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 79 ret 80endfunc cortex_a76ae_cpu_reg_dump 81 82declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 83 cortex_a76ae_core_pwr_dwn 84