1/* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* 28 * ERRATA_DSU_2313941: 29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 30 * Henceforth creating symbolic names to the already existing errata 31 * workaround functions to get them registered under the Errata Framework. 32 */ 33.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 36 37workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 38 /* Apply instruction patching sequence */ 39 ldr x0,=0x6 40 msr S3_6_c15_c8_0,x0 41 ldr x0,=0xF3A08002 42 msr S3_6_c15_c8_2,x0 43 ldr x0,=0xFFF0F7FE 44 msr S3_6_c15_c8_3,x0 45 ldr x0,=0x40000001003ff 46 msr S3_6_c15_c8_1,x0 47 ldr x0,=0x7 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xBF200000 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFEF0000 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003f3 54 msr S3_6_c15_c8_1,x0 55workaround_reset_end neoverse_n2, ERRATUM(2002655) 56 57check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 58 59workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 60 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 61 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 62 msr NEOVERSE_N2_CPUECTLR_EL1, x1 63workaround_reset_end neoverse_n2, ERRATUM(2025414) 64 65check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 66 67workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 68 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 69 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 70 msr NEOVERSE_N2_CPUACTLR_EL1, x1 71workaround_reset_end neoverse_n2, ERRATUM(2067956) 72 73check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 74 75workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 76 /* Apply instruction patching sequence */ 77 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 78 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 79 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 80 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 81workaround_reset_end neoverse_n2, ERRATUM(2138953) 82 83check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 0) 84 85workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 86 /* Apply instruction patching sequence */ 87 ldr x0,=0x3 88 msr S3_6_c15_c8_0,x0 89 ldr x0,=0xF3A08002 90 msr S3_6_c15_c8_2,x0 91 ldr x0,=0xFFF0F7FE 92 msr S3_6_c15_c8_3,x0 93 ldr x0,=0x10002001003FF 94 msr S3_6_c15_c8_1,x0 95 ldr x0,=0x4 96 msr S3_6_c15_c8_0,x0 97 ldr x0,=0xBF200000 98 msr S3_6_c15_c8_2,x0 99 ldr x0,=0xFFEF0000 100 msr S3_6_c15_c8_3,x0 101 ldr x0,=0x10002001003F3 102 msr S3_6_c15_c8_1,x0 103workaround_reset_end neoverse_n2, ERRATUM(2138956) 104 105check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 106 107 108workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 109 /* Apply instruction patching sequence */ 110 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 111 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 112 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 113workaround_reset_end neoverse_n2, ERRATUM(2138958) 114 115check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 116 117 118workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 119 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 120 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 121 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 122workaround_reset_end neoverse_n2, ERRATUM(2189731) 123 124check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 125 126workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 127 /* Apply instruction patching sequence */ 128 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 129 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 130 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 131 ldr x0, =0x2 132 msr S3_6_c15_c8_0, x0 133 ldr x0, =0x10F600E000 134 msr S3_6_c15_c8_2, x0 135 ldr x0, =0x10FF80E000 136 msr S3_6_c15_c8_3, x0 137 ldr x0, =0x80000000003FF 138 msr S3_6_c15_c8_1, x0 139workaround_reset_end neoverse_n2, ERRATUM(2242400) 140 141check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 142 143workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 144 /* Apply instruction patching sequence */ 145 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 146 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 147 msr NEOVERSE_N2_CPUACTLR_EL1, x1 148workaround_reset_end neoverse_n2, ERRATUM(2242415) 149 150check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 151 152 153workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 154 /* Apply instruction patching sequence */ 155 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 156 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 157 msr NEOVERSE_N2_CPUACTLR_EL1, x1 158workaround_reset_end neoverse_n2, ERRATUM(2280757) 159 160check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 161 162workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 163 /* Set bit 36 in ACTLR2_EL1 */ 164 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 165 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 166 msr NEOVERSE_N2_CPUACTLR2_EL1, x1 167workaround_runtime_end neoverse_n2, ERRATUM(2326639) 168 169check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 170 171workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 172 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 173 * ST to behave like PLD/PFRM LD and not cause 174 * invalidations to other PE caches. 175 */ 176 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 177 orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 178 msr NEOVERSE_N2_CPUACTLR2_EL1, x1 179workaround_reset_end neoverse_n2, ERRATUM(2376738) 180 181check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 0) 182 183workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 184 /*Set bit 40 in ACTLR2_EL1 */ 185 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 186 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 187 msr NEOVERSE_N2_CPUACTLR2_EL1, x1 188workaround_reset_end neoverse_n2, ERRATUM(2388450) 189 190check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 191 192 193workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 194 /* dsb before isb of power down sequence */ 195 dsb sy 196workaround_runtime_end neoverse_n2, ERRATUM(2743089) 197 198check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 199 200 201workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 202#if IMAGE_BL31 203 /* 204 * The Neoverse-N2 generic vectors are overridden to apply errata 205 * mitigation on exception entry from lower ELs. 206 */ 207 adr x0, wa_cve_vbar_neoverse_n2 208 msr vbar_el3, x0 209#endif /* IMAGE_BL31 */ 210workaround_reset_end neoverse_n2, CVE(2022,23960) 211 212check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 213 214 /* ------------------------------------------- 215 * The CPU Ops reset function for Neoverse N2. 216 * ------------------------------------------- 217 */ 218cpu_reset_func_start neoverse_n2 219 220 /* Check if the PE implements SSBS */ 221 mrs x0, id_aa64pfr1_el1 222 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 223 b.eq 1f 224 225 /* Disable speculative loads */ 226 msr SSBS, xzr 2271: 228 /* Force all cacheable atomic instructions to be near */ 229 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 230 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 231 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 232 233#if ENABLE_FEAT_AMU 234 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 235 mrs x0, cptr_el3 236 orr x0, x0, #TAM_BIT 237 msr cptr_el3, x0 238 239 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 240 mrs x0, cptr_el2 241 orr x0, x0, #TAM_BIT 242 msr cptr_el2, x0 243 244 /* No need to enable the counters as this would be done at el3 exit */ 245#endif 246 247#if NEOVERSE_Nx_EXTERNAL_LLC 248 /* Some systems may have External LLC, core needs to be made aware */ 249 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 250 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 251 msr NEOVERSE_N2_CPUECTLR_EL1, x0 252#endif 253cpu_reset_func_end neoverse_n2 254 255func neoverse_n2_core_pwr_dwn 256#if ERRATA_N2_2326639 257 mov x15, x30 258 bl cpu_get_rev_var 259 bl erratum_neoverse_n2_2326639_wa 260 mov x30, x15 261#endif /* ERRATA_N2_2326639 */ 262 263 /* --------------------------------------------------- 264 * Enable CPU power down bit in power control register 265 * No need to do cache maintenance here. 266 * --------------------------------------------------- 267 */ 268 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 269 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 270 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 271#if ERRATA_N2_2743089 272 mov x15, x30 273 bl cpu_get_rev_var 274 bl erratum_neoverse_n2_2743089_wa 275 mov x30, x15 276#endif /* ERRATA_N2_2743089 */ 277 isb 278 ret 279endfunc neoverse_n2_core_pwr_dwn 280 281errata_report_shim neoverse_n2 282 283 /* --------------------------------------------- 284 * This function provides Neoverse N2 specific 285 * register information for crash reporting. 286 * It needs to return with x6 pointing to 287 * a list of register names in ASCII and 288 * x8 - x15 having values of registers to be 289 * reported. 290 * --------------------------------------------- 291 */ 292.section .rodata.neoverse_n2_regs, "aS" 293neoverse_n2_regs: /* The ASCII list of register names to be reported */ 294 .asciz "cpupwrctlr_el1", "" 295 296func neoverse_n2_cpu_reg_dump 297 adr x6, neoverse_n2_regs 298 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 299 ret 300endfunc neoverse_n2_cpu_reg_dump 301 302declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 303 neoverse_n2_reset_func, \ 304 neoverse_n2_core_pwr_dwn 305