1/* 2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 .globl cortex_a55_reset_func 20 .globl cortex_a55_core_pwr_dwn 21 22/* ERRATA_DSU_798953: 23 * The errata is defined in dsu_helpers.S but applies to cortex_a55 24 * as well. Henceforth creating symbolic names to the already existing errata 25 * workaround functions to get them registered under the Errata Framework. 26 */ 27.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953 28.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa 29add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET 30 31/* ERRATA_DSU_936184: 32 * The errata is defined in dsu_helpers.S but applies to cortex_a55 33 * as well. Henceforth creating symbolic names to the already existing errata 34 * workaround functions to get them registered under the Errata Framework. 35 */ 36.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184 37.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa 38add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 39 40workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 41 mrs x1, CORTEX_A55_CPUACTLR_EL1 42 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 43 msr CORTEX_A55_CPUACTLR_EL1, x1 44workaround_reset_end cortex_a55, ERRATUM(768277) 45 46check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0) 47 48workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703 49 mrs x1, CORTEX_A55_CPUECTLR_EL1 50 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL 51 msr CORTEX_A55_CPUECTLR_EL1, x1 52 mrs x1, CORTEX_A55_CPUACTLR_EL1 53 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 54 msr CORTEX_A55_CPUACTLR_EL1, x1 55workaround_reset_end cortex_a55, ERRATUM(778703) 56 57check_erratum_custom_start cortex_a55, ERRATUM(778703) 58 mov x16, x30 59 mov x1, #0x00 60 bl cpu_rev_var_ls 61 /* 62 * Check that no private L2 cache is configured 63 */ 64 mrs x1, CORTEX_A55_CLIDR_EL1 65 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 66 cmp x1, #0 67 mov x2, #ERRATA_NOT_APPLIES 68 csel x0, x0, x2, eq 69 ret x16 70check_erratum_custom_end cortex_a55, ERRATUM(778703) 71 72workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797 73 mrs x1, CORTEX_A55_CPUACTLR_EL1 74 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 75 msr CORTEX_A55_CPUACTLR_EL1, x1 76workaround_reset_end cortex_a55, ERRATUM(798797) 77 78check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0) 79 80workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532 81 mrs x1, CORTEX_A55_CPUACTLR_EL1 82 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 83 msr CORTEX_A55_CPUACTLR_EL1, x1 84workaround_reset_end cortex_a55, ERRATUM(846532) 85 86check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1) 87 88workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758 89 mrs x1, CORTEX_A55_CPUACTLR_EL1 90 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 91 msr CORTEX_A55_CPUACTLR_EL1, x1 92workaround_reset_end cortex_a55, ERRATUM(903758) 93 94check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1) 95 96workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012 97 mov x0, #0x0020 98 movk x0, #0x0850, lsl #16 99 msr CPUPOR_EL3, x0 100 mov x0, #0x0000 101 movk x0, #0x1FF0, lsl #16 102 movk x0, #0x2, lsl #32 103 msr CPUPMR_EL3, x0 104 mov x0, #0x03fd 105 movk x0, #0x0110, lsl #16 106 msr CPUPCR_EL3, x0 107 mov x0, #0x1 108 msr CPUPSELR_EL3, x0 109 mov x0, #0x0040 110 movk x0, #0x08D0, lsl #16 111 msr CPUPOR_EL3, x0 112 mov x0, #0x0040 113 movk x0, #0x1FF0, lsl #16 114 movk x0, #0x2, lsl #32 115 msr CPUPMR_EL3, x0 116 mov x0, #0x03fd 117 movk x0, #0x0110, lsl #16 118 msr CPUPCR_EL3, x0 119workaround_reset_end cortex_a55, ERRATUM(1221012) 120 121check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0) 122 123check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 124 125/* erratum has no workaround in the cpu. Generic code must take care */ 126add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET 127 128cpu_reset_func_start cortex_a55 129cpu_reset_func_end cortex_a55 130 131errata_report_shim cortex_a55 132 133 /* --------------------------------------------- 134 * HW will do the cache maintenance while powering down 135 * --------------------------------------------- 136 */ 137func cortex_a55_core_pwr_dwn 138 /* --------------------------------------------- 139 * Enable CPU power down bit in power control register 140 * --------------------------------------------- 141 */ 142 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 143 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 144 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 145 isb 146 ret 147endfunc cortex_a55_core_pwr_dwn 148 149 /* --------------------------------------------- 150 * This function provides cortex_a55 specific 151 * register information for crash reporting. 152 * It needs to return with x6 pointing to 153 * a list of register names in ascii and 154 * x8 - x15 having values of registers to be 155 * reported. 156 * --------------------------------------------- 157 */ 158.section .rodata.cortex_a55_regs, "aS" 159cortex_a55_regs: /* The ascii list of register names to be reported */ 160 .asciz "cpuectlr_el1", "" 161 162func cortex_a55_cpu_reg_dump 163 adr x6, cortex_a55_regs 164 mrs x8, CORTEX_A55_CPUECTLR_EL1 165 ret 166endfunc cortex_a55_cpu_reg_dump 167 168declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 169 cortex_a55_reset_func, \ 170 cortex_a55_core_pwr_dwn 171