| 291bb2f4 | 06-Jun-2023 |
laurenw-arm <lauren.wehrmeister@arm.com> |
refactor(cpus): convert Neoverse-E1 to framework
For E1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_erra
refactor(cpus): convert Neoverse-E1 to framework
For E1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically
And for the E1 DSU erratum, creating symbolic names to the already
existing errata workaround functions to get them registered under
the Errata Framework.
Testing was conducted by:
- Manual comparison of disassembly of converted functions with non-
converted functions:
aarch64-none-elf-objdump -D
<trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D
<trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
- Build for debug with all errata enabled and step through ArmDS
to ensure all functions are entered and the path remains the same
as before conversion to the new framework.
Change-Id: I0a059574948badbd108333344286c76aeb142e71
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
show more ...
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| a2d43637 | 17-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "bk/context_refactor" into integration
* changes:
refactor(amu): separate the EL2 and EL3 enablement code
refactor(cpufeat): separate the EL2 and EL3 enablement code |
| 50316e22 | 13-Jun-2023 |
laurenw-arm <lauren.wehrmeister@arm.com> |
feat(psa): interface with RSS for retrieving ROTPK
Adding the AP/RSS interface for reading the ROTPK.
The read interface implements the psa_call:
psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,
feat(psa): interface with RSS for retrieving ROTPK
Adding the AP/RSS interface for reading the ROTPK.
The read interface implements the psa_call:
psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,
in_vec, IOVEC_LEN(in_vec),
out_vec, IOVEC_LEN(out_vec));
where the in_vec indicates which of the 3 ROTPKs we want,
and the out_vec stores the ROTPK value we get back from RSS.
Through this service, we will be able to read any of the 3
ROTPKs used on a CCA platform:
- ROTPK for CCA firmware (BL2, BL31, RMM).
- ROTPK for secure firmware.
- ROTPK for non-secure firmware.
Change-Id: I44c615588235cc797fdf38870b74b4c422be0a72
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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|
| 94e27bc1 | 14-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(libc): add %X to printf/snprintf" into integration |
| abd11ce7 | 14-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(xlat): fix defects on the xlat library reported by coverity scan" into integration |
| 483edc20 | 13-Jul-2023 |
Matt Schulte <matsch@google.com> |
feat(libc): add %X to printf/snprintf
Enables printing captial hex chars as well as lowercase
Change-Id: I4dc48c3db97b908f0bb344d7765807967de8cf02
Signed-off-by: Matt Schulte <matsch@google.com> |
| 2974ad87 | 12-Jul-2023 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(xlat): fix defects on the xlat library reported by coverity scan
The coverity defects fixed by this patch is
** CID 394601: Integer handling issues (NO_EFFECT)
/lib/xlat_tables_v2/aarch64/xla
fix(xlat): fix defects on the xlat library reported by coverity scan
The coverity defects fixed by this patch is
** CID 394601: Integer handling issues (NO_EFFECT)
/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c: 30 in
xlat_arch_is_granule_size_supported()
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ibc8e20bd7318a52702fbd7aa86e22cd2ded42610
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|
| e2ca9af1 | 10-Jul-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "kc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A75 to use cpu helpers
refactor(cpus): convert the Cortex-A75 to use the errata frame
Merge changes from topic "kc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A75 to use cpu helpers
refactor(cpus): convert the Cortex-A75 to use the errata framework
show more ...
|
| 4085a02c | 27-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(amu): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
refactor(amu): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
the decision of what needs to be set.
Decouple them to allow them to be called from elsewhere. Also take
some time to clarify and simplify AMU code.
The sanity check in the context_restore() is now wrong, as the cpu may
turn off on suspend, thus resetting the value of the counter enables.
Remove it.
Finally, this completes the migration to cm_manage_extensions_el3() and
manage_extensions_nonsecure() so manage_extensions_nonsecure_mixed() is
being removed.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I66399132364c32be66017506bb54cbadd8485577
show more ...
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| 60d330dc | 16-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cpufeat): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to
refactor(cpufeat): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
the decision of what needs to be set.
Decouple them to allow them to be called from elsewhere.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I147764c42771e7d4100699ec8fae98dac0a505c0
show more ...
|
| e87102f3 | 29-Jun-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "gr/cpu_rename" into integration
* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4 |
| dea3d71e | 28-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hayes to a520
Rename Cortex-hayes to Cortes-A520
Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 31b39455 | 23-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hunter to a720
Rename cortex_hunter to cortex_a720
Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 870fcb94 | 23-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hunter_elp to cortex-x4
Rename hunter_elp to cortex-x4
Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 83a4dae1 | 16-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C ru
refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C runtime has not been
initialised yet.
However, there is no need for it to be initialised so soon. The PMU
state is only relevant after TF-A has relinquished control. The code
to do this is also very verbose and difficult to read. Delaying the
initialisation allows for it to happen with the rest of the PMU. Align
with FEAT_STATE in the process.
BREAKING CHANGE: This patch explicitly breaks the EL2 entry path. It is
currently unsupported.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2aa659d026fbdb75152469f6d19812ece3488c6f
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|
| c73686a1 | 15-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
feat(pmu): introduce pmuv3 lib/extensions folder
The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate t
feat(pmu): introduce pmuv3 lib/extensions folder
The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate the implementation. Treat it is as an architecturally
mandatory feature as it is currently.
Additionally, do some cleanup on AArch64. Setting overflow bits in
PMCR_EL0 is irrelevant for firmware so don't do it. Then delay the PMU
initialisation until the context management stage which simplifies the
early environment assembly. One side effect is that the PMU might count
before this happens so reset all counters to 0 to prevent any leakage.
Finally, add an enable to manage_extensions_realm() as realm world uses
the pmu. This introduces the HPMN fixup to realm world.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie13a8625820ecc5fbfa467dc6ca18025bf6a9cd3
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|
| 24a70738 | 08-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cm): introduce a real manage_extensions_nonsecure()
manage_extensions_nonsecure() is problematic because it updates both
context and in-place registers (unlike its secure/realm counterparts
refactor(cm): introduce a real manage_extensions_nonsecure()
manage_extensions_nonsecure() is problematic because it updates both
context and in-place registers (unlike its secure/realm counterparts).
The in-place register updates make it particularly tricky, as those
never change for the lifetime of TF-A. However, they are only set when
exiting to NS world. As such, all of TF-A's execution before that
operates under a different context. This is inconsistent and could cause
problems.
This patch Introduce a real manage_extensions_nonsecure() which only
operates on the context structure. It also introduces a
cm_manage_extensions_el3() which only operates on register in-place that
are not context switched. It is called in BL31's entrypoints so that all
of TF-A executes with the same environment once all features have been
converted.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic579f86c41026d2054863ef44893e0ba4c591da9
show more ...
|
| 098312ed | 28-Jun-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "ms/cpu_errata" into integration
* changes:
refactor(cpus): add Cortex-A72 errata information
refactor(cpus): convert Rainier to use errata framework
refactor(cpus): c
Merge changes from topic "ms/cpu_errata" into integration
* changes:
refactor(cpus): add Cortex-A72 errata information
refactor(cpus): convert Rainier to use errata framework
refactor(cpus): convert QEMU Max to use the errata framework
show more ...
|
| 6fafbd56 | 09-Jun-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
refactor(cpus): convert the Cortex-A75 to use cpu helpers
Testing done in conjunction with change 258152.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I9082c7a5c68e39d6e419
refactor(cpus): convert the Cortex-A75 to use cpu helpers
Testing done in conjunction with change 258152.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I9082c7a5c68e39d6e419c2a00501d63895ca73c7
show more ...
|
| 742bf3ea | 13-Apr-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
refactor(cpus): convert the Cortex-A75 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp
refactor(cpus): convert the Cortex-A75 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata. Only
ERRATA_A75_764081 and ERRATA_A75_790748 could be verified this way,
rest had to be manually verified.
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 CTX_INCLUDE_AARCH32_REGS=1 \
BL33=/home/katcap01/tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_A75_764081=1 ERRATA_A75_790748=1 WORKAROUND_CVE_2017_5715=1 \
WORKAROUND_CVE_2018_3639=1 \
ERRATA_DSU_798953=1 ERRATA_DSU_936184=1 \
WORKAROUND_CVE_2022_23960=1 \
fip all
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I0cd393db825fcb5c7ddea3aa2a5934ffc4b6046e
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|
| a00e9076 | 27-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(cpus): add support for hermes cpu
Adding basic CPU library code to support the Hermes CPU.
Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@ar
feat(cpus): add support for hermes cpu
Adding basic CPU library code to support the Hermes CPU.
Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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|
| f337f39c | 20-Apr-2023 |
Maksims Svecovs <maksims.svecovs@arm.com> |
refactor(cpus): add Cortex-A72 errata information
* adds add_erratum_etnry for all described erratas.
* replaces errata_report function with errata_report_shim to report
errata automatically
Change
refactor(cpus): add Cortex-A72 errata information
* adds add_erratum_etnry for all described erratas.
* replaces errata_report function with errata_report_shim to report
errata automatically
Change-Id: I7e3315d5cc77b77c328fff7f3988ec588b8f88b9
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
show more ...
|
| e8b30c29 | 19-Apr-2023 |
Maksims Svecovs <maksims.svecovs@arm.com> |
refactor(cpus): convert Rainier to use errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_r
refactor(cpus): convert Rainier to use errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
as well as specifically related to single errata for this CPU:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
Change-Id: I31cacbbdd4caa12b32e2c65ec456b0ab6b1a9101
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
show more ...
|
| e5cc52db | 06-Apr-2023 |
Maksims Svecovs <maksims.svecovs@arm.com> |
refactor(cpus): convert QEMU Max to use the errata framework
This involves replacing:
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically.
Change-Id: I78b65052dcfc1
refactor(cpus): convert QEMU Max to use the errata framework
This involves replacing:
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically.
Change-Id: I78b65052dcfc1f29b7dec443bd0aaf67d0efb4eb
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
show more ...
|
| 0452359a | 12-Jun-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
refactor(cpus): add Cortex-A32 errata framework information
Replace errata_report with errata_report_shim.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I5a43b0985f070f88747
refactor(cpus): add Cortex-A32 errata framework information
Replace errata_report with errata_report_shim.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I5a43b0985f070f887474120eb8f5f7c01ba4af5f
show more ...
|