1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 /* Allow access to Allocation Tags when MTE is implemented. */ 201 scr_el3 |= SCR_ATA_BIT; 202 203 #if !CTX_INCLUDE_PAUTH_REGS 204 /* 205 * Pointer Authentication feature, if present, is always enabled by default 206 * for Non secure lower exception levels. We do not have an explicit 207 * flag to set it. 208 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 209 * exception levels of secure and realm worlds. 210 * 211 * To prevent the leakage between the worlds during world switch, 212 * we enable it only for the non-secure world. 213 * 214 * If the Secure/realm world wants to use pointer authentication, 215 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 216 * it will be enabled globally for all the contexts. 217 * 218 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 219 * other than EL3 220 * 221 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 222 * than EL3 223 */ 224 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 225 226 #endif /* CTX_INCLUDE_PAUTH_REGS */ 227 228 #if HANDLE_EA_EL3_FIRST_NS 229 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 230 scr_el3 |= SCR_EA_BIT; 231 #endif 232 233 #if RAS_TRAP_NS_ERR_REC_ACCESS 234 /* 235 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 236 * and RAS ERX registers from EL1 and EL2(from any security state) 237 * are trapped to EL3. 238 * Set here to trap only for NS EL1/EL2 239 * 240 */ 241 scr_el3 |= SCR_TERR_BIT; 242 #endif 243 244 if (is_feat_csv2_2_supported()) { 245 /* Enable access to the SCXTNUM_ELx registers. */ 246 scr_el3 |= SCR_EnSCXT_BIT; 247 } 248 249 #ifdef IMAGE_BL31 250 /* 251 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 252 * indicated by the interrupt routing model for BL31. 253 */ 254 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 255 #endif 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 258 /* Initialize EL1 context registers */ 259 setup_el1_context(ctx, ep); 260 261 /* Initialize EL2 context registers */ 262 #if CTX_INCLUDE_EL2_REGS 263 264 /* 265 * Initialize SCTLR_EL2 context register using Endianness value 266 * taken from the entrypoint attribute. 267 */ 268 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 269 sctlr_el2 |= SCTLR_EL2_RES1; 270 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 271 sctlr_el2); 272 273 if (is_feat_hcx_supported()) { 274 /* 275 * Initialize register HCRX_EL2 with its init value. 276 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 277 * chance that this can lead to unexpected behavior in lower 278 * ELs that have not been updated since the introduction of 279 * this feature if not properly initialized, especially when 280 * it comes to those bits that enable/disable traps. 281 */ 282 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 283 HCRX_EL2_INIT_VAL); 284 } 285 286 if (is_feat_fgt_supported()) { 287 /* 288 * Initialize HFG*_EL2 registers with a default value so legacy 289 * systems unaware of FEAT_FGT do not get trapped due to their lack 290 * of initialization for this feature. 291 */ 292 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 293 HFGITR_EL2_INIT_VAL); 294 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 295 HFGRTR_EL2_INIT_VAL); 296 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 297 HFGWTR_EL2_INIT_VAL); 298 } 299 #endif /* CTX_INCLUDE_EL2_REGS */ 300 301 manage_extensions_nonsecure(ctx); 302 } 303 304 /******************************************************************************* 305 * The following function performs initialization of the cpu_context 'ctx' 306 * for first use that is common to all security states, and sets the 307 * initial entrypoint state as specified by the entry_point_info structure. 308 * 309 * The EE and ST attributes are used to configure the endianness and secure 310 * timer availability for the new execution context. 311 ******************************************************************************/ 312 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 313 { 314 u_register_t cptr_el3; 315 u_register_t scr_el3; 316 el3_state_t *state; 317 gp_regs_t *gp_regs; 318 319 state = get_el3state_ctx(ctx); 320 321 /* Clear any residual register values from the context */ 322 zeromem(ctx, sizeof(*ctx)); 323 324 /* 325 * The lower-EL context is zeroed so that no stale values leak to a world. 326 * It is assumed that an all-zero lower-EL context is good enough for it 327 * to boot correctly. However, there are very few registers where this 328 * is not true and some values need to be recreated. 329 */ 330 #if CTX_INCLUDE_EL2_REGS 331 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 332 333 /* 334 * These bits are set in the gicv3 driver. Losing them (especially the 335 * SRE bit) is problematic for all worlds. Henceforth recreate them. 336 */ 337 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 338 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 339 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 340 #endif /* CTX_INCLUDE_EL2_REGS */ 341 342 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 343 scr_el3 = SCR_RESET_VAL; 344 345 /* 346 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 347 * EL2, EL1 and EL0 are not trapped to EL3. 348 * 349 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 350 * EL2, EL1 and EL0 are not trapped to EL3. 351 * 352 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 353 * both Security states and both Execution states. 354 * 355 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 356 * Non-secure memory. 357 */ 358 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 359 360 scr_el3 |= SCR_SIF_BIT; 361 362 /* 363 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 364 * Exception level as specified by SPSR. 365 */ 366 if (GET_RW(ep->spsr) == MODE_RW_64) { 367 scr_el3 |= SCR_RW_BIT; 368 } 369 370 /* 371 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 372 * Secure timer registers to EL3, from AArch64 state only, if specified 373 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 374 * bit always behaves as 1 (i.e. secure physical timer register access 375 * is not trapped) 376 */ 377 if (EP_GET_ST(ep->h.attr) != 0U) { 378 scr_el3 |= SCR_ST_BIT; 379 } 380 381 /* 382 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 383 * SCR_EL3.HXEn. 384 */ 385 if (is_feat_hcx_supported()) { 386 scr_el3 |= SCR_HXEn_BIT; 387 } 388 389 /* 390 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 391 * registers are trapped to EL3. 392 */ 393 #if ENABLE_FEAT_RNG_TRAP 394 scr_el3 |= SCR_TRNDR_BIT; 395 #endif 396 397 #if FAULT_INJECTION_SUPPORT 398 /* Enable fault injection from lower ELs */ 399 scr_el3 |= SCR_FIEN_BIT; 400 #endif 401 402 #if CTX_INCLUDE_PAUTH_REGS 403 /* 404 * Enable Pointer Authentication globally for all the worlds. 405 * 406 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 407 * other than EL3 408 * 409 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 410 * than EL3 411 */ 412 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 413 #endif /* CTX_INCLUDE_PAUTH_REGS */ 414 415 /* 416 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 417 */ 418 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 419 scr_el3 |= SCR_TCR2EN_BIT; 420 } 421 422 /* 423 * SCR_EL3.PIEN: Enable permission indirection and overlay 424 * registers for AArch64 if present. 425 */ 426 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 427 scr_el3 |= SCR_PIEN_BIT; 428 } 429 430 /* 431 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 432 */ 433 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 434 scr_el3 |= SCR_GCSEn_BIT; 435 } 436 437 /* 438 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 439 * All fields are architecturally UNKNOWN on reset. 440 * 441 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 442 * by Advanced SIMD, floating-point or SVE instructions (if 443 * implemented) do not trap to EL3. 444 * 445 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 446 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 447 */ 448 cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT); 449 450 write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3); 451 452 /* 453 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 454 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 455 * next mode is Hyp. 456 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 457 * same conditions as HVC instructions and when the processor supports 458 * ARMv8.6-FGT. 459 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 460 * CNTPOFF_EL2 register under the same conditions as HVC instructions 461 * and when the processor supports ECV. 462 */ 463 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 464 || ((GET_RW(ep->spsr) != MODE_RW_64) 465 && (GET_M32(ep->spsr) == MODE32_hyp))) { 466 scr_el3 |= SCR_HCE_BIT; 467 468 if (is_feat_fgt_supported()) { 469 scr_el3 |= SCR_FGTEN_BIT; 470 } 471 472 if (is_feat_ecv_supported()) { 473 scr_el3 |= SCR_ECVEN_BIT; 474 } 475 } 476 477 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 478 if (is_feat_twed_supported()) { 479 /* Set delay in SCR_EL3 */ 480 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 481 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 482 << SCR_TWEDEL_SHIFT); 483 484 /* Enable WFE delay */ 485 scr_el3 |= SCR_TWEDEn_BIT; 486 } 487 488 /* 489 * Populate EL3 state so that we've the right context 490 * before doing ERET 491 */ 492 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 493 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 494 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 495 496 /* 497 * Store the X0-X7 value from the entrypoint into the context 498 * Use memcpy as we are in control of the layout of the structures 499 */ 500 gp_regs = get_gpregs_ctx(ctx); 501 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 502 } 503 504 /******************************************************************************* 505 * Context management library initialization routine. This library is used by 506 * runtime services to share pointers to 'cpu_context' structures for secure 507 * non-secure and realm states. Management of the structures and their associated 508 * memory is not done by the context management library e.g. the PSCI service 509 * manages the cpu context used for entry from and exit to the non-secure state. 510 * The Secure payload dispatcher service manages the context(s) corresponding to 511 * the secure state. It also uses this library to get access to the non-secure 512 * state cpu context pointers. 513 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 514 * which will be used for programming an entry into a lower EL. The same context 515 * will be used to save state upon exception entry from that EL. 516 ******************************************************************************/ 517 void __init cm_init(void) 518 { 519 /* 520 * The context management library has only global data to initialize, but 521 * that will be done when the BSS is zeroed out. 522 */ 523 } 524 525 /******************************************************************************* 526 * This is the high-level function used to initialize the cpu_context 'ctx' for 527 * first use. It performs initializations that are common to all security states 528 * and initializations specific to the security state specified in 'ep' 529 ******************************************************************************/ 530 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 531 { 532 unsigned int security_state; 533 534 assert(ctx != NULL); 535 536 /* 537 * Perform initializations that are common 538 * to all security states 539 */ 540 setup_context_common(ctx, ep); 541 542 security_state = GET_SECURITY_STATE(ep->h.attr); 543 544 /* Perform security state specific initializations */ 545 switch (security_state) { 546 case SECURE: 547 setup_secure_context(ctx, ep); 548 break; 549 #if ENABLE_RME 550 case REALM: 551 setup_realm_context(ctx, ep); 552 break; 553 #endif 554 case NON_SECURE: 555 setup_ns_context(ctx, ep); 556 break; 557 default: 558 ERROR("Invalid security state\n"); 559 panic(); 560 break; 561 } 562 } 563 564 /******************************************************************************* 565 * Enable architecture extensions for EL3 execution. This function only updates 566 * registers in-place which are expected to either never change or be 567 * overwritten by el3_exit. 568 ******************************************************************************/ 569 #if IMAGE_BL31 570 void cm_manage_extensions_el3(void) 571 { 572 if (is_feat_spe_supported()) { 573 spe_init_el3(); 574 } 575 576 if (is_feat_amu_supported()) { 577 amu_init_el3(); 578 } 579 580 if (is_feat_sme_supported()) { 581 sme_init_el3(); 582 } 583 584 if (is_feat_mpam_supported()) { 585 mpam_init_el3(); 586 } 587 588 if (is_feat_trbe_supported()) { 589 trbe_init_el3(); 590 } 591 592 if (is_feat_brbe_supported()) { 593 brbe_init_el3(); 594 } 595 596 if (is_feat_trf_supported()) { 597 trf_init_el3(); 598 } 599 600 pmuv3_init_el3(); 601 } 602 #endif /* IMAGE_BL31 */ 603 604 /******************************************************************************* 605 * Enable architecture extensions on first entry to Non-secure world. 606 ******************************************************************************/ 607 static void manage_extensions_nonsecure(cpu_context_t *ctx) 608 { 609 #if IMAGE_BL31 610 if (is_feat_amu_supported()) { 611 amu_enable(ctx); 612 } 613 614 /* Enable SVE and FPU/SIMD */ 615 if (is_feat_sve_supported()) { 616 sve_enable(ctx); 617 } 618 619 if (is_feat_sme_supported()) { 620 sme_enable(ctx); 621 } 622 623 if (is_feat_sys_reg_trace_supported()) { 624 sys_reg_trace_enable(ctx); 625 } 626 627 pmuv3_enable(ctx); 628 #endif /* IMAGE_BL31 */ 629 } 630 631 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 632 static __unused void enable_pauth_el2(void) 633 { 634 u_register_t hcr_el2 = read_hcr_el2(); 635 /* 636 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 637 * accessing key registers or using pointer authentication instructions 638 * from lower ELs. 639 */ 640 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 641 642 write_hcr_el2(hcr_el2); 643 } 644 645 /******************************************************************************* 646 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 647 * world when EL2 is empty and unused. 648 ******************************************************************************/ 649 static void manage_extensions_nonsecure_el2_unused(void) 650 { 651 #if IMAGE_BL31 652 if (is_feat_spe_supported()) { 653 spe_init_el2_unused(); 654 } 655 656 if (is_feat_amu_supported()) { 657 amu_init_el2_unused(); 658 } 659 660 if (is_feat_mpam_supported()) { 661 mpam_init_el2_unused(); 662 } 663 664 if (is_feat_trbe_supported()) { 665 trbe_init_el2_unused(); 666 } 667 668 if (is_feat_sys_reg_trace_supported()) { 669 sys_reg_trace_init_el2_unused(); 670 } 671 672 if (is_feat_trf_supported()) { 673 trf_init_el2_unused(); 674 } 675 676 pmuv3_init_el2_unused(); 677 678 if (is_feat_sve_supported()) { 679 sve_init_el2_unused(); 680 } 681 682 if (is_feat_sme_supported()) { 683 sme_init_el2_unused(); 684 } 685 686 #if ENABLE_PAUTH 687 enable_pauth_el2(); 688 #endif /* ENABLE_PAUTH */ 689 #endif /* IMAGE_BL31 */ 690 } 691 692 /******************************************************************************* 693 * Enable architecture extensions on first entry to Secure world. 694 ******************************************************************************/ 695 static void manage_extensions_secure(cpu_context_t *ctx) 696 { 697 #if IMAGE_BL31 698 if (is_feat_sve_supported()) { 699 if (ENABLE_SVE_FOR_SWD) { 700 /* 701 * Enable SVE and FPU in secure context, secure manager must 702 * ensure that the SVE and FPU register contexts are properly 703 * managed. 704 */ 705 sve_enable(ctx); 706 } else { 707 /* 708 * Disable SVE and FPU in secure context so non-secure world 709 * can safely use them. 710 */ 711 sve_disable(ctx); 712 } 713 } 714 715 if (is_feat_sme_supported()) { 716 if (ENABLE_SME_FOR_SWD) { 717 /* 718 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 719 * must ensure SME, SVE, and FPU/SIMD context properly managed. 720 */ 721 sme_init_el3(); 722 sme_enable(ctx); 723 } else { 724 /* 725 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 726 * world can safely use the associated registers. 727 */ 728 sme_disable(ctx); 729 } 730 } 731 732 /* NS can access this but Secure shouldn't */ 733 if (is_feat_sys_reg_trace_supported()) { 734 sys_reg_trace_disable(ctx); 735 } 736 #endif /* IMAGE_BL31 */ 737 } 738 739 /******************************************************************************* 740 * The following function initializes the cpu_context for a CPU specified by 741 * its `cpu_idx` for first use, and sets the initial entrypoint state as 742 * specified by the entry_point_info structure. 743 ******************************************************************************/ 744 void cm_init_context_by_index(unsigned int cpu_idx, 745 const entry_point_info_t *ep) 746 { 747 cpu_context_t *ctx; 748 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 749 cm_setup_context(ctx, ep); 750 } 751 752 /******************************************************************************* 753 * The following function initializes the cpu_context for the current CPU 754 * for first use, and sets the initial entrypoint state as specified by the 755 * entry_point_info structure. 756 ******************************************************************************/ 757 void cm_init_my_context(const entry_point_info_t *ep) 758 { 759 cpu_context_t *ctx; 760 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 761 cm_setup_context(ctx, ep); 762 } 763 764 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 765 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 766 { 767 u_register_t hcr_el2 = HCR_RESET_VAL; 768 u_register_t mdcr_el2; 769 u_register_t scr_el3; 770 771 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 772 773 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 774 if ((scr_el3 & SCR_RW_BIT) != 0U) { 775 hcr_el2 |= HCR_RW_BIT; 776 } 777 778 write_hcr_el2(hcr_el2); 779 780 /* 781 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 782 * All fields have architecturally UNKNOWN reset values. 783 */ 784 write_cptr_el2(CPTR_EL2_RESET_VAL); 785 786 /* 787 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 788 * reset and are set to zero except for field(s) listed below. 789 * 790 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 791 * Non-secure EL0 and EL1 accesses to the physical timer registers. 792 * 793 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 794 * Non-secure EL0 and EL1 accesses to the physical counter registers. 795 */ 796 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 797 798 /* 799 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 800 * UNKNOWN value. 801 */ 802 write_cntvoff_el2(0); 803 804 /* 805 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 806 * respectively. 807 */ 808 write_vpidr_el2(read_midr_el1()); 809 write_vmpidr_el2(read_mpidr_el1()); 810 811 /* 812 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 813 * 814 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 815 * translation is disabled, cache maintenance operations depend on the 816 * VMID. 817 * 818 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 819 * disabled. 820 */ 821 write_vttbr_el2(VTTBR_RESET_VAL & 822 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 823 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 824 825 /* 826 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 827 * Some fields are architecturally UNKNOWN on reset. 828 * 829 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 830 * register accesses to the Debug ROM registers are not trapped to EL2. 831 * 832 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 833 * accesses to the powerdown debug registers are not trapped to EL2. 834 * 835 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 836 * debug registers do not trap to EL2. 837 * 838 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 839 * EL2. 840 */ 841 mdcr_el2 = MDCR_EL2_RESET_VAL & 842 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 843 MDCR_EL2_TDE_BIT); 844 845 write_mdcr_el2(mdcr_el2); 846 847 /* 848 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 849 * 850 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 851 * EL1 accesses to System registers do not trap to EL2. 852 */ 853 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 854 855 /* 856 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 857 * reset. 858 * 859 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 860 * and prevent timer interrupts. 861 */ 862 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 863 864 manage_extensions_nonsecure_el2_unused(); 865 } 866 867 /******************************************************************************* 868 * Prepare the CPU system registers for first entry into realm, secure, or 869 * normal world. 870 * 871 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 872 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 873 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 874 * For all entries, the EL1 registers are initialized from the cpu_context 875 ******************************************************************************/ 876 void cm_prepare_el3_exit(uint32_t security_state) 877 { 878 u_register_t sctlr_elx, scr_el3; 879 cpu_context_t *ctx = cm_get_context(security_state); 880 881 assert(ctx != NULL); 882 883 if (security_state == NON_SECURE) { 884 uint64_t el2_implemented = el_implemented(2); 885 886 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 887 CTX_SCR_EL3); 888 889 if (((scr_el3 & SCR_HCE_BIT) != 0U) 890 || (el2_implemented != EL_IMPL_NONE)) { 891 /* 892 * If context is not being used for EL2, initialize 893 * HCRX_EL2 with its init value here. 894 */ 895 if (is_feat_hcx_supported()) { 896 write_hcrx_el2(HCRX_EL2_INIT_VAL); 897 } 898 899 /* 900 * Initialize Fine-grained trap registers introduced 901 * by FEAT_FGT so all traps are initially disabled when 902 * switching to EL2 or a lower EL, preventing undesired 903 * behavior. 904 */ 905 if (is_feat_fgt_supported()) { 906 /* 907 * Initialize HFG*_EL2 registers with a default 908 * value so legacy systems unaware of FEAT_FGT 909 * do not get trapped due to their lack of 910 * initialization for this feature. 911 */ 912 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 913 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 914 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 915 } 916 } 917 918 919 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 920 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 921 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 922 CTX_SCTLR_EL1); 923 sctlr_elx &= SCTLR_EE_BIT; 924 sctlr_elx |= SCTLR_EL2_RES1; 925 #if ERRATA_A75_764081 926 /* 927 * If workaround of errata 764081 for Cortex-A75 is used 928 * then set SCTLR_EL2.IESB to enable Implicit Error 929 * Synchronization Barrier. 930 */ 931 sctlr_elx |= SCTLR_IESB_BIT; 932 #endif 933 write_sctlr_el2(sctlr_elx); 934 } else if (el2_implemented != EL_IMPL_NONE) { 935 init_nonsecure_el2_unused(ctx); 936 } 937 } 938 939 cm_el1_sysregs_context_restore(security_state); 940 cm_set_next_eret_context(security_state); 941 } 942 943 #if CTX_INCLUDE_EL2_REGS 944 945 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 946 { 947 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 948 if (is_feat_amu_supported()) { 949 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 950 } 951 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 952 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 953 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 954 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 955 } 956 957 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 958 { 959 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 960 if (is_feat_amu_supported()) { 961 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 962 } 963 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 964 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 965 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 966 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 967 } 968 969 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 970 { 971 u_register_t mpam_idr = read_mpamidr_el1(); 972 973 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 974 975 /* 976 * The context registers that we intend to save would be part of the 977 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 978 */ 979 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 980 return; 981 } 982 983 /* 984 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 985 * MPAMIDR_HAS_HCR_BIT == 1. 986 */ 987 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 988 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 989 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 990 991 /* 992 * The number of MPAMVPM registers is implementation defined, their 993 * number is stored in the MPAMIDR_EL1 register. 994 */ 995 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 996 case 7: 997 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 998 __fallthrough; 999 case 6: 1000 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1001 __fallthrough; 1002 case 5: 1003 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1004 __fallthrough; 1005 case 4: 1006 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1007 __fallthrough; 1008 case 3: 1009 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1010 __fallthrough; 1011 case 2: 1012 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1013 __fallthrough; 1014 case 1: 1015 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1016 break; 1017 } 1018 } 1019 1020 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1021 { 1022 u_register_t mpam_idr = read_mpamidr_el1(); 1023 1024 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1025 1026 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1027 return; 1028 } 1029 1030 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1031 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1032 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1033 1034 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1035 case 7: 1036 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1037 __fallthrough; 1038 case 6: 1039 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1040 __fallthrough; 1041 case 5: 1042 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1043 __fallthrough; 1044 case 4: 1045 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1046 __fallthrough; 1047 case 3: 1048 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1049 __fallthrough; 1050 case 2: 1051 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1052 __fallthrough; 1053 case 1: 1054 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1055 break; 1056 } 1057 } 1058 1059 /* ----------------------------------------------------- 1060 * The following registers are not added: 1061 * AMEVCNTVOFF0<n>_EL2 1062 * AMEVCNTVOFF1<n>_EL2 1063 * ICH_AP0R<n>_EL2 1064 * ICH_AP1R<n>_EL2 1065 * ICH_LR<n>_EL2 1066 * ----------------------------------------------------- 1067 */ 1068 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1069 { 1070 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1071 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1072 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1073 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1074 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1075 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1076 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1077 if (CTX_INCLUDE_AARCH32_REGS) { 1078 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1079 } 1080 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1081 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1082 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1083 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1084 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1085 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1086 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1087 1088 /* 1089 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1090 * TODO: remove with root context 1091 */ 1092 u_register_t scr_el3 = read_scr_el3(); 1093 1094 write_scr_el3(scr_el3 | SCR_NS_BIT); 1095 isb(); 1096 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1097 1098 write_scr_el3(scr_el3); 1099 isb(); 1100 1101 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1102 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1103 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1104 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1105 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1106 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1107 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1108 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1109 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1110 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1111 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1112 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1113 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1114 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1115 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1116 } 1117 1118 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1119 { 1120 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1121 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1122 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1123 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1124 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1125 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1126 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1127 if (CTX_INCLUDE_AARCH32_REGS) { 1128 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1129 } 1130 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1131 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1132 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1133 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1134 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1135 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1136 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1137 1138 /* 1139 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1140 * TODO: remove with root context 1141 */ 1142 u_register_t scr_el3 = read_scr_el3(); 1143 1144 write_scr_el3(scr_el3 | SCR_NS_BIT); 1145 isb(); 1146 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1147 1148 write_scr_el3(scr_el3); 1149 isb(); 1150 1151 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1152 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1153 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1154 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1155 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1156 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1157 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1158 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1159 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1160 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1161 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1162 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1163 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1164 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1165 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1166 } 1167 1168 /******************************************************************************* 1169 * Save EL2 sysreg context 1170 ******************************************************************************/ 1171 void cm_el2_sysregs_context_save(uint32_t security_state) 1172 { 1173 cpu_context_t *ctx; 1174 el2_sysregs_t *el2_sysregs_ctx; 1175 1176 ctx = cm_get_context(security_state); 1177 assert(ctx != NULL); 1178 1179 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1180 1181 el2_sysregs_context_save_common(el2_sysregs_ctx); 1182 #if CTX_INCLUDE_MTE_REGS 1183 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1184 #endif 1185 if (is_feat_mpam_supported()) { 1186 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1187 } 1188 1189 if (is_feat_fgt_supported()) { 1190 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1191 } 1192 1193 if (is_feat_ecv_v2_supported()) { 1194 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); 1195 } 1196 1197 if (is_feat_vhe_supported()) { 1198 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); 1199 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); 1200 } 1201 1202 if (is_feat_ras_supported()) { 1203 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); 1204 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); 1205 } 1206 1207 if (is_feat_nv2_supported()) { 1208 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); 1209 } 1210 1211 if (is_feat_trf_supported()) { 1212 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1213 } 1214 1215 if (is_feat_csv2_2_supported()) { 1216 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); 1217 } 1218 1219 if (is_feat_hcx_supported()) { 1220 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1221 } 1222 if (is_feat_tcr2_supported()) { 1223 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1224 } 1225 if (is_feat_sxpie_supported()) { 1226 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1227 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1228 } 1229 if (is_feat_s2pie_supported()) { 1230 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1231 } 1232 if (is_feat_sxpoe_supported()) { 1233 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1234 } 1235 if (is_feat_gcs_supported()) { 1236 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1237 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1238 } 1239 } 1240 1241 /******************************************************************************* 1242 * Restore EL2 sysreg context 1243 ******************************************************************************/ 1244 void cm_el2_sysregs_context_restore(uint32_t security_state) 1245 { 1246 cpu_context_t *ctx; 1247 el2_sysregs_t *el2_sysregs_ctx; 1248 1249 ctx = cm_get_context(security_state); 1250 assert(ctx != NULL); 1251 1252 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1253 1254 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1255 #if CTX_INCLUDE_MTE_REGS 1256 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1257 #endif 1258 if (is_feat_mpam_supported()) { 1259 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1260 } 1261 1262 if (is_feat_fgt_supported()) { 1263 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1264 } 1265 1266 if (is_feat_ecv_v2_supported()) { 1267 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); 1268 } 1269 1270 if (is_feat_vhe_supported()) { 1271 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1272 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1273 } 1274 1275 if (is_feat_ras_supported()) { 1276 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1277 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1278 } 1279 1280 if (is_feat_nv2_supported()) { 1281 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1282 } 1283 if (is_feat_trf_supported()) { 1284 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1285 } 1286 1287 if (is_feat_csv2_2_supported()) { 1288 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); 1289 } 1290 1291 if (is_feat_hcx_supported()) { 1292 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1293 } 1294 if (is_feat_tcr2_supported()) { 1295 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1296 } 1297 if (is_feat_sxpie_supported()) { 1298 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1299 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1300 } 1301 if (is_feat_s2pie_supported()) { 1302 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1303 } 1304 if (is_feat_sxpoe_supported()) { 1305 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1306 } 1307 if (is_feat_gcs_supported()) { 1308 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1309 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1310 } 1311 } 1312 #endif /* CTX_INCLUDE_EL2_REGS */ 1313 1314 /******************************************************************************* 1315 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1316 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1317 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1318 * cm_prepare_el3_exit function. 1319 ******************************************************************************/ 1320 void cm_prepare_el3_exit_ns(void) 1321 { 1322 #if CTX_INCLUDE_EL2_REGS 1323 #if ENABLE_ASSERTIONS 1324 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1325 assert(ctx != NULL); 1326 1327 /* Assert that EL2 is used. */ 1328 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1329 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1330 (el_implemented(2U) != EL_IMPL_NONE)); 1331 #endif /* ENABLE_ASSERTIONS */ 1332 1333 /* Restore EL2 and EL1 sysreg contexts */ 1334 cm_el2_sysregs_context_restore(NON_SECURE); 1335 cm_el1_sysregs_context_restore(NON_SECURE); 1336 cm_set_next_eret_context(NON_SECURE); 1337 #else 1338 cm_prepare_el3_exit(NON_SECURE); 1339 #endif /* CTX_INCLUDE_EL2_REGS */ 1340 } 1341 1342 /******************************************************************************* 1343 * The next four functions are used by runtime services to save and restore 1344 * EL1 context on the 'cpu_context' structure for the specified security 1345 * state. 1346 ******************************************************************************/ 1347 void cm_el1_sysregs_context_save(uint32_t security_state) 1348 { 1349 cpu_context_t *ctx; 1350 1351 ctx = cm_get_context(security_state); 1352 assert(ctx != NULL); 1353 1354 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1355 1356 #if IMAGE_BL31 1357 if (security_state == SECURE) 1358 PUBLISH_EVENT(cm_exited_secure_world); 1359 else 1360 PUBLISH_EVENT(cm_exited_normal_world); 1361 #endif 1362 } 1363 1364 void cm_el1_sysregs_context_restore(uint32_t security_state) 1365 { 1366 cpu_context_t *ctx; 1367 1368 ctx = cm_get_context(security_state); 1369 assert(ctx != NULL); 1370 1371 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1372 1373 #if IMAGE_BL31 1374 if (security_state == SECURE) 1375 PUBLISH_EVENT(cm_entering_secure_world); 1376 else 1377 PUBLISH_EVENT(cm_entering_normal_world); 1378 #endif 1379 } 1380 1381 /******************************************************************************* 1382 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1383 * given security state with the given entrypoint 1384 ******************************************************************************/ 1385 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1386 { 1387 cpu_context_t *ctx; 1388 el3_state_t *state; 1389 1390 ctx = cm_get_context(security_state); 1391 assert(ctx != NULL); 1392 1393 /* Populate EL3 state so that ERET jumps to the correct entry */ 1394 state = get_el3state_ctx(ctx); 1395 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1396 } 1397 1398 /******************************************************************************* 1399 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1400 * pertaining to the given security state 1401 ******************************************************************************/ 1402 void cm_set_elr_spsr_el3(uint32_t security_state, 1403 uintptr_t entrypoint, uint32_t spsr) 1404 { 1405 cpu_context_t *ctx; 1406 el3_state_t *state; 1407 1408 ctx = cm_get_context(security_state); 1409 assert(ctx != NULL); 1410 1411 /* Populate EL3 state so that ERET jumps to the correct entry */ 1412 state = get_el3state_ctx(ctx); 1413 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1414 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1415 } 1416 1417 /******************************************************************************* 1418 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1419 * pertaining to the given security state using the value and bit position 1420 * specified in the parameters. It preserves all other bits. 1421 ******************************************************************************/ 1422 void cm_write_scr_el3_bit(uint32_t security_state, 1423 uint32_t bit_pos, 1424 uint32_t value) 1425 { 1426 cpu_context_t *ctx; 1427 el3_state_t *state; 1428 u_register_t scr_el3; 1429 1430 ctx = cm_get_context(security_state); 1431 assert(ctx != NULL); 1432 1433 /* Ensure that the bit position is a valid one */ 1434 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1435 1436 /* Ensure that the 'value' is only a bit wide */ 1437 assert(value <= 1U); 1438 1439 /* 1440 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1441 * and set it to its new value. 1442 */ 1443 state = get_el3state_ctx(ctx); 1444 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1445 scr_el3 &= ~(1UL << bit_pos); 1446 scr_el3 |= (u_register_t)value << bit_pos; 1447 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1448 } 1449 1450 /******************************************************************************* 1451 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1452 * given security state. 1453 ******************************************************************************/ 1454 u_register_t cm_get_scr_el3(uint32_t security_state) 1455 { 1456 cpu_context_t *ctx; 1457 el3_state_t *state; 1458 1459 ctx = cm_get_context(security_state); 1460 assert(ctx != NULL); 1461 1462 /* Populate EL3 state so that ERET jumps to the correct entry */ 1463 state = get_el3state_ctx(ctx); 1464 return read_ctx_reg(state, CTX_SCR_EL3); 1465 } 1466 1467 /******************************************************************************* 1468 * This function is used to program the context that's used for exception 1469 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1470 * the required security state 1471 ******************************************************************************/ 1472 void cm_set_next_eret_context(uint32_t security_state) 1473 { 1474 cpu_context_t *ctx; 1475 1476 ctx = cm_get_context(security_state); 1477 assert(ctx != NULL); 1478 1479 cm_set_next_context(ctx); 1480 } 1481