1 /* 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/arm/dcc.h> 17 #include <drivers/console.h> 18 #include <lib/mmio.h> 19 #include <libfdt.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 23 #include <custom_svc.h> 24 #include <plat_private.h> 25 #include <plat_startup.h> 26 #include <zynqmp_def.h> 27 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 entry_point_info_t *next_image_info; 41 42 assert(sec_state_is_valid(type)); 43 if (type == NON_SECURE) { 44 next_image_info = &bl33_image_ep_info; 45 } else { 46 next_image_info = &bl32_image_ep_info; 47 } 48 49 return next_image_info; 50 } 51 52 /* 53 * Set the build time defaults. We want to do this when doing a JTAG boot 54 * or if we can't find any other config data. 55 */ 56 static inline void bl31_set_default_config(void) 57 { 58 bl32_image_ep_info.pc = BL32_BASE; 59 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 60 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 61 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 62 DISABLE_ALL_EXCEPTIONS); 63 } 64 65 /* 66 * Perform any BL31 specific platform actions. Here is an opportunity to copy 67 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 68 * are lost (potentially). This needs to be done before the MMU is initialized 69 * so that the memory layout can be used while creating page tables. 70 */ 71 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 72 u_register_t arg2, u_register_t arg3) 73 { 74 uint64_t tfa_handoff_addr; 75 76 if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) { 77 /* Register the console to provide early debug support */ 78 static console_t bl31_boot_console; 79 (void)console_cdns_register(ZYNQMP_UART_BASE, 80 zynqmp_get_uart_clk(), 81 ZYNQMP_UART_BAUDRATE, 82 &bl31_boot_console); 83 console_set_scope(&bl31_boot_console, 84 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT | 85 CONSOLE_FLAG_CRASH); 86 } else if (ZYNQMP_CONSOLE_IS(dcc)) { 87 /* Initialize the dcc console for debug */ 88 int32_t rc = console_dcc_register(); 89 if (rc == 0) { 90 panic(); 91 } 92 } else { 93 ERROR("BL31: No console device found.\n"); 94 } 95 /* Initialize the platform config for future decision making */ 96 zynqmp_config_setup(); 97 98 /* 99 * Do initial security configuration to allow DRAM/device access. On 100 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 101 * other platforms might have more programmable security devices 102 * present. 103 */ 104 105 /* Populate common information for BL32 and BL33 */ 106 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 107 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 108 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 109 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 110 111 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 112 113 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 114 bl31_set_default_config(); 115 } else { 116 /* use parameters from XBL */ 117 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 118 &bl33_image_ep_info, 119 tfa_handoff_addr); 120 if (ret != XBL_HANDOFF_SUCCESS) { 121 panic(); 122 } 123 } 124 if (bl32_image_ep_info.pc != 0) { 125 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 126 } 127 if (bl33_image_ep_info.pc != 0) { 128 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 129 } 130 131 custom_early_setup(); 132 133 } 134 135 #if ZYNQMP_WDT_RESTART 136 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 137 138 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 139 { 140 static uint32_t index; 141 uint32_t i; 142 143 /* Validate 'handler' and 'id' parameters */ 144 if (!handler || index >= MAX_INTR_EL3) { 145 return -EINVAL; 146 } 147 148 /* Check if a handler has already been registered */ 149 for (i = 0; i < index; i++) { 150 if (id == type_el3_interrupt_table[i].id) { 151 return -EALREADY; 152 } 153 } 154 155 type_el3_interrupt_table[index].id = id; 156 type_el3_interrupt_table[index].handler = handler; 157 158 index++; 159 160 return 0; 161 } 162 163 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 164 void *handle, void *cookie) 165 { 166 uint32_t intr_id; 167 uint32_t i; 168 interrupt_type_handler_t handler = NULL; 169 170 intr_id = plat_ic_get_pending_interrupt_id(); 171 172 for (i = 0; i < MAX_INTR_EL3; i++) { 173 if (intr_id == type_el3_interrupt_table[i].id) { 174 handler = type_el3_interrupt_table[i].handler; 175 } 176 } 177 178 if (handler != NULL) { 179 return handler(intr_id, flags, handle, cookie); 180 } 181 182 return 0; 183 } 184 #endif 185 186 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 187 static void prepare_dtb(void) 188 { 189 void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; 190 int ret; 191 192 /* Return if no device tree is detected */ 193 if (fdt_check_header(dtb) != 0) { 194 NOTICE("Can't read DT at %p\n", dtb); 195 return; 196 } 197 198 ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE); 199 if (ret < 0) { 200 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); 201 return; 202 } 203 204 if (dt_add_psci_node(dtb)) { 205 ERROR("Failed to add PSCI Device Tree node\n"); 206 return; 207 } 208 209 if (dt_add_psci_cpu_enable_methods(dtb)) { 210 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); 211 return; 212 } 213 214 /* Reserve memory used by Trusted Firmware. */ 215 if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, 216 (size_t) (BL31_LIMIT - BL31_BASE))) { 217 WARN("Failed to add reserved memory nodes for BL31 to DT.\n"); 218 } 219 220 ret = fdt_pack(dtb); 221 if (ret < 0) { 222 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); 223 } 224 225 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); 226 INFO("Changed device tree to advertise PSCI and reserved memories.\n"); 227 } 228 #endif 229 230 void bl31_platform_setup(void) 231 { 232 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 233 prepare_dtb(); 234 #endif 235 236 /* Initialize the gic cpu and distributor interfaces */ 237 plat_arm_gic_driver_init(); 238 plat_arm_gic_init(); 239 } 240 241 void bl31_plat_runtime_setup(void) 242 { 243 #if ZYNQMP_WDT_RESTART 244 uint64_t flags = 0; 245 uint64_t rc; 246 247 set_interrupt_rm_flag(flags, NON_SECURE); 248 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 249 rdo_el3_interrupt_handler, flags); 250 if (rc) { 251 panic(); 252 } 253 #endif 254 255 custom_runtime_setup(); 256 } 257 258 /* 259 * Perform the very early platform specific architectural setup here. 260 */ 261 void bl31_plat_arch_setup(void) 262 { 263 plat_arm_interconnect_init(); 264 plat_arm_interconnect_enter_coherency(); 265 266 const mmap_region_t bl_regions[] = { 267 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 268 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 269 MT_MEMORY | MT_RW | MT_NS), 270 #endif 271 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 272 MT_MEMORY | MT_RW | MT_SECURE), 273 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 274 MT_CODE | MT_SECURE), 275 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 276 MT_RO_DATA | MT_SECURE), 277 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 278 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 279 MT_DEVICE | MT_RW | MT_SECURE), 280 {0} 281 }; 282 283 custom_mmap_add(); 284 285 setup_page_tables(bl_regions, plat_arm_get_mmap()); 286 enable_mmu_el3(0); 287 } 288