1/* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl init_cpu_data_ptr 53#endif /* IMAGE_BL31 */ 54 55 /* --------------------------------------------------------------------- 56 * Initialise SCR_EL3, setting all fields rather than relying on hw. 57 * All fields are architecturally UNKNOWN on reset. The following fields 58 * do not change during the TF lifetime. The remaining fields are set to 59 * zero here but are updated ahead of transitioning to a lower EL in the 60 * function cm_init_context_common(). 61 * 62 * SCR_EL3.SIF: Set to one to disable instruction fetches from 63 * Non-secure memory. 64 * 65 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 66 * to EL3 when executing at any EL. 67 * --------------------------------------------------------------------- 68 */ 69 mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) 70#if ENABLE_RME 71 /* 72 * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers 73 * in context management. This will need to be refactored. 74 */ 75 orr x0, x0, #SCR_EEL2_BIT 76#endif 77 msr scr_el3, x0 78 79 /* --------------------------------------------------------------------- 80 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 81 * Some fields are architecturally UNKNOWN on reset. 82 * 83 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 84 * Debug exceptions, other than Breakpoint Instruction exceptions, are 85 * disabled from all ELs in Secure state. 86 * 87 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 88 * privileged debug from S-EL1. 89 * 90 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 91 * access to the powerdown debug registers do not trap to EL3. 92 * 93 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 94 * debug registers, other than those registers that are controlled by 95 * MDCR_EL3.TDOSA. 96 */ 97 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 98 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ 99 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT)) 100 101 msr mdcr_el3, x0 102 103 /* --------------------------------------------------------------------- 104 * Enable External Aborts and SError Interrupts now that the exception 105 * vectors have been setup. 106 * --------------------------------------------------------------------- 107 */ 108 msr daifclr, #DAIF_ABT_BIT 109 110 /* --------------------------------------------------------------------- 111 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 112 * All fields are architecturally UNKNOWN on reset. 113 * --------------------------------------------------------------------- 114 */ 115 mov_imm x0, CPTR_EL3_RESET_VAL 116 msr cptr_el3, x0 117 118 /* 119 * If Data Independent Timing (DIT) functionality is implemented, 120 * always enable DIT in EL3. 121 * First assert that the FEAT_DIT build flag matches the feature id 122 * register value for DIT. 123 */ 124#if ENABLE_FEAT_DIT 125#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 126 mrs x0, id_aa64pfr0_el1 127 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 128#if ENABLE_FEAT_DIT > 1 129 cbz x0, 1f 130#else 131 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 132 ASM_ASSERT(eq) 133#endif 134 135#endif /* ENABLE_ASSERTIONS */ 136 mov x0, #DIT_BIT 137 msr DIT, x0 1381: 139#endif 140 .endm 141 142/* ----------------------------------------------------------------------------- 143 * This is the super set of actions that need to be performed during a cold boot 144 * or a warm boot in EL3. This code is shared by BL1 and BL31. 145 * 146 * This macro will always perform reset handling, architectural initialisations 147 * and stack setup. The rest of the actions are optional because they might not 148 * be needed, depending on the context in which this macro is called. This is 149 * why this macro is parameterised ; each parameter allows to enable/disable 150 * some actions. 151 * 152 * _init_sctlr: 153 * Whether the macro needs to initialise SCTLR_EL3, including configuring 154 * the endianness of data accesses. 155 * 156 * _warm_boot_mailbox: 157 * Whether the macro needs to detect the type of boot (cold/warm). The 158 * detection is based on the platform entrypoint address : if it is zero 159 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 160 * this macro jumps on the platform entrypoint address. 161 * 162 * _secondary_cold_boot: 163 * Whether the macro needs to identify the CPU that is calling it: primary 164 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 165 * the platform initialisations, while the secondaries will be put in a 166 * platform-specific state in the meantime. 167 * 168 * If the caller knows this macro will only be called by the primary CPU 169 * then this parameter can be defined to 0 to skip this step. 170 * 171 * _init_memory: 172 * Whether the macro needs to initialise the memory. 173 * 174 * _init_c_runtime: 175 * Whether the macro needs to initialise the C runtime environment. 176 * 177 * _exception_vectors: 178 * Address of the exception vectors to program in the VBAR_EL3 register. 179 * 180 * _pie_fixup_size: 181 * Size of memory region to fixup Global Descriptor Table (GDT). 182 * 183 * A non-zero value is expected when firmware needs GDT to be fixed-up. 184 * 185 * ----------------------------------------------------------------------------- 186 */ 187 .macro el3_entrypoint_common \ 188 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 189 _init_memory, _init_c_runtime, _exception_vectors, \ 190 _pie_fixup_size 191 192 .if \_init_sctlr 193 /* ------------------------------------------------------------- 194 * This is the initialisation of SCTLR_EL3 and so must ensure 195 * that all fields are explicitly set rather than relying on hw. 196 * Some fields reset to an IMPLEMENTATION DEFINED value and 197 * others are architecturally UNKNOWN on reset. 198 * 199 * SCTLR.EE: Set the CPU endianness before doing anything that 200 * might involve memory reads or writes. Set to zero to select 201 * Little Endian. 202 * 203 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 204 * force all memory regions that are writeable to be treated as 205 * XN (Execute-never). Set to zero so that this control has no 206 * effect on memory access permissions. 207 * 208 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 209 * 210 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 211 * 212 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 213 * safe behaviour upon exception entry to EL3. 214 * ------------------------------------------------------------- 215 */ 216 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 217 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 218 msr sctlr_el3, x0 219 isb 220 .endif /* _init_sctlr */ 221 222 .if \_warm_boot_mailbox 223 /* ------------------------------------------------------------- 224 * This code will be executed for both warm and cold resets. 225 * Now is the time to distinguish between the two. 226 * Query the platform entrypoint address and if it is not zero 227 * then it means it is a warm boot so jump to this address. 228 * ------------------------------------------------------------- 229 */ 230 bl plat_get_my_entrypoint 231 cbz x0, do_cold_boot 232 br x0 233 234 do_cold_boot: 235 .endif /* _warm_boot_mailbox */ 236 237 .if \_pie_fixup_size 238#if ENABLE_PIE 239 /* 240 * ------------------------------------------------------------ 241 * If PIE is enabled fixup the Global descriptor Table only 242 * once during primary core cold boot path. 243 * 244 * Compile time base address, required for fixup, is calculated 245 * using "pie_fixup" label present within first page. 246 * ------------------------------------------------------------ 247 */ 248 pie_fixup: 249 ldr x0, =pie_fixup 250 and x0, x0, #~(PAGE_SIZE_MASK) 251 mov_imm x1, \_pie_fixup_size 252 add x1, x1, x0 253 bl fixup_gdt_reloc 254#endif /* ENABLE_PIE */ 255 .endif /* _pie_fixup_size */ 256 257 /* --------------------------------------------------------------------- 258 * Set the exception vectors. 259 * --------------------------------------------------------------------- 260 */ 261 adr x0, \_exception_vectors 262 msr vbar_el3, x0 263 isb 264 265#if !(defined(IMAGE_BL2) && ENABLE_RME) 266 /* --------------------------------------------------------------------- 267 * It is a cold boot. 268 * Perform any processor specific actions upon reset e.g. cache, TLB 269 * invalidations etc. 270 * --------------------------------------------------------------------- 271 */ 272 bl reset_handler 273#endif 274 275 el3_arch_init_common 276 277 .if \_secondary_cold_boot 278 /* ------------------------------------------------------------- 279 * Check if this is a primary or secondary CPU cold boot. 280 * The primary CPU will set up the platform while the 281 * secondaries are placed in a platform-specific state until the 282 * primary CPU performs the necessary actions to bring them out 283 * of that state and allows entry into the OS. 284 * ------------------------------------------------------------- 285 */ 286 bl plat_is_my_cpu_primary 287 cbnz w0, do_primary_cold_boot 288 289 /* This is a cold boot on a secondary CPU */ 290 bl plat_secondary_cold_boot_setup 291 /* plat_secondary_cold_boot_setup() is not supposed to return */ 292 bl el3_panic 293 294 do_primary_cold_boot: 295 .endif /* _secondary_cold_boot */ 296 297 /* --------------------------------------------------------------------- 298 * Initialize memory now. Secondary CPU initialization won't get to this 299 * point. 300 * --------------------------------------------------------------------- 301 */ 302 303 .if \_init_memory 304 bl platform_mem_init 305 .endif /* _init_memory */ 306 307 /* --------------------------------------------------------------------- 308 * Init C runtime environment: 309 * - Zero-initialise the NOBITS sections. There are 2 of them: 310 * - the .bss section; 311 * - the coherent memory section (if any). 312 * - Relocate the data section from ROM to RAM, if required. 313 * --------------------------------------------------------------------- 314 */ 315 .if \_init_c_runtime 316#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 317 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 318 /* ------------------------------------------------------------- 319 * Invalidate the RW memory used by the BL31 image. This 320 * includes the data and NOBITS sections. This is done to 321 * safeguard against possible corruption of this memory by 322 * dirty cache lines in a system cache as a result of use by 323 * an earlier boot loader stage. If PIE is enabled however, 324 * RO sections including the GOT may be modified during 325 * pie fixup. Therefore, to be on the safe side, invalidate 326 * the entire image region if PIE is enabled. 327 * ------------------------------------------------------------- 328 */ 329#if ENABLE_PIE 330#if SEPARATE_CODE_AND_RODATA 331 adrp x0, __TEXT_START__ 332 add x0, x0, :lo12:__TEXT_START__ 333#else 334 adrp x0, __RO_START__ 335 add x0, x0, :lo12:__RO_START__ 336#endif /* SEPARATE_CODE_AND_RODATA */ 337#else 338 adrp x0, __RW_START__ 339 add x0, x0, :lo12:__RW_START__ 340#endif /* ENABLE_PIE */ 341 adrp x1, __RW_END__ 342 add x1, x1, :lo12:__RW_END__ 343 sub x1, x1, x0 344 bl inv_dcache_range 345#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 346 adrp x0, __NOBITS_START__ 347 add x0, x0, :lo12:__NOBITS_START__ 348 adrp x1, __NOBITS_END__ 349 add x1, x1, :lo12:__NOBITS_END__ 350 sub x1, x1, x0 351 bl inv_dcache_range 352#endif 353#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 354 adrp x0, __BL2_NOLOAD_START__ 355 add x0, x0, :lo12:__BL2_NOLOAD_START__ 356 adrp x1, __BL2_NOLOAD_END__ 357 add x1, x1, :lo12:__BL2_NOLOAD_END__ 358 sub x1, x1, x0 359 bl inv_dcache_range 360#endif 361#endif 362 adrp x0, __BSS_START__ 363 add x0, x0, :lo12:__BSS_START__ 364 365 adrp x1, __BSS_END__ 366 add x1, x1, :lo12:__BSS_END__ 367 sub x1, x1, x0 368 bl zeromem 369 370#if USE_COHERENT_MEM 371 adrp x0, __COHERENT_RAM_START__ 372 add x0, x0, :lo12:__COHERENT_RAM_START__ 373 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 374 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 375 sub x1, x1, x0 376 bl zeromem 377#endif 378 379#if defined(IMAGE_BL1) || \ 380 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) 381 adrp x0, __DATA_RAM_START__ 382 add x0, x0, :lo12:__DATA_RAM_START__ 383 adrp x1, __DATA_ROM_START__ 384 add x1, x1, :lo12:__DATA_ROM_START__ 385 adrp x2, __DATA_RAM_END__ 386 add x2, x2, :lo12:__DATA_RAM_END__ 387 sub x2, x2, x0 388 bl memcpy16 389#endif 390 .endif /* _init_c_runtime */ 391 392 /* --------------------------------------------------------------------- 393 * Use SP_EL0 for the C runtime stack. 394 * --------------------------------------------------------------------- 395 */ 396 msr spsel, #0 397 398 /* --------------------------------------------------------------------- 399 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 400 * the MMU is enabled. There is no risk of reading stale stack memory 401 * after enabling the MMU as only the primary CPU is running at the 402 * moment. 403 * --------------------------------------------------------------------- 404 */ 405 bl plat_set_my_stack 406 407#if STACK_PROTECTOR_ENABLED 408 .if \_init_c_runtime 409 bl update_stack_protector_canary 410 .endif /* _init_c_runtime */ 411#endif 412 .endm 413 414 .macro apply_at_speculative_wa 415#if ERRATA_SPECULATIVE_AT 416 /* 417 * This function expects x30 has been saved. 418 * Also, save x29 which will be used in the called function. 419 */ 420 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 421 bl save_and_update_ptw_el1_sys_regs 422 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 423#endif 424 .endm 425 426 .macro restore_ptw_el1_sys_regs 427#if ERRATA_SPECULATIVE_AT 428 /* ----------------------------------------------------------- 429 * In case of ERRATA_SPECULATIVE_AT, must follow below order 430 * to ensure that page table walk is not enabled until 431 * restoration of all EL1 system registers. TCR_EL1 register 432 * should be updated at the end which restores previous page 433 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 434 * ensures that CPU does below steps in order. 435 * 436 * 1. Ensure all other system registers are written before 437 * updating SCTLR_EL1 using ISB. 438 * 2. Restore SCTLR_EL1 register. 439 * 3. Ensure SCTLR_EL1 written successfully using ISB. 440 * 4. Restore TCR_EL1 register. 441 * ----------------------------------------------------------- 442 */ 443 isb 444 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 445 msr sctlr_el1, x28 446 isb 447 msr tcr_el1, x29 448#endif 449 .endm 450 451#endif /* EL3_COMMON_MACROS_S */ 452