1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 /* Allow access to Allocation Tags when MTE is implemented. */ 201 scr_el3 |= SCR_ATA_BIT; 202 203 #if !CTX_INCLUDE_PAUTH_REGS 204 /* 205 * Pointer Authentication feature, if present, is always enabled by default 206 * for Non secure lower exception levels. We do not have an explicit 207 * flag to set it. 208 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 209 * exception levels of secure and realm worlds. 210 * 211 * To prevent the leakage between the worlds during world switch, 212 * we enable it only for the non-secure world. 213 * 214 * If the Secure/realm world wants to use pointer authentication, 215 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 216 * it will be enabled globally for all the contexts. 217 * 218 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 219 * other than EL3 220 * 221 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 222 * than EL3 223 */ 224 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 225 226 #endif /* CTX_INCLUDE_PAUTH_REGS */ 227 228 #if HANDLE_EA_EL3_FIRST_NS 229 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 230 scr_el3 |= SCR_EA_BIT; 231 #endif 232 233 #if RAS_TRAP_NS_ERR_REC_ACCESS 234 /* 235 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 236 * and RAS ERX registers from EL1 and EL2(from any security state) 237 * are trapped to EL3. 238 * Set here to trap only for NS EL1/EL2 239 * 240 */ 241 scr_el3 |= SCR_TERR_BIT; 242 #endif 243 244 if (is_feat_csv2_2_supported()) { 245 /* Enable access to the SCXTNUM_ELx registers. */ 246 scr_el3 |= SCR_EnSCXT_BIT; 247 } 248 249 #ifdef IMAGE_BL31 250 /* 251 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 252 * indicated by the interrupt routing model for BL31. 253 */ 254 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 255 #endif 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 258 /* Initialize EL1 context registers */ 259 setup_el1_context(ctx, ep); 260 261 /* Initialize EL2 context registers */ 262 #if CTX_INCLUDE_EL2_REGS 263 264 /* 265 * Initialize SCTLR_EL2 context register using Endianness value 266 * taken from the entrypoint attribute. 267 */ 268 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 269 sctlr_el2 |= SCTLR_EL2_RES1; 270 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 271 sctlr_el2); 272 273 /* 274 * Program the ICC_SRE_EL2 to make sure the correct bits are set 275 * when restoring NS context. 276 */ 277 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 278 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 279 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 280 icc_sre_el2); 281 282 if (is_feat_hcx_supported()) { 283 /* 284 * Initialize register HCRX_EL2 with its init value. 285 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 286 * chance that this can lead to unexpected behavior in lower 287 * ELs that have not been updated since the introduction of 288 * this feature if not properly initialized, especially when 289 * it comes to those bits that enable/disable traps. 290 */ 291 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 292 HCRX_EL2_INIT_VAL); 293 } 294 295 if (is_feat_fgt_supported()) { 296 /* 297 * Initialize HFG*_EL2 registers with a default value so legacy 298 * systems unaware of FEAT_FGT do not get trapped due to their lack 299 * of initialization for this feature. 300 */ 301 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 302 HFGITR_EL2_INIT_VAL); 303 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 304 HFGRTR_EL2_INIT_VAL); 305 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 306 HFGWTR_EL2_INIT_VAL); 307 } 308 #endif /* CTX_INCLUDE_EL2_REGS */ 309 310 manage_extensions_nonsecure(ctx); 311 } 312 313 /******************************************************************************* 314 * The following function performs initialization of the cpu_context 'ctx' 315 * for first use that is common to all security states, and sets the 316 * initial entrypoint state as specified by the entry_point_info structure. 317 * 318 * The EE and ST attributes are used to configure the endianness and secure 319 * timer availability for the new execution context. 320 ******************************************************************************/ 321 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 322 { 323 u_register_t cptr_el3; 324 u_register_t scr_el3; 325 el3_state_t *state; 326 gp_regs_t *gp_regs; 327 328 state = get_el3state_ctx(ctx); 329 330 /* Clear any residual register values from the context */ 331 zeromem(ctx, sizeof(*ctx)); 332 333 /* 334 * SCR_EL3 was initialised during reset sequence in macro 335 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 336 * affect the next EL. 337 * 338 * The following fields are initially set to zero and then updated to 339 * the required value depending on the state of the SPSR_EL3 and the 340 * Security state and entrypoint attributes of the next EL. 341 */ 342 scr_el3 = read_scr(); 343 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 344 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 345 346 /* 347 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 348 * EL2, EL1 and EL0 are not trapped to EL3. 349 * 350 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 351 * EL2, EL1 and EL0 are not trapped to EL3. 352 * 353 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 354 * both Security states and both Execution states. 355 * 356 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 357 * Non-secure memory. 358 */ 359 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 360 361 scr_el3 |= SCR_SIF_BIT; 362 363 /* 364 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 365 * Exception level as specified by SPSR. 366 */ 367 if (GET_RW(ep->spsr) == MODE_RW_64) { 368 scr_el3 |= SCR_RW_BIT; 369 } 370 371 /* 372 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 373 * Secure timer registers to EL3, from AArch64 state only, if specified 374 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 375 * bit always behaves as 1 (i.e. secure physical timer register access 376 * is not trapped) 377 */ 378 if (EP_GET_ST(ep->h.attr) != 0U) { 379 scr_el3 |= SCR_ST_BIT; 380 } 381 382 /* 383 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 384 * SCR_EL3.HXEn. 385 */ 386 if (is_feat_hcx_supported()) { 387 scr_el3 |= SCR_HXEn_BIT; 388 } 389 390 /* 391 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 392 * registers are trapped to EL3. 393 */ 394 #if ENABLE_FEAT_RNG_TRAP 395 scr_el3 |= SCR_TRNDR_BIT; 396 #endif 397 398 #if FAULT_INJECTION_SUPPORT 399 /* Enable fault injection from lower ELs */ 400 scr_el3 |= SCR_FIEN_BIT; 401 #endif 402 403 #if CTX_INCLUDE_PAUTH_REGS 404 /* 405 * Enable Pointer Authentication globally for all the worlds. 406 * 407 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 408 * other than EL3 409 * 410 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 411 * than EL3 412 */ 413 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 414 #endif /* CTX_INCLUDE_PAUTH_REGS */ 415 416 /* 417 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 418 */ 419 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 420 scr_el3 |= SCR_TCR2EN_BIT; 421 } 422 423 /* 424 * SCR_EL3.PIEN: Enable permission indirection and overlay 425 * registers for AArch64 if present. 426 */ 427 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 428 scr_el3 |= SCR_PIEN_BIT; 429 } 430 431 /* 432 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 433 */ 434 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 435 scr_el3 |= SCR_GCSEn_BIT; 436 } 437 438 /* 439 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 440 * All fields are architecturally UNKNOWN on reset. 441 * 442 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 443 * by Advanced SIMD, floating-point or SVE instructions (if 444 * implemented) do not trap to EL3. 445 * 446 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 447 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 448 */ 449 cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT); 450 451 write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3); 452 453 /* 454 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 455 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 456 * next mode is Hyp. 457 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 458 * same conditions as HVC instructions and when the processor supports 459 * ARMv8.6-FGT. 460 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 461 * CNTPOFF_EL2 register under the same conditions as HVC instructions 462 * and when the processor supports ECV. 463 */ 464 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 465 || ((GET_RW(ep->spsr) != MODE_RW_64) 466 && (GET_M32(ep->spsr) == MODE32_hyp))) { 467 scr_el3 |= SCR_HCE_BIT; 468 469 if (is_feat_fgt_supported()) { 470 scr_el3 |= SCR_FGTEN_BIT; 471 } 472 473 if (is_feat_ecv_supported()) { 474 scr_el3 |= SCR_ECVEN_BIT; 475 } 476 } 477 478 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 479 if (is_feat_twed_supported()) { 480 /* Set delay in SCR_EL3 */ 481 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 482 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 483 << SCR_TWEDEL_SHIFT); 484 485 /* Enable WFE delay */ 486 scr_el3 |= SCR_TWEDEn_BIT; 487 } 488 489 /* 490 * Populate EL3 state so that we've the right context 491 * before doing ERET 492 */ 493 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 494 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 495 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 496 497 /* 498 * Store the X0-X7 value from the entrypoint into the context 499 * Use memcpy as we are in control of the layout of the structures 500 */ 501 gp_regs = get_gpregs_ctx(ctx); 502 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 503 } 504 505 /******************************************************************************* 506 * Context management library initialization routine. This library is used by 507 * runtime services to share pointers to 'cpu_context' structures for secure 508 * non-secure and realm states. Management of the structures and their associated 509 * memory is not done by the context management library e.g. the PSCI service 510 * manages the cpu context used for entry from and exit to the non-secure state. 511 * The Secure payload dispatcher service manages the context(s) corresponding to 512 * the secure state. It also uses this library to get access to the non-secure 513 * state cpu context pointers. 514 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 515 * which will be used for programming an entry into a lower EL. The same context 516 * will be used to save state upon exception entry from that EL. 517 ******************************************************************************/ 518 void __init cm_init(void) 519 { 520 /* 521 * The context management library has only global data to initialize, but 522 * that will be done when the BSS is zeroed out. 523 */ 524 } 525 526 /******************************************************************************* 527 * This is the high-level function used to initialize the cpu_context 'ctx' for 528 * first use. It performs initializations that are common to all security states 529 * and initializations specific to the security state specified in 'ep' 530 ******************************************************************************/ 531 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 532 { 533 unsigned int security_state; 534 535 assert(ctx != NULL); 536 537 /* 538 * Perform initializations that are common 539 * to all security states 540 */ 541 setup_context_common(ctx, ep); 542 543 security_state = GET_SECURITY_STATE(ep->h.attr); 544 545 /* Perform security state specific initializations */ 546 switch (security_state) { 547 case SECURE: 548 setup_secure_context(ctx, ep); 549 break; 550 #if ENABLE_RME 551 case REALM: 552 setup_realm_context(ctx, ep); 553 break; 554 #endif 555 case NON_SECURE: 556 setup_ns_context(ctx, ep); 557 break; 558 default: 559 ERROR("Invalid security state\n"); 560 panic(); 561 break; 562 } 563 } 564 565 /******************************************************************************* 566 * Enable architecture extensions for EL3 execution. This function only updates 567 * registers in-place which are expected to either never change or be 568 * overwritten by el3_exit. 569 ******************************************************************************/ 570 #if IMAGE_BL31 571 void cm_manage_extensions_el3(void) 572 { 573 if (is_feat_spe_supported()) { 574 spe_init_el3(); 575 } 576 577 if (is_feat_amu_supported()) { 578 amu_init_el3(); 579 } 580 581 if (is_feat_sme_supported()) { 582 sme_init_el3(); 583 } 584 585 if (is_feat_mpam_supported()) { 586 mpam_init_el3(); 587 } 588 589 if (is_feat_trbe_supported()) { 590 trbe_init_el3(); 591 } 592 593 if (is_feat_brbe_supported()) { 594 brbe_init_el3(); 595 } 596 597 if (is_feat_trf_supported()) { 598 trf_init_el3(); 599 } 600 601 pmuv3_init_el3(); 602 } 603 #endif /* IMAGE_BL31 */ 604 605 /******************************************************************************* 606 * Enable architecture extensions on first entry to Non-secure world. 607 ******************************************************************************/ 608 static void manage_extensions_nonsecure(cpu_context_t *ctx) 609 { 610 #if IMAGE_BL31 611 if (is_feat_amu_supported()) { 612 amu_enable(ctx); 613 } 614 615 /* Enable SVE and FPU/SIMD */ 616 if (is_feat_sve_supported()) { 617 sve_enable(ctx); 618 } 619 620 if (is_feat_sme_supported()) { 621 sme_enable(ctx); 622 } 623 624 if (is_feat_sys_reg_trace_supported()) { 625 sys_reg_trace_enable(ctx); 626 } 627 628 pmuv3_enable(ctx); 629 #endif /* IMAGE_BL31 */ 630 } 631 632 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 633 static __unused void enable_pauth_el2(void) 634 { 635 u_register_t hcr_el2 = read_hcr_el2(); 636 /* 637 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 638 * accessing key registers or using pointer authentication instructions 639 * from lower ELs. 640 */ 641 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 642 643 write_hcr_el2(hcr_el2); 644 } 645 646 /******************************************************************************* 647 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 648 * world when EL2 is empty and unused. 649 ******************************************************************************/ 650 static void manage_extensions_nonsecure_el2_unused(void) 651 { 652 #if IMAGE_BL31 653 if (is_feat_spe_supported()) { 654 spe_init_el2_unused(); 655 } 656 657 if (is_feat_amu_supported()) { 658 amu_init_el2_unused(); 659 } 660 661 if (is_feat_mpam_supported()) { 662 mpam_init_el2_unused(); 663 } 664 665 if (is_feat_trbe_supported()) { 666 trbe_init_el2_unused(); 667 } 668 669 if (is_feat_sys_reg_trace_supported()) { 670 sys_reg_trace_init_el2_unused(); 671 } 672 673 if (is_feat_trf_supported()) { 674 trf_init_el2_unused(); 675 } 676 677 pmuv3_init_el2_unused(); 678 679 if (is_feat_sve_supported()) { 680 sve_init_el2_unused(); 681 } 682 683 if (is_feat_sme_supported()) { 684 sme_init_el2_unused(); 685 } 686 687 #if ENABLE_PAUTH 688 enable_pauth_el2(); 689 #endif /* ENABLE_PAUTH */ 690 #endif /* IMAGE_BL31 */ 691 } 692 693 /******************************************************************************* 694 * Enable architecture extensions on first entry to Secure world. 695 ******************************************************************************/ 696 static void manage_extensions_secure(cpu_context_t *ctx) 697 { 698 #if IMAGE_BL31 699 if (is_feat_sve_supported()) { 700 if (ENABLE_SVE_FOR_SWD) { 701 /* 702 * Enable SVE and FPU in secure context, secure manager must 703 * ensure that the SVE and FPU register contexts are properly 704 * managed. 705 */ 706 sve_enable(ctx); 707 } else { 708 /* 709 * Disable SVE and FPU in secure context so non-secure world 710 * can safely use them. 711 */ 712 sve_disable(ctx); 713 } 714 } 715 716 if (is_feat_sme_supported()) { 717 if (ENABLE_SME_FOR_SWD) { 718 /* 719 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 720 * must ensure SME, SVE, and FPU/SIMD context properly managed. 721 */ 722 sme_init_el3(); 723 sme_enable(ctx); 724 } else { 725 /* 726 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 727 * world can safely use the associated registers. 728 */ 729 sme_disable(ctx); 730 } 731 } 732 733 /* NS can access this but Secure shouldn't */ 734 if (is_feat_sys_reg_trace_supported()) { 735 sys_reg_trace_disable(ctx); 736 } 737 #endif /* IMAGE_BL31 */ 738 } 739 740 /******************************************************************************* 741 * The following function initializes the cpu_context for a CPU specified by 742 * its `cpu_idx` for first use, and sets the initial entrypoint state as 743 * specified by the entry_point_info structure. 744 ******************************************************************************/ 745 void cm_init_context_by_index(unsigned int cpu_idx, 746 const entry_point_info_t *ep) 747 { 748 cpu_context_t *ctx; 749 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 750 cm_setup_context(ctx, ep); 751 } 752 753 /******************************************************************************* 754 * The following function initializes the cpu_context for the current CPU 755 * for first use, and sets the initial entrypoint state as specified by the 756 * entry_point_info structure. 757 ******************************************************************************/ 758 void cm_init_my_context(const entry_point_info_t *ep) 759 { 760 cpu_context_t *ctx; 761 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 762 cm_setup_context(ctx, ep); 763 } 764 765 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 766 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 767 { 768 u_register_t hcr_el2 = HCR_RESET_VAL; 769 u_register_t mdcr_el2; 770 u_register_t scr_el3; 771 772 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 773 774 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 775 if ((scr_el3 & SCR_RW_BIT) != 0U) { 776 hcr_el2 |= HCR_RW_BIT; 777 } 778 779 write_hcr_el2(hcr_el2); 780 781 /* 782 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 783 * All fields have architecturally UNKNOWN reset values. 784 */ 785 write_cptr_el2(CPTR_EL2_RESET_VAL); 786 787 /* 788 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 789 * reset and are set to zero except for field(s) listed below. 790 * 791 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 792 * Non-secure EL0 and EL1 accesses to the physical timer registers. 793 * 794 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 795 * Non-secure EL0 and EL1 accesses to the physical counter registers. 796 */ 797 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 798 799 /* 800 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 801 * UNKNOWN value. 802 */ 803 write_cntvoff_el2(0); 804 805 /* 806 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 807 * respectively. 808 */ 809 write_vpidr_el2(read_midr_el1()); 810 write_vmpidr_el2(read_mpidr_el1()); 811 812 /* 813 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 814 * 815 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 816 * translation is disabled, cache maintenance operations depend on the 817 * VMID. 818 * 819 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 820 * disabled. 821 */ 822 write_vttbr_el2(VTTBR_RESET_VAL & 823 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 824 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 825 826 /* 827 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 828 * Some fields are architecturally UNKNOWN on reset. 829 * 830 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 831 * register accesses to the Debug ROM registers are not trapped to EL2. 832 * 833 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 834 * accesses to the powerdown debug registers are not trapped to EL2. 835 * 836 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 837 * debug registers do not trap to EL2. 838 * 839 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 840 * EL2. 841 */ 842 mdcr_el2 = MDCR_EL2_RESET_VAL & 843 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 844 MDCR_EL2_TDE_BIT); 845 846 write_mdcr_el2(mdcr_el2); 847 848 /* 849 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 850 * 851 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 852 * EL1 accesses to System registers do not trap to EL2. 853 */ 854 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 855 856 /* 857 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 858 * reset. 859 * 860 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 861 * and prevent timer interrupts. 862 */ 863 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 864 865 manage_extensions_nonsecure_el2_unused(); 866 } 867 868 /******************************************************************************* 869 * Prepare the CPU system registers for first entry into realm, secure, or 870 * normal world. 871 * 872 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 873 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 874 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 875 * For all entries, the EL1 registers are initialized from the cpu_context 876 ******************************************************************************/ 877 void cm_prepare_el3_exit(uint32_t security_state) 878 { 879 u_register_t sctlr_elx, scr_el3; 880 cpu_context_t *ctx = cm_get_context(security_state); 881 882 assert(ctx != NULL); 883 884 if (security_state == NON_SECURE) { 885 uint64_t el2_implemented = el_implemented(2); 886 887 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 888 CTX_SCR_EL3); 889 890 if (((scr_el3 & SCR_HCE_BIT) != 0U) 891 || (el2_implemented != EL_IMPL_NONE)) { 892 /* 893 * If context is not being used for EL2, initialize 894 * HCRX_EL2 with its init value here. 895 */ 896 if (is_feat_hcx_supported()) { 897 write_hcrx_el2(HCRX_EL2_INIT_VAL); 898 } 899 900 /* 901 * Initialize Fine-grained trap registers introduced 902 * by FEAT_FGT so all traps are initially disabled when 903 * switching to EL2 or a lower EL, preventing undesired 904 * behavior. 905 */ 906 if (is_feat_fgt_supported()) { 907 /* 908 * Initialize HFG*_EL2 registers with a default 909 * value so legacy systems unaware of FEAT_FGT 910 * do not get trapped due to their lack of 911 * initialization for this feature. 912 */ 913 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 914 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 915 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 916 } 917 } 918 919 920 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 921 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 922 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 923 CTX_SCTLR_EL1); 924 sctlr_elx &= SCTLR_EE_BIT; 925 sctlr_elx |= SCTLR_EL2_RES1; 926 #if ERRATA_A75_764081 927 /* 928 * If workaround of errata 764081 for Cortex-A75 is used 929 * then set SCTLR_EL2.IESB to enable Implicit Error 930 * Synchronization Barrier. 931 */ 932 sctlr_elx |= SCTLR_IESB_BIT; 933 #endif 934 write_sctlr_el2(sctlr_elx); 935 } else if (el2_implemented != EL_IMPL_NONE) { 936 init_nonsecure_el2_unused(ctx); 937 } 938 } 939 940 cm_el1_sysregs_context_restore(security_state); 941 cm_set_next_eret_context(security_state); 942 } 943 944 #if CTX_INCLUDE_EL2_REGS 945 946 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 947 { 948 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 949 if (is_feat_amu_supported()) { 950 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 951 } 952 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 953 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 954 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 955 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 956 } 957 958 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 959 { 960 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 961 if (is_feat_amu_supported()) { 962 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 963 } 964 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 965 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 966 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 967 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 968 } 969 970 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 971 { 972 u_register_t mpam_idr = read_mpamidr_el1(); 973 974 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 975 976 /* 977 * The context registers that we intend to save would be part of the 978 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 979 */ 980 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 981 return; 982 } 983 984 /* 985 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 986 * MPAMIDR_HAS_HCR_BIT == 1. 987 */ 988 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 989 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 990 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 991 992 /* 993 * The number of MPAMVPM registers is implementation defined, their 994 * number is stored in the MPAMIDR_EL1 register. 995 */ 996 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 997 case 7: 998 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 999 __fallthrough; 1000 case 6: 1001 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1002 __fallthrough; 1003 case 5: 1004 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1005 __fallthrough; 1006 case 4: 1007 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1008 __fallthrough; 1009 case 3: 1010 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1011 __fallthrough; 1012 case 2: 1013 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1014 __fallthrough; 1015 case 1: 1016 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1017 break; 1018 } 1019 } 1020 1021 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1022 { 1023 u_register_t mpam_idr = read_mpamidr_el1(); 1024 1025 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1026 1027 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1028 return; 1029 } 1030 1031 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1032 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1033 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1034 1035 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1036 case 7: 1037 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1038 __fallthrough; 1039 case 6: 1040 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1041 __fallthrough; 1042 case 5: 1043 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1044 __fallthrough; 1045 case 4: 1046 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1047 __fallthrough; 1048 case 3: 1049 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1050 __fallthrough; 1051 case 2: 1052 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1053 __fallthrough; 1054 case 1: 1055 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1056 break; 1057 } 1058 } 1059 1060 /* ----------------------------------------------------- 1061 * The following registers are not added: 1062 * AMEVCNTVOFF0<n>_EL2 1063 * AMEVCNTVOFF1<n>_EL2 1064 * ICH_AP0R<n>_EL2 1065 * ICH_AP1R<n>_EL2 1066 * ICH_LR<n>_EL2 1067 * ----------------------------------------------------- 1068 */ 1069 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1070 { 1071 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1072 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1073 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1074 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1075 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1076 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1077 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1078 if (CTX_INCLUDE_AARCH32_REGS) { 1079 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1080 } 1081 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1082 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1083 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1084 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1085 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1086 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1087 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1088 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1089 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1090 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1091 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1092 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1093 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1094 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1095 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1096 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1097 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1098 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1099 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1100 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1101 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1102 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1103 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1104 } 1105 1106 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1107 { 1108 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1109 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1110 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1111 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1112 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1113 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1114 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1115 if (CTX_INCLUDE_AARCH32_REGS) { 1116 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1117 } 1118 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1119 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1120 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1121 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1122 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1123 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1124 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1125 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1126 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1127 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1128 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1129 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1130 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1131 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1132 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1133 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1134 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1135 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1136 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1137 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1138 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1139 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1140 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1141 } 1142 1143 /******************************************************************************* 1144 * Save EL2 sysreg context 1145 ******************************************************************************/ 1146 void cm_el2_sysregs_context_save(uint32_t security_state) 1147 { 1148 u_register_t scr_el3 = read_scr(); 1149 1150 /* 1151 * Always save the non-secure and realm EL2 context, only save the 1152 * S-EL2 context if S-EL2 is enabled. 1153 */ 1154 if ((security_state != SECURE) || 1155 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1156 cpu_context_t *ctx; 1157 el2_sysregs_t *el2_sysregs_ctx; 1158 1159 ctx = cm_get_context(security_state); 1160 assert(ctx != NULL); 1161 1162 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1163 1164 el2_sysregs_context_save_common(el2_sysregs_ctx); 1165 #if CTX_INCLUDE_MTE_REGS 1166 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1167 #endif 1168 if (is_feat_mpam_supported()) { 1169 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1170 } 1171 1172 if (is_feat_fgt_supported()) { 1173 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1174 } 1175 1176 if (is_feat_ecv_v2_supported()) { 1177 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 1178 read_cntpoff_el2()); 1179 } 1180 1181 if (is_feat_vhe_supported()) { 1182 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1183 read_contextidr_el2()); 1184 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1185 read_ttbr1_el2()); 1186 } 1187 1188 if (is_feat_ras_supported()) { 1189 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, 1190 read_vdisr_el2()); 1191 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, 1192 read_vsesr_el2()); 1193 } 1194 1195 if (is_feat_nv2_supported()) { 1196 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1197 read_vncr_el2()); 1198 } 1199 1200 if (is_feat_trf_supported()) { 1201 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1202 } 1203 1204 if (is_feat_csv2_2_supported()) { 1205 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1206 read_scxtnum_el2()); 1207 } 1208 1209 if (is_feat_hcx_supported()) { 1210 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1211 } 1212 if (is_feat_tcr2_supported()) { 1213 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1214 } 1215 if (is_feat_sxpie_supported()) { 1216 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1217 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1218 } 1219 if (is_feat_s2pie_supported()) { 1220 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1221 } 1222 if (is_feat_sxpoe_supported()) { 1223 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1224 } 1225 if (is_feat_gcs_supported()) { 1226 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1227 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1228 } 1229 } 1230 } 1231 1232 /******************************************************************************* 1233 * Restore EL2 sysreg context 1234 ******************************************************************************/ 1235 void cm_el2_sysregs_context_restore(uint32_t security_state) 1236 { 1237 u_register_t scr_el3 = read_scr(); 1238 1239 /* 1240 * Always restore the non-secure and realm EL2 context, only restore the 1241 * S-EL2 context if S-EL2 is enabled. 1242 */ 1243 if ((security_state != SECURE) || 1244 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1245 cpu_context_t *ctx; 1246 el2_sysregs_t *el2_sysregs_ctx; 1247 1248 ctx = cm_get_context(security_state); 1249 assert(ctx != NULL); 1250 1251 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1252 1253 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1254 #if CTX_INCLUDE_MTE_REGS 1255 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1256 #endif 1257 if (is_feat_mpam_supported()) { 1258 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1259 } 1260 1261 if (is_feat_fgt_supported()) { 1262 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1263 } 1264 1265 if (is_feat_ecv_v2_supported()) { 1266 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1267 CTX_CNTPOFF_EL2)); 1268 } 1269 1270 if (is_feat_vhe_supported()) { 1271 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1272 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1273 } 1274 1275 if (is_feat_ras_supported()) { 1276 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1277 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1278 } 1279 1280 if (is_feat_nv2_supported()) { 1281 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1282 } 1283 if (is_feat_trf_supported()) { 1284 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1285 } 1286 1287 if (is_feat_csv2_2_supported()) { 1288 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1289 CTX_SCXTNUM_EL2)); 1290 } 1291 1292 if (is_feat_hcx_supported()) { 1293 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1294 } 1295 if (is_feat_tcr2_supported()) { 1296 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1297 } 1298 if (is_feat_sxpie_supported()) { 1299 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1300 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1301 } 1302 if (is_feat_s2pie_supported()) { 1303 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1304 } 1305 if (is_feat_sxpoe_supported()) { 1306 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1307 } 1308 if (is_feat_gcs_supported()) { 1309 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1310 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1311 } 1312 } 1313 } 1314 #endif /* CTX_INCLUDE_EL2_REGS */ 1315 1316 /******************************************************************************* 1317 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1318 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1319 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1320 * cm_prepare_el3_exit function. 1321 ******************************************************************************/ 1322 void cm_prepare_el3_exit_ns(void) 1323 { 1324 #if CTX_INCLUDE_EL2_REGS 1325 #if ENABLE_ASSERTIONS 1326 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1327 assert(ctx != NULL); 1328 1329 /* Assert that EL2 is used. */ 1330 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1331 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1332 (el_implemented(2U) != EL_IMPL_NONE)); 1333 #endif /* ENABLE_ASSERTIONS */ 1334 1335 /* 1336 * Set the NS bit to be able to access the ICC_SRE_EL2 1337 * register when restoring context. 1338 */ 1339 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1340 1341 /* 1342 * Ensure the NS bit change is committed before the EL2/EL1 1343 * state restoration. 1344 */ 1345 isb(); 1346 1347 /* Restore EL2 and EL1 sysreg contexts */ 1348 cm_el2_sysregs_context_restore(NON_SECURE); 1349 cm_el1_sysregs_context_restore(NON_SECURE); 1350 cm_set_next_eret_context(NON_SECURE); 1351 #else 1352 cm_prepare_el3_exit(NON_SECURE); 1353 #endif /* CTX_INCLUDE_EL2_REGS */ 1354 } 1355 1356 /******************************************************************************* 1357 * The next four functions are used by runtime services to save and restore 1358 * EL1 context on the 'cpu_context' structure for the specified security 1359 * state. 1360 ******************************************************************************/ 1361 void cm_el1_sysregs_context_save(uint32_t security_state) 1362 { 1363 cpu_context_t *ctx; 1364 1365 ctx = cm_get_context(security_state); 1366 assert(ctx != NULL); 1367 1368 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1369 1370 #if IMAGE_BL31 1371 if (security_state == SECURE) 1372 PUBLISH_EVENT(cm_exited_secure_world); 1373 else 1374 PUBLISH_EVENT(cm_exited_normal_world); 1375 #endif 1376 } 1377 1378 void cm_el1_sysregs_context_restore(uint32_t security_state) 1379 { 1380 cpu_context_t *ctx; 1381 1382 ctx = cm_get_context(security_state); 1383 assert(ctx != NULL); 1384 1385 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1386 1387 #if IMAGE_BL31 1388 if (security_state == SECURE) 1389 PUBLISH_EVENT(cm_entering_secure_world); 1390 else 1391 PUBLISH_EVENT(cm_entering_normal_world); 1392 #endif 1393 } 1394 1395 /******************************************************************************* 1396 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1397 * given security state with the given entrypoint 1398 ******************************************************************************/ 1399 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1400 { 1401 cpu_context_t *ctx; 1402 el3_state_t *state; 1403 1404 ctx = cm_get_context(security_state); 1405 assert(ctx != NULL); 1406 1407 /* Populate EL3 state so that ERET jumps to the correct entry */ 1408 state = get_el3state_ctx(ctx); 1409 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1410 } 1411 1412 /******************************************************************************* 1413 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1414 * pertaining to the given security state 1415 ******************************************************************************/ 1416 void cm_set_elr_spsr_el3(uint32_t security_state, 1417 uintptr_t entrypoint, uint32_t spsr) 1418 { 1419 cpu_context_t *ctx; 1420 el3_state_t *state; 1421 1422 ctx = cm_get_context(security_state); 1423 assert(ctx != NULL); 1424 1425 /* Populate EL3 state so that ERET jumps to the correct entry */ 1426 state = get_el3state_ctx(ctx); 1427 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1428 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1429 } 1430 1431 /******************************************************************************* 1432 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1433 * pertaining to the given security state using the value and bit position 1434 * specified in the parameters. It preserves all other bits. 1435 ******************************************************************************/ 1436 void cm_write_scr_el3_bit(uint32_t security_state, 1437 uint32_t bit_pos, 1438 uint32_t value) 1439 { 1440 cpu_context_t *ctx; 1441 el3_state_t *state; 1442 u_register_t scr_el3; 1443 1444 ctx = cm_get_context(security_state); 1445 assert(ctx != NULL); 1446 1447 /* Ensure that the bit position is a valid one */ 1448 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1449 1450 /* Ensure that the 'value' is only a bit wide */ 1451 assert(value <= 1U); 1452 1453 /* 1454 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1455 * and set it to its new value. 1456 */ 1457 state = get_el3state_ctx(ctx); 1458 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1459 scr_el3 &= ~(1UL << bit_pos); 1460 scr_el3 |= (u_register_t)value << bit_pos; 1461 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1462 } 1463 1464 /******************************************************************************* 1465 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1466 * given security state. 1467 ******************************************************************************/ 1468 u_register_t cm_get_scr_el3(uint32_t security_state) 1469 { 1470 cpu_context_t *ctx; 1471 el3_state_t *state; 1472 1473 ctx = cm_get_context(security_state); 1474 assert(ctx != NULL); 1475 1476 /* Populate EL3 state so that ERET jumps to the correct entry */ 1477 state = get_el3state_ctx(ctx); 1478 return read_ctx_reg(state, CTX_SCR_EL3); 1479 } 1480 1481 /******************************************************************************* 1482 * This function is used to program the context that's used for exception 1483 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1484 * the required security state 1485 ******************************************************************************/ 1486 void cm_set_next_eret_context(uint32_t security_state) 1487 { 1488 cpu_context_t *ctx; 1489 1490 ctx = cm_get_context(security_state); 1491 assert(ctx != NULL); 1492 1493 cm_set_next_context(ctx); 1494 } 1495