1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 /* Allow access to Allocation Tags when MTE is implemented. */ 201 scr_el3 |= SCR_ATA_BIT; 202 203 #if !CTX_INCLUDE_PAUTH_REGS 204 /* 205 * Pointer Authentication feature, if present, is always enabled by default 206 * for Non secure lower exception levels. We do not have an explicit 207 * flag to set it. 208 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 209 * exception levels of secure and realm worlds. 210 * 211 * To prevent the leakage between the worlds during world switch, 212 * we enable it only for the non-secure world. 213 * 214 * If the Secure/realm world wants to use pointer authentication, 215 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 216 * it will be enabled globally for all the contexts. 217 * 218 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 219 * other than EL3 220 * 221 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 222 * than EL3 223 */ 224 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 225 226 #endif /* CTX_INCLUDE_PAUTH_REGS */ 227 228 #if HANDLE_EA_EL3_FIRST_NS 229 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 230 scr_el3 |= SCR_EA_BIT; 231 #endif 232 233 #if RAS_TRAP_NS_ERR_REC_ACCESS 234 /* 235 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 236 * and RAS ERX registers from EL1 and EL2(from any security state) 237 * are trapped to EL3. 238 * Set here to trap only for NS EL1/EL2 239 * 240 */ 241 scr_el3 |= SCR_TERR_BIT; 242 #endif 243 244 if (is_feat_csv2_2_supported()) { 245 /* Enable access to the SCXTNUM_ELx registers. */ 246 scr_el3 |= SCR_EnSCXT_BIT; 247 } 248 249 #ifdef IMAGE_BL31 250 /* 251 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 252 * indicated by the interrupt routing model for BL31. 253 */ 254 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 255 #endif 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 258 /* Initialize EL1 context registers */ 259 setup_el1_context(ctx, ep); 260 261 /* Initialize EL2 context registers */ 262 #if CTX_INCLUDE_EL2_REGS 263 264 /* 265 * Initialize SCTLR_EL2 context register using Endianness value 266 * taken from the entrypoint attribute. 267 */ 268 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 269 sctlr_el2 |= SCTLR_EL2_RES1; 270 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 271 sctlr_el2); 272 273 if (is_feat_hcx_supported()) { 274 /* 275 * Initialize register HCRX_EL2 with its init value. 276 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 277 * chance that this can lead to unexpected behavior in lower 278 * ELs that have not been updated since the introduction of 279 * this feature if not properly initialized, especially when 280 * it comes to those bits that enable/disable traps. 281 */ 282 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 283 HCRX_EL2_INIT_VAL); 284 } 285 286 if (is_feat_fgt_supported()) { 287 /* 288 * Initialize HFG*_EL2 registers with a default value so legacy 289 * systems unaware of FEAT_FGT do not get trapped due to their lack 290 * of initialization for this feature. 291 */ 292 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 293 HFGITR_EL2_INIT_VAL); 294 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 295 HFGRTR_EL2_INIT_VAL); 296 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 297 HFGWTR_EL2_INIT_VAL); 298 } 299 #endif /* CTX_INCLUDE_EL2_REGS */ 300 301 manage_extensions_nonsecure(ctx); 302 } 303 304 /******************************************************************************* 305 * The following function performs initialization of the cpu_context 'ctx' 306 * for first use that is common to all security states, and sets the 307 * initial entrypoint state as specified by the entry_point_info structure. 308 * 309 * The EE and ST attributes are used to configure the endianness and secure 310 * timer availability for the new execution context. 311 ******************************************************************************/ 312 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 313 { 314 u_register_t cptr_el3; 315 u_register_t scr_el3; 316 el3_state_t *state; 317 gp_regs_t *gp_regs; 318 319 state = get_el3state_ctx(ctx); 320 321 /* Clear any residual register values from the context */ 322 zeromem(ctx, sizeof(*ctx)); 323 324 /* 325 * The lower-EL context is zeroed so that no stale values leak to a world. 326 * It is assumed that an all-zero lower-EL context is good enough for it 327 * to boot correctly. However, there are very few registers where this 328 * is not true and some values need to be recreated. 329 */ 330 #if CTX_INCLUDE_EL2_REGS 331 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 332 333 /* 334 * These bits are set in the gicv3 driver. Losing them (especially the 335 * SRE bit) is problematic for all worlds. Henceforth recreate them. 336 */ 337 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 338 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 339 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 340 #endif /* CTX_INCLUDE_EL2_REGS */ 341 342 /* 343 * SCR_EL3 was initialised during reset sequence in macro 344 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 345 * affect the next EL. 346 * 347 * The following fields are initially set to zero and then updated to 348 * the required value depending on the state of the SPSR_EL3 and the 349 * Security state and entrypoint attributes of the next EL. 350 */ 351 scr_el3 = read_scr(); 352 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 353 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 354 355 /* 356 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 357 * EL2, EL1 and EL0 are not trapped to EL3. 358 * 359 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 360 * EL2, EL1 and EL0 are not trapped to EL3. 361 * 362 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 363 * both Security states and both Execution states. 364 * 365 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 366 * Non-secure memory. 367 */ 368 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 369 370 scr_el3 |= SCR_SIF_BIT; 371 372 /* 373 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 374 * Exception level as specified by SPSR. 375 */ 376 if (GET_RW(ep->spsr) == MODE_RW_64) { 377 scr_el3 |= SCR_RW_BIT; 378 } 379 380 /* 381 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 382 * Secure timer registers to EL3, from AArch64 state only, if specified 383 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 384 * bit always behaves as 1 (i.e. secure physical timer register access 385 * is not trapped) 386 */ 387 if (EP_GET_ST(ep->h.attr) != 0U) { 388 scr_el3 |= SCR_ST_BIT; 389 } 390 391 /* 392 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 393 * SCR_EL3.HXEn. 394 */ 395 if (is_feat_hcx_supported()) { 396 scr_el3 |= SCR_HXEn_BIT; 397 } 398 399 /* 400 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 401 * registers are trapped to EL3. 402 */ 403 #if ENABLE_FEAT_RNG_TRAP 404 scr_el3 |= SCR_TRNDR_BIT; 405 #endif 406 407 #if FAULT_INJECTION_SUPPORT 408 /* Enable fault injection from lower ELs */ 409 scr_el3 |= SCR_FIEN_BIT; 410 #endif 411 412 #if CTX_INCLUDE_PAUTH_REGS 413 /* 414 * Enable Pointer Authentication globally for all the worlds. 415 * 416 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 417 * other than EL3 418 * 419 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 420 * than EL3 421 */ 422 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 423 #endif /* CTX_INCLUDE_PAUTH_REGS */ 424 425 /* 426 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 427 */ 428 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 429 scr_el3 |= SCR_TCR2EN_BIT; 430 } 431 432 /* 433 * SCR_EL3.PIEN: Enable permission indirection and overlay 434 * registers for AArch64 if present. 435 */ 436 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 437 scr_el3 |= SCR_PIEN_BIT; 438 } 439 440 /* 441 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 442 */ 443 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 444 scr_el3 |= SCR_GCSEn_BIT; 445 } 446 447 /* 448 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 449 * All fields are architecturally UNKNOWN on reset. 450 * 451 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 452 * by Advanced SIMD, floating-point or SVE instructions (if 453 * implemented) do not trap to EL3. 454 * 455 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 456 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 457 */ 458 cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT); 459 460 write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3); 461 462 /* 463 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 464 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 465 * next mode is Hyp. 466 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 467 * same conditions as HVC instructions and when the processor supports 468 * ARMv8.6-FGT. 469 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 470 * CNTPOFF_EL2 register under the same conditions as HVC instructions 471 * and when the processor supports ECV. 472 */ 473 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 474 || ((GET_RW(ep->spsr) != MODE_RW_64) 475 && (GET_M32(ep->spsr) == MODE32_hyp))) { 476 scr_el3 |= SCR_HCE_BIT; 477 478 if (is_feat_fgt_supported()) { 479 scr_el3 |= SCR_FGTEN_BIT; 480 } 481 482 if (is_feat_ecv_supported()) { 483 scr_el3 |= SCR_ECVEN_BIT; 484 } 485 } 486 487 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 488 if (is_feat_twed_supported()) { 489 /* Set delay in SCR_EL3 */ 490 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 491 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 492 << SCR_TWEDEL_SHIFT); 493 494 /* Enable WFE delay */ 495 scr_el3 |= SCR_TWEDEn_BIT; 496 } 497 498 /* 499 * Populate EL3 state so that we've the right context 500 * before doing ERET 501 */ 502 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 503 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 504 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 505 506 /* 507 * Store the X0-X7 value from the entrypoint into the context 508 * Use memcpy as we are in control of the layout of the structures 509 */ 510 gp_regs = get_gpregs_ctx(ctx); 511 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 512 } 513 514 /******************************************************************************* 515 * Context management library initialization routine. This library is used by 516 * runtime services to share pointers to 'cpu_context' structures for secure 517 * non-secure and realm states. Management of the structures and their associated 518 * memory is not done by the context management library e.g. the PSCI service 519 * manages the cpu context used for entry from and exit to the non-secure state. 520 * The Secure payload dispatcher service manages the context(s) corresponding to 521 * the secure state. It also uses this library to get access to the non-secure 522 * state cpu context pointers. 523 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 524 * which will be used for programming an entry into a lower EL. The same context 525 * will be used to save state upon exception entry from that EL. 526 ******************************************************************************/ 527 void __init cm_init(void) 528 { 529 /* 530 * The context management library has only global data to initialize, but 531 * that will be done when the BSS is zeroed out. 532 */ 533 } 534 535 /******************************************************************************* 536 * This is the high-level function used to initialize the cpu_context 'ctx' for 537 * first use. It performs initializations that are common to all security states 538 * and initializations specific to the security state specified in 'ep' 539 ******************************************************************************/ 540 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 541 { 542 unsigned int security_state; 543 544 assert(ctx != NULL); 545 546 /* 547 * Perform initializations that are common 548 * to all security states 549 */ 550 setup_context_common(ctx, ep); 551 552 security_state = GET_SECURITY_STATE(ep->h.attr); 553 554 /* Perform security state specific initializations */ 555 switch (security_state) { 556 case SECURE: 557 setup_secure_context(ctx, ep); 558 break; 559 #if ENABLE_RME 560 case REALM: 561 setup_realm_context(ctx, ep); 562 break; 563 #endif 564 case NON_SECURE: 565 setup_ns_context(ctx, ep); 566 break; 567 default: 568 ERROR("Invalid security state\n"); 569 panic(); 570 break; 571 } 572 } 573 574 /******************************************************************************* 575 * Enable architecture extensions for EL3 execution. This function only updates 576 * registers in-place which are expected to either never change or be 577 * overwritten by el3_exit. 578 ******************************************************************************/ 579 #if IMAGE_BL31 580 void cm_manage_extensions_el3(void) 581 { 582 if (is_feat_spe_supported()) { 583 spe_init_el3(); 584 } 585 586 if (is_feat_amu_supported()) { 587 amu_init_el3(); 588 } 589 590 if (is_feat_sme_supported()) { 591 sme_init_el3(); 592 } 593 594 if (is_feat_mpam_supported()) { 595 mpam_init_el3(); 596 } 597 598 if (is_feat_trbe_supported()) { 599 trbe_init_el3(); 600 } 601 602 if (is_feat_brbe_supported()) { 603 brbe_init_el3(); 604 } 605 606 if (is_feat_trf_supported()) { 607 trf_init_el3(); 608 } 609 610 pmuv3_init_el3(); 611 } 612 #endif /* IMAGE_BL31 */ 613 614 /******************************************************************************* 615 * Enable architecture extensions on first entry to Non-secure world. 616 ******************************************************************************/ 617 static void manage_extensions_nonsecure(cpu_context_t *ctx) 618 { 619 #if IMAGE_BL31 620 if (is_feat_amu_supported()) { 621 amu_enable(ctx); 622 } 623 624 /* Enable SVE and FPU/SIMD */ 625 if (is_feat_sve_supported()) { 626 sve_enable(ctx); 627 } 628 629 if (is_feat_sme_supported()) { 630 sme_enable(ctx); 631 } 632 633 if (is_feat_sys_reg_trace_supported()) { 634 sys_reg_trace_enable(ctx); 635 } 636 637 pmuv3_enable(ctx); 638 #endif /* IMAGE_BL31 */ 639 } 640 641 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 642 static __unused void enable_pauth_el2(void) 643 { 644 u_register_t hcr_el2 = read_hcr_el2(); 645 /* 646 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 647 * accessing key registers or using pointer authentication instructions 648 * from lower ELs. 649 */ 650 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 651 652 write_hcr_el2(hcr_el2); 653 } 654 655 /******************************************************************************* 656 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 657 * world when EL2 is empty and unused. 658 ******************************************************************************/ 659 static void manage_extensions_nonsecure_el2_unused(void) 660 { 661 #if IMAGE_BL31 662 if (is_feat_spe_supported()) { 663 spe_init_el2_unused(); 664 } 665 666 if (is_feat_amu_supported()) { 667 amu_init_el2_unused(); 668 } 669 670 if (is_feat_mpam_supported()) { 671 mpam_init_el2_unused(); 672 } 673 674 if (is_feat_trbe_supported()) { 675 trbe_init_el2_unused(); 676 } 677 678 if (is_feat_sys_reg_trace_supported()) { 679 sys_reg_trace_init_el2_unused(); 680 } 681 682 if (is_feat_trf_supported()) { 683 trf_init_el2_unused(); 684 } 685 686 pmuv3_init_el2_unused(); 687 688 if (is_feat_sve_supported()) { 689 sve_init_el2_unused(); 690 } 691 692 if (is_feat_sme_supported()) { 693 sme_init_el2_unused(); 694 } 695 696 #if ENABLE_PAUTH 697 enable_pauth_el2(); 698 #endif /* ENABLE_PAUTH */ 699 #endif /* IMAGE_BL31 */ 700 } 701 702 /******************************************************************************* 703 * Enable architecture extensions on first entry to Secure world. 704 ******************************************************************************/ 705 static void manage_extensions_secure(cpu_context_t *ctx) 706 { 707 #if IMAGE_BL31 708 if (is_feat_sve_supported()) { 709 if (ENABLE_SVE_FOR_SWD) { 710 /* 711 * Enable SVE and FPU in secure context, secure manager must 712 * ensure that the SVE and FPU register contexts are properly 713 * managed. 714 */ 715 sve_enable(ctx); 716 } else { 717 /* 718 * Disable SVE and FPU in secure context so non-secure world 719 * can safely use them. 720 */ 721 sve_disable(ctx); 722 } 723 } 724 725 if (is_feat_sme_supported()) { 726 if (ENABLE_SME_FOR_SWD) { 727 /* 728 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 729 * must ensure SME, SVE, and FPU/SIMD context properly managed. 730 */ 731 sme_init_el3(); 732 sme_enable(ctx); 733 } else { 734 /* 735 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 736 * world can safely use the associated registers. 737 */ 738 sme_disable(ctx); 739 } 740 } 741 742 /* NS can access this but Secure shouldn't */ 743 if (is_feat_sys_reg_trace_supported()) { 744 sys_reg_trace_disable(ctx); 745 } 746 #endif /* IMAGE_BL31 */ 747 } 748 749 /******************************************************************************* 750 * The following function initializes the cpu_context for a CPU specified by 751 * its `cpu_idx` for first use, and sets the initial entrypoint state as 752 * specified by the entry_point_info structure. 753 ******************************************************************************/ 754 void cm_init_context_by_index(unsigned int cpu_idx, 755 const entry_point_info_t *ep) 756 { 757 cpu_context_t *ctx; 758 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 759 cm_setup_context(ctx, ep); 760 } 761 762 /******************************************************************************* 763 * The following function initializes the cpu_context for the current CPU 764 * for first use, and sets the initial entrypoint state as specified by the 765 * entry_point_info structure. 766 ******************************************************************************/ 767 void cm_init_my_context(const entry_point_info_t *ep) 768 { 769 cpu_context_t *ctx; 770 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 771 cm_setup_context(ctx, ep); 772 } 773 774 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 775 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 776 { 777 u_register_t hcr_el2 = HCR_RESET_VAL; 778 u_register_t mdcr_el2; 779 u_register_t scr_el3; 780 781 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 782 783 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 784 if ((scr_el3 & SCR_RW_BIT) != 0U) { 785 hcr_el2 |= HCR_RW_BIT; 786 } 787 788 write_hcr_el2(hcr_el2); 789 790 /* 791 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 792 * All fields have architecturally UNKNOWN reset values. 793 */ 794 write_cptr_el2(CPTR_EL2_RESET_VAL); 795 796 /* 797 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 798 * reset and are set to zero except for field(s) listed below. 799 * 800 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 801 * Non-secure EL0 and EL1 accesses to the physical timer registers. 802 * 803 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 804 * Non-secure EL0 and EL1 accesses to the physical counter registers. 805 */ 806 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 807 808 /* 809 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 810 * UNKNOWN value. 811 */ 812 write_cntvoff_el2(0); 813 814 /* 815 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 816 * respectively. 817 */ 818 write_vpidr_el2(read_midr_el1()); 819 write_vmpidr_el2(read_mpidr_el1()); 820 821 /* 822 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 823 * 824 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 825 * translation is disabled, cache maintenance operations depend on the 826 * VMID. 827 * 828 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 829 * disabled. 830 */ 831 write_vttbr_el2(VTTBR_RESET_VAL & 832 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 833 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 834 835 /* 836 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 837 * Some fields are architecturally UNKNOWN on reset. 838 * 839 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 840 * register accesses to the Debug ROM registers are not trapped to EL2. 841 * 842 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 843 * accesses to the powerdown debug registers are not trapped to EL2. 844 * 845 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 846 * debug registers do not trap to EL2. 847 * 848 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 849 * EL2. 850 */ 851 mdcr_el2 = MDCR_EL2_RESET_VAL & 852 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 853 MDCR_EL2_TDE_BIT); 854 855 write_mdcr_el2(mdcr_el2); 856 857 /* 858 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 859 * 860 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 861 * EL1 accesses to System registers do not trap to EL2. 862 */ 863 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 864 865 /* 866 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 867 * reset. 868 * 869 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 870 * and prevent timer interrupts. 871 */ 872 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 873 874 manage_extensions_nonsecure_el2_unused(); 875 } 876 877 /******************************************************************************* 878 * Prepare the CPU system registers for first entry into realm, secure, or 879 * normal world. 880 * 881 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 882 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 883 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 884 * For all entries, the EL1 registers are initialized from the cpu_context 885 ******************************************************************************/ 886 void cm_prepare_el3_exit(uint32_t security_state) 887 { 888 u_register_t sctlr_elx, scr_el3; 889 cpu_context_t *ctx = cm_get_context(security_state); 890 891 assert(ctx != NULL); 892 893 if (security_state == NON_SECURE) { 894 uint64_t el2_implemented = el_implemented(2); 895 896 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 897 CTX_SCR_EL3); 898 899 if (((scr_el3 & SCR_HCE_BIT) != 0U) 900 || (el2_implemented != EL_IMPL_NONE)) { 901 /* 902 * If context is not being used for EL2, initialize 903 * HCRX_EL2 with its init value here. 904 */ 905 if (is_feat_hcx_supported()) { 906 write_hcrx_el2(HCRX_EL2_INIT_VAL); 907 } 908 909 /* 910 * Initialize Fine-grained trap registers introduced 911 * by FEAT_FGT so all traps are initially disabled when 912 * switching to EL2 or a lower EL, preventing undesired 913 * behavior. 914 */ 915 if (is_feat_fgt_supported()) { 916 /* 917 * Initialize HFG*_EL2 registers with a default 918 * value so legacy systems unaware of FEAT_FGT 919 * do not get trapped due to their lack of 920 * initialization for this feature. 921 */ 922 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 923 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 924 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 925 } 926 } 927 928 929 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 930 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 931 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 932 CTX_SCTLR_EL1); 933 sctlr_elx &= SCTLR_EE_BIT; 934 sctlr_elx |= SCTLR_EL2_RES1; 935 #if ERRATA_A75_764081 936 /* 937 * If workaround of errata 764081 for Cortex-A75 is used 938 * then set SCTLR_EL2.IESB to enable Implicit Error 939 * Synchronization Barrier. 940 */ 941 sctlr_elx |= SCTLR_IESB_BIT; 942 #endif 943 write_sctlr_el2(sctlr_elx); 944 } else if (el2_implemented != EL_IMPL_NONE) { 945 init_nonsecure_el2_unused(ctx); 946 } 947 } 948 949 cm_el1_sysregs_context_restore(security_state); 950 cm_set_next_eret_context(security_state); 951 } 952 953 #if CTX_INCLUDE_EL2_REGS 954 955 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 956 { 957 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 958 if (is_feat_amu_supported()) { 959 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 960 } 961 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 962 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 963 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 964 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 965 } 966 967 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 968 { 969 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 970 if (is_feat_amu_supported()) { 971 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 972 } 973 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 974 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 975 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 976 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 977 } 978 979 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 980 { 981 u_register_t mpam_idr = read_mpamidr_el1(); 982 983 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 984 985 /* 986 * The context registers that we intend to save would be part of the 987 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 988 */ 989 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 990 return; 991 } 992 993 /* 994 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 995 * MPAMIDR_HAS_HCR_BIT == 1. 996 */ 997 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 998 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 999 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 1000 1001 /* 1002 * The number of MPAMVPM registers is implementation defined, their 1003 * number is stored in the MPAMIDR_EL1 register. 1004 */ 1005 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1006 case 7: 1007 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 1008 __fallthrough; 1009 case 6: 1010 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1011 __fallthrough; 1012 case 5: 1013 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1014 __fallthrough; 1015 case 4: 1016 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1017 __fallthrough; 1018 case 3: 1019 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1020 __fallthrough; 1021 case 2: 1022 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1023 __fallthrough; 1024 case 1: 1025 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1026 break; 1027 } 1028 } 1029 1030 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1031 { 1032 u_register_t mpam_idr = read_mpamidr_el1(); 1033 1034 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1035 1036 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1037 return; 1038 } 1039 1040 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1041 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1042 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1043 1044 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1045 case 7: 1046 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1047 __fallthrough; 1048 case 6: 1049 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1050 __fallthrough; 1051 case 5: 1052 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1053 __fallthrough; 1054 case 4: 1055 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1056 __fallthrough; 1057 case 3: 1058 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1059 __fallthrough; 1060 case 2: 1061 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1062 __fallthrough; 1063 case 1: 1064 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1065 break; 1066 } 1067 } 1068 1069 /* ----------------------------------------------------- 1070 * The following registers are not added: 1071 * AMEVCNTVOFF0<n>_EL2 1072 * AMEVCNTVOFF1<n>_EL2 1073 * ICH_AP0R<n>_EL2 1074 * ICH_AP1R<n>_EL2 1075 * ICH_LR<n>_EL2 1076 * ----------------------------------------------------- 1077 */ 1078 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1079 { 1080 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1081 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1082 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1083 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1084 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1085 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1086 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1087 if (CTX_INCLUDE_AARCH32_REGS) { 1088 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1089 } 1090 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1091 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1092 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1093 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1094 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1095 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1096 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1097 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1098 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1099 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1100 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1101 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1102 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1103 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1104 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1105 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1106 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1107 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1108 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1109 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1110 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1111 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1112 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1113 } 1114 1115 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1116 { 1117 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1118 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1119 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1120 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1121 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1122 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1123 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1124 if (CTX_INCLUDE_AARCH32_REGS) { 1125 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1126 } 1127 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1128 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1129 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1130 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1131 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1132 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1133 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1134 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1135 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1136 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1137 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1138 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1139 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1140 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1141 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1142 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1143 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1144 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1145 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1146 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1147 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1148 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1149 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1150 } 1151 1152 /******************************************************************************* 1153 * Save EL2 sysreg context 1154 ******************************************************************************/ 1155 void cm_el2_sysregs_context_save(uint32_t security_state) 1156 { 1157 u_register_t scr_el3 = read_scr(); 1158 1159 /* 1160 * Always save the non-secure and realm EL2 context, only save the 1161 * S-EL2 context if S-EL2 is enabled. 1162 */ 1163 if ((security_state != SECURE) || 1164 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1165 cpu_context_t *ctx; 1166 el2_sysregs_t *el2_sysregs_ctx; 1167 1168 ctx = cm_get_context(security_state); 1169 assert(ctx != NULL); 1170 1171 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1172 1173 el2_sysregs_context_save_common(el2_sysregs_ctx); 1174 #if CTX_INCLUDE_MTE_REGS 1175 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1176 #endif 1177 if (is_feat_mpam_supported()) { 1178 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1179 } 1180 1181 if (is_feat_fgt_supported()) { 1182 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1183 } 1184 1185 if (is_feat_ecv_v2_supported()) { 1186 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 1187 read_cntpoff_el2()); 1188 } 1189 1190 if (is_feat_vhe_supported()) { 1191 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1192 read_contextidr_el2()); 1193 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1194 read_ttbr1_el2()); 1195 } 1196 1197 if (is_feat_ras_supported()) { 1198 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, 1199 read_vdisr_el2()); 1200 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, 1201 read_vsesr_el2()); 1202 } 1203 1204 if (is_feat_nv2_supported()) { 1205 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1206 read_vncr_el2()); 1207 } 1208 1209 if (is_feat_trf_supported()) { 1210 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1211 } 1212 1213 if (is_feat_csv2_2_supported()) { 1214 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1215 read_scxtnum_el2()); 1216 } 1217 1218 if (is_feat_hcx_supported()) { 1219 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1220 } 1221 if (is_feat_tcr2_supported()) { 1222 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1223 } 1224 if (is_feat_sxpie_supported()) { 1225 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1226 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1227 } 1228 if (is_feat_s2pie_supported()) { 1229 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1230 } 1231 if (is_feat_sxpoe_supported()) { 1232 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1233 } 1234 if (is_feat_gcs_supported()) { 1235 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1236 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1237 } 1238 } 1239 } 1240 1241 /******************************************************************************* 1242 * Restore EL2 sysreg context 1243 ******************************************************************************/ 1244 void cm_el2_sysregs_context_restore(uint32_t security_state) 1245 { 1246 u_register_t scr_el3 = read_scr(); 1247 1248 /* 1249 * Always restore the non-secure and realm EL2 context, only restore the 1250 * S-EL2 context if S-EL2 is enabled. 1251 */ 1252 if ((security_state != SECURE) || 1253 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1254 cpu_context_t *ctx; 1255 el2_sysregs_t *el2_sysregs_ctx; 1256 1257 ctx = cm_get_context(security_state); 1258 assert(ctx != NULL); 1259 1260 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1261 1262 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1263 #if CTX_INCLUDE_MTE_REGS 1264 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1265 #endif 1266 if (is_feat_mpam_supported()) { 1267 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1268 } 1269 1270 if (is_feat_fgt_supported()) { 1271 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1272 } 1273 1274 if (is_feat_ecv_v2_supported()) { 1275 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1276 CTX_CNTPOFF_EL2)); 1277 } 1278 1279 if (is_feat_vhe_supported()) { 1280 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1281 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1282 } 1283 1284 if (is_feat_ras_supported()) { 1285 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1286 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1287 } 1288 1289 if (is_feat_nv2_supported()) { 1290 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1291 } 1292 if (is_feat_trf_supported()) { 1293 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1294 } 1295 1296 if (is_feat_csv2_2_supported()) { 1297 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1298 CTX_SCXTNUM_EL2)); 1299 } 1300 1301 if (is_feat_hcx_supported()) { 1302 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1303 } 1304 if (is_feat_tcr2_supported()) { 1305 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1306 } 1307 if (is_feat_sxpie_supported()) { 1308 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1309 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1310 } 1311 if (is_feat_s2pie_supported()) { 1312 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1313 } 1314 if (is_feat_sxpoe_supported()) { 1315 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1316 } 1317 if (is_feat_gcs_supported()) { 1318 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1319 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1320 } 1321 } 1322 } 1323 #endif /* CTX_INCLUDE_EL2_REGS */ 1324 1325 /******************************************************************************* 1326 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1327 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1328 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1329 * cm_prepare_el3_exit function. 1330 ******************************************************************************/ 1331 void cm_prepare_el3_exit_ns(void) 1332 { 1333 #if CTX_INCLUDE_EL2_REGS 1334 #if ENABLE_ASSERTIONS 1335 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1336 assert(ctx != NULL); 1337 1338 /* Assert that EL2 is used. */ 1339 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1340 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1341 (el_implemented(2U) != EL_IMPL_NONE)); 1342 #endif /* ENABLE_ASSERTIONS */ 1343 1344 /* 1345 * Set the NS bit to be able to access the ICC_SRE_EL2 1346 * register when restoring context. 1347 */ 1348 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1349 1350 /* 1351 * Ensure the NS bit change is committed before the EL2/EL1 1352 * state restoration. 1353 */ 1354 isb(); 1355 1356 /* Restore EL2 and EL1 sysreg contexts */ 1357 cm_el2_sysregs_context_restore(NON_SECURE); 1358 cm_el1_sysregs_context_restore(NON_SECURE); 1359 cm_set_next_eret_context(NON_SECURE); 1360 #else 1361 cm_prepare_el3_exit(NON_SECURE); 1362 #endif /* CTX_INCLUDE_EL2_REGS */ 1363 } 1364 1365 /******************************************************************************* 1366 * The next four functions are used by runtime services to save and restore 1367 * EL1 context on the 'cpu_context' structure for the specified security 1368 * state. 1369 ******************************************************************************/ 1370 void cm_el1_sysregs_context_save(uint32_t security_state) 1371 { 1372 cpu_context_t *ctx; 1373 1374 ctx = cm_get_context(security_state); 1375 assert(ctx != NULL); 1376 1377 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1378 1379 #if IMAGE_BL31 1380 if (security_state == SECURE) 1381 PUBLISH_EVENT(cm_exited_secure_world); 1382 else 1383 PUBLISH_EVENT(cm_exited_normal_world); 1384 #endif 1385 } 1386 1387 void cm_el1_sysregs_context_restore(uint32_t security_state) 1388 { 1389 cpu_context_t *ctx; 1390 1391 ctx = cm_get_context(security_state); 1392 assert(ctx != NULL); 1393 1394 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1395 1396 #if IMAGE_BL31 1397 if (security_state == SECURE) 1398 PUBLISH_EVENT(cm_entering_secure_world); 1399 else 1400 PUBLISH_EVENT(cm_entering_normal_world); 1401 #endif 1402 } 1403 1404 /******************************************************************************* 1405 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1406 * given security state with the given entrypoint 1407 ******************************************************************************/ 1408 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1409 { 1410 cpu_context_t *ctx; 1411 el3_state_t *state; 1412 1413 ctx = cm_get_context(security_state); 1414 assert(ctx != NULL); 1415 1416 /* Populate EL3 state so that ERET jumps to the correct entry */ 1417 state = get_el3state_ctx(ctx); 1418 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1419 } 1420 1421 /******************************************************************************* 1422 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1423 * pertaining to the given security state 1424 ******************************************************************************/ 1425 void cm_set_elr_spsr_el3(uint32_t security_state, 1426 uintptr_t entrypoint, uint32_t spsr) 1427 { 1428 cpu_context_t *ctx; 1429 el3_state_t *state; 1430 1431 ctx = cm_get_context(security_state); 1432 assert(ctx != NULL); 1433 1434 /* Populate EL3 state so that ERET jumps to the correct entry */ 1435 state = get_el3state_ctx(ctx); 1436 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1437 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1438 } 1439 1440 /******************************************************************************* 1441 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1442 * pertaining to the given security state using the value and bit position 1443 * specified in the parameters. It preserves all other bits. 1444 ******************************************************************************/ 1445 void cm_write_scr_el3_bit(uint32_t security_state, 1446 uint32_t bit_pos, 1447 uint32_t value) 1448 { 1449 cpu_context_t *ctx; 1450 el3_state_t *state; 1451 u_register_t scr_el3; 1452 1453 ctx = cm_get_context(security_state); 1454 assert(ctx != NULL); 1455 1456 /* Ensure that the bit position is a valid one */ 1457 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1458 1459 /* Ensure that the 'value' is only a bit wide */ 1460 assert(value <= 1U); 1461 1462 /* 1463 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1464 * and set it to its new value. 1465 */ 1466 state = get_el3state_ctx(ctx); 1467 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1468 scr_el3 &= ~(1UL << bit_pos); 1469 scr_el3 |= (u_register_t)value << bit_pos; 1470 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1471 } 1472 1473 /******************************************************************************* 1474 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1475 * given security state. 1476 ******************************************************************************/ 1477 u_register_t cm_get_scr_el3(uint32_t security_state) 1478 { 1479 cpu_context_t *ctx; 1480 el3_state_t *state; 1481 1482 ctx = cm_get_context(security_state); 1483 assert(ctx != NULL); 1484 1485 /* Populate EL3 state so that ERET jumps to the correct entry */ 1486 state = get_el3state_ctx(ctx); 1487 return read_ctx_reg(state, CTX_SCR_EL3); 1488 } 1489 1490 /******************************************************************************* 1491 * This function is used to program the context that's used for exception 1492 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1493 * the required security state 1494 ******************************************************************************/ 1495 void cm_set_next_eret_context(uint32_t security_state) 1496 { 1497 cpu_context_t *ctx; 1498 1499 ctx = cm_get_context(security_state); 1500 assert(ctx != NULL); 1501 1502 cm_set_next_context(ctx); 1503 } 1504