1/* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* 28 * ERRATA_DSU_2313941: 29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 30 * Henceforth creating symbolic names to the already existing errata 31 * workaround functions to get them registered under the Errata Framework. 32 */ 33.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 36 37workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 38 /* Apply instruction patching sequence */ 39 ldr x0,=0x6 40 msr S3_6_c15_c8_0,x0 41 ldr x0,=0xF3A08002 42 msr S3_6_c15_c8_2,x0 43 ldr x0,=0xFFF0F7FE 44 msr S3_6_c15_c8_3,x0 45 ldr x0,=0x40000001003ff 46 msr S3_6_c15_c8_1,x0 47 ldr x0,=0x7 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xBF200000 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFEF0000 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003f3 54 msr S3_6_c15_c8_1,x0 55workaround_reset_end neoverse_n2, ERRATUM(2002655) 56 57check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 58 59workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 60 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 61workaround_reset_end neoverse_n2, ERRATUM(2025414) 62 63check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 64 65workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 66 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 67workaround_reset_end neoverse_n2, ERRATUM(2067956) 68 69check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 70 71workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 72 /* Stash ERRSELR_EL1 in x2 */ 73 mrs x2, ERRSELR_EL1 74 75 /* Select error record 0 and clear ED bit */ 76 msr ERRSELR_EL1, xzr 77 mrs x1, ERXCTLR_EL1 78 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 79 msr ERXCTLR_EL1, x1 80 81 /* Restore ERRSELR_EL1 from x2 */ 82 msr ERRSELR_EL1, x2 83workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 84 85check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 86 87workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 88 /* Apply instruction patching sequence */ 89 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 90 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 91 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 92 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 93workaround_reset_end neoverse_n2, ERRATUM(2138953) 94 95check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 96 97workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 98 /* Apply instruction patching sequence */ 99 ldr x0,=0x3 100 msr S3_6_c15_c8_0,x0 101 ldr x0,=0xF3A08002 102 msr S3_6_c15_c8_2,x0 103 ldr x0,=0xFFF0F7FE 104 msr S3_6_c15_c8_3,x0 105 ldr x0,=0x10002001003FF 106 msr S3_6_c15_c8_1,x0 107 ldr x0,=0x4 108 msr S3_6_c15_c8_0,x0 109 ldr x0,=0xBF200000 110 msr S3_6_c15_c8_2,x0 111 ldr x0,=0xFFEF0000 112 msr S3_6_c15_c8_3,x0 113 ldr x0,=0x10002001003F3 114 msr S3_6_c15_c8_1,x0 115workaround_reset_end neoverse_n2, ERRATUM(2138956) 116 117check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 118 119 120workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 121 /* Apply instruction patching sequence */ 122 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 123workaround_reset_end neoverse_n2, ERRATUM(2138958) 124 125check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 126 127workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 128 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 129workaround_reset_end neoverse_n2, ERRATUM(2189731) 130 131check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 132 133workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 134 /* Apply instruction patching sequence */ 135 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 136 ldr x0, =0x2 137 msr S3_6_c15_c8_0, x0 138 ldr x0, =0x10F600E000 139 msr S3_6_c15_c8_2, x0 140 ldr x0, =0x10FF80E000 141 msr S3_6_c15_c8_3, x0 142 ldr x0, =0x80000000003FF 143 msr S3_6_c15_c8_1, x0 144workaround_reset_end neoverse_n2, ERRATUM(2242400) 145 146check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 147 148workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 149 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 150workaround_reset_end neoverse_n2, ERRATUM(2242415) 151 152check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 153 154workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 155 /* Apply instruction patching sequence */ 156 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 157workaround_reset_end neoverse_n2, ERRATUM(2280757) 158 159check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 160 161workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 162 /* Set bit 36 in ACTLR2_EL1 */ 163 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 164workaround_runtime_end neoverse_n2, ERRATUM(2326639) 165 166check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 167 168workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 169 /* Set TXREQ to STATIC and full L2 TQ size */ 170 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 171 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 172 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 173 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 174workaround_runtime_end neoverse_n2, ERRATUM(2346952) 175 176check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 177 178workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 179 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 180 * ST to behave like PLD/PFRM LD and not cause 181 * invalidations to other PE caches. 182 */ 183 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 184workaround_reset_end neoverse_n2, ERRATUM(2376738) 185 186check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 187 188workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 189 /*Set bit 40 in ACTLR2_EL1 */ 190 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 191workaround_reset_end neoverse_n2, ERRATUM(2388450) 192 193check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 194 195workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 196 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 197 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 198 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 199workaround_reset_end neoverse_n2, ERRATUM(2743014) 200 201check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 202 203workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 204 /* dsb before isb of power down sequence */ 205 dsb sy 206workaround_runtime_end neoverse_n2, ERRATUM(2743089) 207 208check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 209 210workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 211 /* Set bit 47 in ACTLR3_EL1 */ 212 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 213workaround_reset_end neoverse_n2, ERRATUM(2779511) 214 215check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 216 217workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 218#if IMAGE_BL31 219 /* 220 * The Neoverse-N2 generic vectors are overridden to apply errata 221 * mitigation on exception entry from lower ELs. 222 */ 223 override_vector_table wa_cve_vbar_neoverse_n2 224#endif /* IMAGE_BL31 */ 225workaround_reset_end neoverse_n2, CVE(2022,23960) 226 227check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 228 229 /* ------------------------------------------- 230 * The CPU Ops reset function for Neoverse N2. 231 * ------------------------------------------- 232 */ 233cpu_reset_func_start neoverse_n2 234 235 /* Check if the PE implements SSBS */ 236 mrs x0, id_aa64pfr1_el1 237 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 238 b.eq 1f 239 240 /* Disable speculative loads */ 241 msr SSBS, xzr 2421: 243 /* Force all cacheable atomic instructions to be near */ 244 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 245 246#if ENABLE_FEAT_AMU 247 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 248 sysreg_bit_set cptr_el3, TAM_BIT 249 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 250 sysreg_bit_set cptr_el2, TAM_BIT 251 /* No need to enable the counters as this would be done at el3 exit */ 252#endif 253 254#if NEOVERSE_Nx_EXTERNAL_LLC 255 /* Some systems may have External LLC, core needs to be made aware */ 256 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 257#endif 258cpu_reset_func_end neoverse_n2 259 260func neoverse_n2_core_pwr_dwn 261 262 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 263 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 264 265 /* --------------------------------------------------- 266 * Enable CPU power down bit in power control register 267 * No need to do cache maintenance here. 268 * --------------------------------------------------- 269 */ 270 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 271 272 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 273 274 isb 275 ret 276endfunc neoverse_n2_core_pwr_dwn 277 278errata_report_shim neoverse_n2 279 280 /* --------------------------------------------- 281 * This function provides Neoverse N2 specific 282 * register information for crash reporting. 283 * It needs to return with x6 pointing to 284 * a list of register names in ASCII and 285 * x8 - x15 having values of registers to be 286 * reported. 287 * --------------------------------------------- 288 */ 289.section .rodata.neoverse_n2_regs, "aS" 290neoverse_n2_regs: /* The ASCII list of register names to be reported */ 291 .asciz "cpupwrctlr_el1", "" 292 293func neoverse_n2_cpu_reg_dump 294 adr x6, neoverse_n2_regs 295 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 296 ret 297endfunc neoverse_n2_cpu_reg_dump 298 299declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 300 neoverse_n2_reset_func, \ 301 neoverse_n2_core_pwr_dwn 302