Merge pull request #1533 from jeenu-arm/mpam

AArch64: Enable MPAM for lower ELs

RAS: MISRA fixes

These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I76cacf6e1d73b09510561b5090c2bb66d8

RAS: MISRA fixes

These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I76cacf6e1d73b09510561b5090c2bb66d81bec88
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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SDEI: MISRA fixes

These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I6235a355e006f0b1c7c1c4d811b3964a6

SDEI: MISRA fixes

These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I6235a355e006f0b1c7c1c4d811b3964a64d0434f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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AArch64: Enable MPAM for lower ELs

Memory Partitioning And Monitoring is an Armv8.4 feature that enables
various memory system components and resources to define partitions.
Software running at vari

AArch64: Enable MPAM for lower ELs

Memory Partitioning And Monitoring is an Armv8.4 feature that enables
various memory system components and resources to define partitions.
Software running at various ELs can then assign themselves to the
desired partition to control their performance aspects.

With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
lower ELs to access their own MPAM registers without trapping to EL3.
This patch however doesn't make use of partitioning in EL3; platform
initialisation code should configure and use partitions in EL3 if
required.

Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd
Co-authored-by: James Morse <james.morse@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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DSU erratum 936184 workaround

If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.

This DSU erratu

DSU erratum 936184 workaround

If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.

This DSU erratum affects only the DSUs that contain the ACP interface
and it was fixed in r2p0. The workaround is applied only to the DSUs
that are actually affected.

Link to respective Arm documentation:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html

Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge pull request #1510 from robertovargas-arm/romlib

Add support for moving libraries to ROM

xlat v2: Support the EL2 translation regime

The translation library is useful elsewhere. Even though this repository
doesn't exercise the EL2 support of the library, it is better to have it
here as

xlat v2: Support the EL2 translation regime

The translation library is useful elsewhere. Even though this repository
doesn't exercise the EL2 support of the library, it is better to have it
here as well to make it easier to maintain.

enable_mmu_secure() and enable_mmu_direct() have been deprecated. The
functions are still present, but they are behind ERROR_DEPRECATED and
they call the new functions enable_mmu_svc_mon() and
enable_mmu_direct_svc_mon().

Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat v2: Cleanup get/change mem attr helpers

Changed the names for consistency with the rest of the library. Introduced
new helpers that manipulate the active translation tables context.

Change-Id:

xlat v2: Cleanup get/change mem attr helpers

Changed the names for consistency with the rest of the library. Introduced
new helpers that manipulate the active translation tables context.

Change-Id: Icaca56b67fcf6a96e88aa3c7e47411162e8e6856
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Create a library file for libc

TF Makefile was linking all the objects files generated for the
c library instead of creating a static library that could be
used in the linking stage.

Change-Id: I72

Create a library file for libc

TF Makefile was linking all the objects files generated for the
c library instead of creating a static library that could be
used in the linking stage.

Change-Id: I721daea097e9b13cbb42c9f8eaa2af8fea0799cf
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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xlat: Use bool instead of int

Change-Id: I35d5b6a7c219f6f38983b30f157c1ed3808af17f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Define bool type

This would enable us to write semantically sensible code.

Change-Id: Ie7c75f9c024f671a037448f5c0922174fff3f0ce
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

xlat: Fix MISRA defects

Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.

Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9

xlat: Fix MISRA defects

Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.

Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

Merge pull request #1485 from jeenu-arm/ras

Double-fault and fatal error handling support

PSCI: Fix MISRA defects in common and setup code

MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7.

Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064
Signed-off-by: Antonio Nino Diaz <antonio.ninodia

PSCI: Fix MISRA defects in common and setup code

MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7.

Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>

PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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PMF: Fix MISRA defects

Fix instances of MISRA C-2012 Rule 10.1 and 21.1.

Change-Id: I5676edede0703481e3635be0bc4a635df8e48f5e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI: Add missing function argument names

Fix MISRA C-2012 Rules 8.2 and 21.1.

Change-Id: I7f41fe76fe16399734d11847ab601ad8eb78df1a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI: Replace macros by static inline functions

Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects.

Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2
Signed-off-by: Antonio Nino Diaz <antonio.

PSCI: Replace macros by static inline functions

Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects.

Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Fix check_[uptr/u32]_overflow() macros MISRA defects

Add missing parentheses to fix MISRA C-2012 Rule 12.1.

Also, the result of a comparison is an essentially boolean value, it
isn't needed to retu

Fix check_[uptr/u32]_overflow() macros MISRA defects

Add missing parentheses to fix MISRA C-2012 Rule 12.1.

Also, the result of a comparison is an essentially boolean value, it
isn't needed to return 1 or 0 depending on it.

Also, fix header guards (MISRA C-2012 Rule 21.1).

Change-Id: I90c0bcdeb2787c1ca659fc9a981808ece7958de3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Introduce UL(), L() and LL() macros

utils_def.h already has U() and ULL(), but not UL(), which is needed for
types like uinptr_t and u_register_t.

Also added L() and LL() for signed values.

Change

Introduce UL(), L() and LL() macros

utils_def.h already has U() and ULL(), but not UL(), which is needed for
types like uinptr_t and u_register_t.

Also added L() and LL() for signed values.

Change-Id: I0654df80d57149ff49507c52f1b27f3d500486a0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6

Marvell support for Armada 8K SoC family

Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor

xlat: More refactoring

RAS: Introduce handler for Uncontainable errors

Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that

RAS: Introduce handler for Uncontainable errors

Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.

This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.

Also fix ras_arch.h header guards.

Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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lib: cpu: Add L2 cache aux control register definition to CA72

Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.

Signed-off-by: Konstantin Porotchkin <kostap@marvell

lib: cpu: Add L2 cache aux control register definition to CA72

Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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