1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_def.h> 9 #include <arm_xlat_tables.h> 10 #include <assert.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <sp805.h> 17 #include <utils.h> 18 #include "../../../bl1/bl1_private.h" 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_platform_setup 24 #pragma weak bl1_plat_sec_mem_layout 25 #pragma weak bl1_plat_prepare_exit 26 27 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 28 bl1_tzram_layout.total_base, \ 29 bl1_tzram_layout.total_size, \ 30 MT_MEMORY | MT_RW | MT_SECURE) 31 /* 32 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 33 * otherwise one region is defined containing both 34 */ 35 #if SEPARATE_CODE_AND_RODATA 36 #define MAP_BL1_RO MAP_REGION_FLAT( \ 37 BL_CODE_BASE, \ 38 BL1_CODE_END - BL_CODE_BASE, \ 39 MT_CODE | MT_SECURE), \ 40 MAP_REGION_FLAT( \ 41 BL1_RO_DATA_BASE, \ 42 BL1_RO_DATA_END \ 43 - BL_RO_DATA_BASE, \ 44 MT_RO_DATA | MT_SECURE) 45 #else 46 #define MAP_BL1_RO MAP_REGION_FLAT( \ 47 BL_CODE_BASE, \ 48 BL1_CODE_END - BL_CODE_BASE, \ 49 MT_CODE | MT_SECURE) 50 #endif 51 52 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 53 static meminfo_t bl1_tzram_layout; 54 55 struct meminfo *bl1_plat_sec_mem_layout(void) 56 { 57 return &bl1_tzram_layout; 58 } 59 60 /******************************************************************************* 61 * BL1 specific platform actions shared between ARM standard platforms. 62 ******************************************************************************/ 63 void arm_bl1_early_platform_setup(void) 64 { 65 66 #if !ARM_DISABLE_TRUSTED_WDOG 67 /* Enable watchdog */ 68 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 69 #endif 70 71 /* Initialize the console to provide early debug support */ 72 arm_console_boot_init(); 73 74 /* Allow BL1 to see the whole Trusted RAM */ 75 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 76 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 77 78 #if !LOAD_IMAGE_V2 79 /* Calculate how much RAM BL1 is using and how much remains free */ 80 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 81 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 82 reserve_mem(&bl1_tzram_layout.free_base, 83 &bl1_tzram_layout.free_size, 84 BL1_RAM_BASE, 85 BL1_RAM_LIMIT - BL1_RAM_BASE); 86 #endif /* LOAD_IMAGE_V2 */ 87 } 88 89 void bl1_early_platform_setup(void) 90 { 91 arm_bl1_early_platform_setup(); 92 93 /* 94 * Initialize Interconnect for this cluster during cold boot. 95 * No need for locks as no other CPU is active. 96 */ 97 plat_arm_interconnect_init(); 98 /* 99 * Enable Interconnect coherency for the primary CPU's cluster. 100 */ 101 plat_arm_interconnect_enter_coherency(); 102 } 103 104 /****************************************************************************** 105 * Perform the very early platform specific architecture setup shared between 106 * ARM standard platforms. This only does basic initialization. Later 107 * architectural setup (bl1_arch_setup()) does not do anything platform 108 * specific. 109 *****************************************************************************/ 110 void arm_bl1_plat_arch_setup(void) 111 { 112 #if USE_COHERENT_MEM 113 /* ARM platforms dont use coherent memory in BL1 */ 114 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 115 #endif 116 117 const mmap_region_t bl_regions[] = { 118 MAP_BL1_TOTAL, 119 MAP_BL1_RO, 120 {0} 121 }; 122 123 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 124 #ifdef AARCH32 125 enable_mmu_secure(0); 126 #else 127 enable_mmu_el3(0); 128 #endif /* AARCH32 */ 129 } 130 131 void bl1_plat_arch_setup(void) 132 { 133 arm_bl1_plat_arch_setup(); 134 } 135 136 /* 137 * Perform the platform specific architecture setup shared between 138 * ARM standard platforms. 139 */ 140 void arm_bl1_platform_setup(void) 141 { 142 /* Initialise the IO layer and register platform IO devices */ 143 plat_arm_io_setup(); 144 #if LOAD_IMAGE_V2 145 arm_load_tb_fw_config(); 146 #endif 147 /* 148 * Allow access to the System counter timer module and program 149 * counter frequency for non secure images during FWU 150 */ 151 arm_configure_sys_timer(); 152 write_cntfrq_el0(plat_get_syscnt_freq2()); 153 } 154 155 void bl1_platform_setup(void) 156 { 157 arm_bl1_platform_setup(); 158 } 159 160 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 161 { 162 #if !ARM_DISABLE_TRUSTED_WDOG 163 /* Disable watchdog before leaving BL1 */ 164 sp805_stop(ARM_SP805_TWDG_BASE); 165 #endif 166 167 #ifdef EL3_PAYLOAD_BASE 168 /* 169 * Program the EL3 payload's entry point address into the CPUs mailbox 170 * in order to release secondary CPUs from their holding pen and make 171 * them jump there. 172 */ 173 plat_arm_program_trusted_mailbox(ep_info->pc); 174 dsbsy(); 175 sev(); 176 #endif 177 } 178 179 /******************************************************************************* 180 * The following function checks if Firmware update is needed, 181 * by checking if TOC in FIP image is valid or not. 182 ******************************************************************************/ 183 unsigned int bl1_plat_get_next_image_id(void) 184 { 185 if (!arm_io_is_toc_valid()) 186 return NS_BL1U_IMAGE_ID; 187 188 return BL2_IMAGE_ID; 189 } 190