1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context_mgmt.h> 12 #include <debug.h> 13 #include <platform.h> 14 #include <pubsub_events.h> 15 #include <stddef.h> 16 #include "psci_private.h" 17 18 /* 19 * Helper functions for the CPU level spinlocks 20 */ 21 static inline void psci_spin_lock_cpu(int idx) 22 { 23 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); 24 } 25 26 static inline void psci_spin_unlock_cpu(int idx) 27 { 28 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); 29 } 30 31 /******************************************************************************* 32 * This function checks whether a cpu which has been requested to be turned on 33 * is OFF to begin with. 34 ******************************************************************************/ 35 static int cpu_on_validate_state(aff_info_state_t aff_state) 36 { 37 if (aff_state == AFF_STATE_ON) 38 return PSCI_E_ALREADY_ON; 39 40 if (aff_state == AFF_STATE_ON_PENDING) 41 return PSCI_E_ON_PENDING; 42 43 assert(aff_state == AFF_STATE_OFF); 44 return PSCI_E_SUCCESS; 45 } 46 47 /******************************************************************************* 48 * Generic handler which is called to physically power on a cpu identified by 49 * its mpidr. It performs the generic, architectural, platform setup and state 50 * management to power on the target cpu e.g. it will ensure that 51 * enough information is stashed for it to resume execution in the non-secure 52 * security state. 53 * 54 * The state of all the relevant power domains are changed after calling the 55 * platform handler as it can return error. 56 ******************************************************************************/ 57 int psci_cpu_on_start(u_register_t target_cpu, 58 entry_point_info_t *ep) 59 { 60 int rc; 61 unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); 62 aff_info_state_t target_aff_state; 63 64 /* Calling function must supply valid input arguments */ 65 assert((int) target_idx >= 0); 66 assert(ep != NULL); 67 68 /* 69 * This function must only be called on platforms where the 70 * CPU_ON platform hooks have been implemented. 71 */ 72 assert(psci_plat_pm_ops->pwr_domain_on && 73 psci_plat_pm_ops->pwr_domain_on_finish); 74 75 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 76 psci_spin_lock_cpu(target_idx); 77 78 /* 79 * Generic management: Ensure that the cpu is off to be 80 * turned on. 81 * Perform cache maintanence ahead of reading the target CPU state to 82 * ensure that the data is not stale. 83 * There is a theoretical edge case where the cache may contain stale 84 * data for the target CPU data - this can occur under the following 85 * conditions: 86 * - the target CPU is in another cluster from the current 87 * - the target CPU was the last CPU to shutdown on its cluster 88 * - the cluster was removed from coherency as part of the CPU shutdown 89 * 90 * In this case the cache maintenace that was performed as part of the 91 * target CPUs shutdown was not seen by the current CPU's cluster. And 92 * so the cache may contain stale data for the target CPU. 93 */ 94 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 95 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 96 if (rc != PSCI_E_SUCCESS) 97 goto exit; 98 99 /* 100 * Call the cpu on handler registered by the Secure Payload Dispatcher 101 * to let it do any bookeeping. If the handler encounters an error, it's 102 * expected to assert within 103 */ 104 if (psci_spd_pm && psci_spd_pm->svc_on) 105 psci_spd_pm->svc_on(target_cpu); 106 107 /* 108 * Set the Affinity info state of the target cpu to ON_PENDING. 109 * Flush aff_info_state as it will be accessed with caches 110 * turned OFF. 111 */ 112 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 113 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 114 115 /* 116 * The cache line invalidation by the target CPU after setting the 117 * state to OFF (see psci_do_cpu_off()), could cause the update to 118 * aff_info_state to be invalidated. Retry the update if the target 119 * CPU aff_info_state is not ON_PENDING. 120 */ 121 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 122 if (target_aff_state != AFF_STATE_ON_PENDING) { 123 assert(target_aff_state == AFF_STATE_OFF); 124 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 125 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 126 127 assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); 128 } 129 130 /* 131 * Perform generic, architecture and platform specific handling. 132 */ 133 /* 134 * Plat. management: Give the platform the current state 135 * of the target cpu to allow it to perform the necessary 136 * steps to power on. 137 */ 138 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 139 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 140 141 if (rc == PSCI_E_SUCCESS) 142 /* Store the re-entry information for the non-secure world. */ 143 cm_init_context_by_index(target_idx, ep); 144 else { 145 /* Restore the state on error. */ 146 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 147 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 148 } 149 150 exit: 151 psci_spin_unlock_cpu(target_idx); 152 return rc; 153 } 154 155 /******************************************************************************* 156 * The following function finish an earlier power on request. They 157 * are called by the common finisher routine in psci_common.c. The `state_info` 158 * is the psci_power_state from which this CPU has woken up from. 159 ******************************************************************************/ 160 void psci_cpu_on_finish(unsigned int cpu_idx, 161 psci_power_state_t *state_info) 162 { 163 /* 164 * Plat. management: Perform the platform specific actions 165 * for this cpu e.g. enabling the gic or zeroing the mailbox 166 * register. The actual state of this cpu has already been 167 * changed. 168 */ 169 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 170 171 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 172 /* 173 * Arch. management: Enable data cache and manage stack memory 174 */ 175 psci_do_pwrup_cache_maintenance(); 176 #endif 177 178 /* 179 * All the platform specific actions for turning this cpu 180 * on have completed. Perform enough arch.initialization 181 * to run in the non-secure address space. 182 */ 183 psci_arch_setup(); 184 185 /* 186 * Lock the CPU spin lock to make sure that the context initialization 187 * is done. Since the lock is only used in this function to create 188 * a synchronization point with cpu_on_start(), it can be released 189 * immediately. 190 */ 191 psci_spin_lock_cpu(cpu_idx); 192 psci_spin_unlock_cpu(cpu_idx); 193 194 /* Ensure we have been explicitly woken up by another cpu */ 195 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 196 197 /* 198 * Call the cpu on finish handler registered by the Secure Payload 199 * Dispatcher to let it do any bookeeping. If the handler encounters an 200 * error, it's expected to assert within 201 */ 202 if (psci_spd_pm && psci_spd_pm->svc_on_finish) 203 psci_spd_pm->svc_on_finish(0); 204 205 PUBLISH_EVENT(psci_cpu_on_finish); 206 207 /* Populate the mpidr field within the cpu node array */ 208 /* This needs to be done only once */ 209 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 210 211 /* 212 * Generic management: Now we just need to retrieve the 213 * information that we had stashed away during the cpu_on 214 * call to set this cpu on its way. 215 */ 216 cm_prepare_el3_exit(NON_SECURE); 217 } 218