1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_arch_svc.h> 10 #include <assert.h> 11 #include <debug.h> 12 #include <platform.h> 13 #include <pmf.h> 14 #include <runtime_instr.h> 15 #include <smccc.h> 16 #include <string.h> 17 #include "psci_private.h" 18 19 /******************************************************************************* 20 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 21 ******************************************************************************/ 22 int psci_cpu_on(u_register_t target_cpu, 23 uintptr_t entrypoint, 24 u_register_t context_id) 25 26 { 27 int rc; 28 entry_point_info_t ep; 29 30 /* Determine if the cpu exists of not */ 31 rc = psci_validate_mpidr(target_cpu); 32 if (rc != PSCI_E_SUCCESS) 33 return PSCI_E_INVALID_PARAMS; 34 35 /* Validate the entry point and get the entry_point_info */ 36 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 37 if (rc != PSCI_E_SUCCESS) 38 return rc; 39 40 /* 41 * To turn this cpu on, specify which power 42 * levels need to be turned on 43 */ 44 return psci_cpu_on_start(target_cpu, &ep); 45 } 46 47 unsigned int psci_version(void) 48 { 49 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 50 } 51 52 int psci_cpu_suspend(unsigned int power_state, 53 uintptr_t entrypoint, 54 u_register_t context_id) 55 { 56 int rc; 57 unsigned int target_pwrlvl, is_power_down_state; 58 entry_point_info_t ep; 59 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 60 plat_local_state_t cpu_pd_state; 61 62 /* Validate the power_state parameter */ 63 rc = psci_validate_power_state(power_state, &state_info); 64 if (rc != PSCI_E_SUCCESS) { 65 assert(rc == PSCI_E_INVALID_PARAMS); 66 return rc; 67 } 68 69 /* 70 * Get the value of the state type bit from the power state parameter. 71 */ 72 is_power_down_state = psci_get_pstate_type(power_state); 73 74 /* Sanity check the requested suspend levels */ 75 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 76 == PSCI_E_SUCCESS); 77 78 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 79 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 80 ERROR("Invalid target power level for suspend operation\n"); 81 panic(); 82 } 83 84 /* Fast path for CPU standby.*/ 85 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 86 if (psci_plat_pm_ops->cpu_standby == NULL) 87 return PSCI_E_INVALID_PARAMS; 88 89 /* 90 * Set the state of the CPU power domain to the platform 91 * specific retention state and enter the standby state. 92 */ 93 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 94 psci_set_cpu_local_state(cpu_pd_state); 95 96 #if ENABLE_PSCI_STAT 97 plat_psci_stat_accounting_start(&state_info); 98 #endif 99 100 #if ENABLE_RUNTIME_INSTRUMENTATION 101 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 102 RT_INSTR_ENTER_HW_LOW_PWR, 103 PMF_NO_CACHE_MAINT); 104 #endif 105 106 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 107 108 /* Upon exit from standby, set the state back to RUN. */ 109 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 110 111 #if ENABLE_RUNTIME_INSTRUMENTATION 112 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 113 RT_INSTR_EXIT_HW_LOW_PWR, 114 PMF_NO_CACHE_MAINT); 115 #endif 116 117 #if ENABLE_PSCI_STAT 118 plat_psci_stat_accounting_stop(&state_info); 119 120 /* Update PSCI stats */ 121 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 122 #endif 123 124 return PSCI_E_SUCCESS; 125 } 126 127 /* 128 * If a power down state has been requested, we need to verify entry 129 * point and program entry information. 130 */ 131 if (is_power_down_state != 0U) { 132 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 133 if (rc != PSCI_E_SUCCESS) 134 return rc; 135 } 136 137 /* 138 * Do what is needed to enter the power down state. Upon success, 139 * enter the final wfi which will power down this CPU. This function 140 * might return if the power down was abandoned for any reason, e.g. 141 * arrival of an interrupt 142 */ 143 psci_cpu_suspend_start(&ep, 144 target_pwrlvl, 145 &state_info, 146 is_power_down_state); 147 148 return PSCI_E_SUCCESS; 149 } 150 151 152 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 153 { 154 int rc; 155 psci_power_state_t state_info; 156 entry_point_info_t ep; 157 158 /* Check if the current CPU is the last ON CPU in the system */ 159 if (psci_is_last_on_cpu() == 0U) 160 return PSCI_E_DENIED; 161 162 /* Validate the entry point and get the entry_point_info */ 163 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 164 if (rc != PSCI_E_SUCCESS) 165 return rc; 166 167 /* Query the psci_power_state for system suspend */ 168 psci_query_sys_suspend_pwrstate(&state_info); 169 170 /* Ensure that the psci_power_state makes sense */ 171 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 172 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 173 == PSCI_E_SUCCESS); 174 assert(is_local_state_off( 175 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); 176 177 /* 178 * Do what is needed to enter the system suspend state. This function 179 * might return if the power down was abandoned for any reason, e.g. 180 * arrival of an interrupt 181 */ 182 psci_cpu_suspend_start(&ep, 183 PLAT_MAX_PWR_LVL, 184 &state_info, 185 PSTATE_TYPE_POWERDOWN); 186 187 return PSCI_E_SUCCESS; 188 } 189 190 int psci_cpu_off(void) 191 { 192 int rc; 193 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 194 195 /* 196 * Do what is needed to power off this CPU and possible higher power 197 * levels if it able to do so. Upon success, enter the final wfi 198 * which will power down this CPU. 199 */ 200 rc = psci_do_cpu_off(target_pwrlvl); 201 202 /* 203 * The only error cpu_off can return is E_DENIED. So check if that's 204 * indeed the case. 205 */ 206 assert(rc == PSCI_E_DENIED); 207 208 return rc; 209 } 210 211 int psci_affinity_info(u_register_t target_affinity, 212 unsigned int lowest_affinity_level) 213 { 214 int target_idx; 215 216 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 217 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 218 return PSCI_E_INVALID_PARAMS; 219 220 /* Calculate the cpu index of the target */ 221 target_idx = plat_core_pos_by_mpidr(target_affinity); 222 if (target_idx == -1) 223 return PSCI_E_INVALID_PARAMS; 224 225 /* 226 * Generic management: 227 * Perform cache maintanence ahead of reading the target CPU state to 228 * ensure that the data is not stale. 229 * There is a theoretical edge case where the cache may contain stale 230 * data for the target CPU data - this can occur under the following 231 * conditions: 232 * - the target CPU is in another cluster from the current 233 * - the target CPU was the last CPU to shutdown on its cluster 234 * - the cluster was removed from coherency as part of the CPU shutdown 235 * 236 * In this case the cache maintenace that was performed as part of the 237 * target CPUs shutdown was not seen by the current CPU's cluster. And 238 * so the cache may contain stale data for the target CPU. 239 */ 240 flush_cpu_data_by_index((unsigned int)target_idx, 241 psci_svc_cpu_data.aff_info_state); 242 243 return psci_get_aff_info_state_by_idx(target_idx); 244 } 245 246 int psci_migrate(u_register_t target_cpu) 247 { 248 int rc; 249 u_register_t resident_cpu_mpidr; 250 251 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 252 if (rc != PSCI_TOS_UP_MIG_CAP) 253 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 254 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 255 256 /* 257 * Migrate should only be invoked on the CPU where 258 * the Secure OS is resident. 259 */ 260 if (resident_cpu_mpidr != read_mpidr_el1()) 261 return PSCI_E_NOT_PRESENT; 262 263 /* Check the validity of the specified target cpu */ 264 rc = psci_validate_mpidr(target_cpu); 265 if (rc != PSCI_E_SUCCESS) 266 return PSCI_E_INVALID_PARAMS; 267 268 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); 269 270 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 271 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 272 273 return rc; 274 } 275 276 int psci_migrate_info_type(void) 277 { 278 u_register_t resident_cpu_mpidr; 279 280 return psci_spd_migrate_info(&resident_cpu_mpidr); 281 } 282 283 u_register_t psci_migrate_info_up_cpu(void) 284 { 285 u_register_t resident_cpu_mpidr; 286 int rc; 287 288 /* 289 * Return value of this depends upon what 290 * psci_spd_migrate_info() returns. 291 */ 292 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 293 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP)) 294 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS; 295 296 return resident_cpu_mpidr; 297 } 298 299 int psci_node_hw_state(u_register_t target_cpu, 300 unsigned int power_level) 301 { 302 int rc; 303 304 /* Validate target_cpu */ 305 rc = psci_validate_mpidr(target_cpu); 306 if (rc != PSCI_E_SUCCESS) 307 return PSCI_E_INVALID_PARAMS; 308 309 /* Validate power_level against PLAT_MAX_PWR_LVL */ 310 if (power_level > PLAT_MAX_PWR_LVL) 311 return PSCI_E_INVALID_PARAMS; 312 313 /* 314 * Dispatch this call to platform to query power controller, and pass on 315 * to the caller what it returns 316 */ 317 assert(psci_plat_pm_ops->get_node_hw_state != NULL); 318 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 319 assert(((rc >= HW_ON) && (rc <= HW_STANDBY)) 320 || (rc == PSCI_E_NOT_SUPPORTED) 321 || (rc == PSCI_E_INVALID_PARAMS)); 322 return rc; 323 } 324 325 int psci_features(unsigned int psci_fid) 326 { 327 unsigned int local_caps = psci_caps; 328 329 if (psci_fid == SMCCC_VERSION) 330 return PSCI_E_SUCCESS; 331 332 /* Check if it is a 64 bit function */ 333 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 334 local_caps &= PSCI_CAP_64BIT_MASK; 335 336 /* Check for invalid fid */ 337 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 338 && is_psci_fid(psci_fid))) 339 return PSCI_E_NOT_SUPPORTED; 340 341 342 /* Check if the psci fid is supported or not */ 343 if ((local_caps & define_psci_cap(psci_fid)) == 0U) 344 return PSCI_E_NOT_SUPPORTED; 345 346 /* Format the feature flags */ 347 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) || 348 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) { 349 /* 350 * The trusted firmware does not support OS Initiated Mode. 351 */ 352 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) | 353 (((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U) 354 << FF_MODE_SUPPORT_SHIFT)); 355 return (int) ret; 356 } 357 358 /* Return 0 for all other fid's */ 359 return PSCI_E_SUCCESS; 360 } 361 362 /******************************************************************************* 363 * PSCI top level handler for servicing SMCs. 364 ******************************************************************************/ 365 u_register_t psci_smc_handler(uint32_t smc_fid, 366 u_register_t x1, 367 u_register_t x2, 368 u_register_t x3, 369 u_register_t x4, 370 void *cookie, 371 void *handle, 372 u_register_t flags) 373 { 374 u_register_t ret; 375 376 if (is_caller_secure(flags)) 377 return (u_register_t)SMC_UNK; 378 379 /* Check the fid against the capabilities */ 380 if ((psci_caps & define_psci_cap(smc_fid)) == 0U) 381 return (u_register_t)SMC_UNK; 382 383 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 384 /* 32-bit PSCI function, clear top parameter bits */ 385 386 uint32_t r1 = (uint32_t)x1; 387 uint32_t r2 = (uint32_t)x2; 388 uint32_t r3 = (uint32_t)x3; 389 390 switch (smc_fid) { 391 case PSCI_VERSION: 392 ret = (u_register_t)psci_version(); 393 break; 394 395 case PSCI_CPU_OFF: 396 ret = (u_register_t)psci_cpu_off(); 397 break; 398 399 case PSCI_CPU_SUSPEND_AARCH32: 400 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3); 401 break; 402 403 case PSCI_CPU_ON_AARCH32: 404 ret = (u_register_t)psci_cpu_on(r1, r2, r3); 405 break; 406 407 case PSCI_AFFINITY_INFO_AARCH32: 408 ret = (u_register_t)psci_affinity_info(r1, r2); 409 break; 410 411 case PSCI_MIG_AARCH32: 412 ret = (u_register_t)psci_migrate(r1); 413 break; 414 415 case PSCI_MIG_INFO_TYPE: 416 ret = (u_register_t)psci_migrate_info_type(); 417 break; 418 419 case PSCI_MIG_INFO_UP_CPU_AARCH32: 420 ret = psci_migrate_info_up_cpu(); 421 break; 422 423 case PSCI_NODE_HW_STATE_AARCH32: 424 ret = (u_register_t)psci_node_hw_state(r1, r2); 425 break; 426 427 case PSCI_SYSTEM_SUSPEND_AARCH32: 428 ret = (u_register_t)psci_system_suspend(r1, r2); 429 break; 430 431 case PSCI_SYSTEM_OFF: 432 psci_system_off(); 433 /* We should never return from psci_system_off() */ 434 break; 435 436 case PSCI_SYSTEM_RESET: 437 psci_system_reset(); 438 /* We should never return from psci_system_reset() */ 439 break; 440 441 case PSCI_FEATURES: 442 ret = (u_register_t)psci_features(r1); 443 break; 444 445 #if ENABLE_PSCI_STAT 446 case PSCI_STAT_RESIDENCY_AARCH32: 447 ret = psci_stat_residency(r1, r2); 448 break; 449 450 case PSCI_STAT_COUNT_AARCH32: 451 ret = psci_stat_count(r1, r2); 452 break; 453 #endif 454 case PSCI_MEM_PROTECT: 455 ret = psci_mem_protect(r1); 456 break; 457 458 case PSCI_MEM_CHK_RANGE_AARCH32: 459 ret = psci_mem_chk_range(r1, r2); 460 break; 461 462 case PSCI_SYSTEM_RESET2_AARCH32: 463 /* We should never return from psci_system_reset2() */ 464 ret = psci_system_reset2(r1, r2); 465 break; 466 467 default: 468 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 469 ret = (u_register_t)SMC_UNK; 470 break; 471 } 472 } else { 473 /* 64-bit PSCI function */ 474 475 switch (smc_fid) { 476 case PSCI_CPU_SUSPEND_AARCH64: 477 ret = (u_register_t) 478 psci_cpu_suspend((unsigned int)x1, x2, x3); 479 break; 480 481 case PSCI_CPU_ON_AARCH64: 482 ret = (u_register_t)psci_cpu_on(x1, x2, x3); 483 break; 484 485 case PSCI_AFFINITY_INFO_AARCH64: 486 ret = (u_register_t) 487 psci_affinity_info(x1, (unsigned int)x2); 488 break; 489 490 case PSCI_MIG_AARCH64: 491 ret = (u_register_t)psci_migrate(x1); 492 break; 493 494 case PSCI_MIG_INFO_UP_CPU_AARCH64: 495 ret = psci_migrate_info_up_cpu(); 496 break; 497 498 case PSCI_NODE_HW_STATE_AARCH64: 499 ret = (u_register_t)psci_node_hw_state( 500 x1, (unsigned int) x2); 501 break; 502 503 case PSCI_SYSTEM_SUSPEND_AARCH64: 504 ret = (u_register_t)psci_system_suspend(x1, x2); 505 break; 506 507 #if ENABLE_PSCI_STAT 508 case PSCI_STAT_RESIDENCY_AARCH64: 509 ret = psci_stat_residency(x1, (unsigned int) x2); 510 break; 511 512 case PSCI_STAT_COUNT_AARCH64: 513 ret = psci_stat_count(x1, (unsigned int) x2); 514 break; 515 #endif 516 517 case PSCI_MEM_CHK_RANGE_AARCH64: 518 ret = psci_mem_chk_range(x1, x2); 519 break; 520 521 case PSCI_SYSTEM_RESET2_AARCH64: 522 /* We should never return from psci_system_reset2() */ 523 ret = psci_system_reset2((uint32_t) x1, x2); 524 break; 525 526 default: 527 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid); 528 ret = (u_register_t)SMC_UNK; 529 break; 530 } 531 } 532 533 return ret; 534 } 535