1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <arch.h> 11 #include <bakery_lock.h> 12 #include <bl_common.h> 13 #include <cpu_data.h> 14 #include <psci.h> 15 #include <spinlock.h> 16 17 #if HW_ASSISTED_COHERENCY 18 19 /* 20 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 21 * as PSCI participants are cache-coherent, and there's no need for explicit 22 * cache maintenance operations or barriers to coordinate their state. 23 */ 24 #define psci_flush_dcache_range(addr, size) 25 #define psci_flush_cpu_data(member) 26 #define psci_inv_cpu_data(member) 27 28 #define psci_dsbish() 29 30 /* 31 * On systems where participant CPUs are cache-coherent, we can use spinlocks 32 * instead of bakery locks. 33 */ 34 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 35 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 36 37 #define psci_lock_get(non_cpu_pd_node) \ 38 spin_lock(&psci_locks[(non_cpu_pd_node)->lock_index]) 39 #define psci_lock_release(non_cpu_pd_node) \ 40 spin_unlock(&psci_locks[(non_cpu_pd_node)->lock_index]) 41 42 #else 43 44 /* 45 * If not all PSCI participants are cache-coherent, perform cache maintenance 46 * and issue barriers wherever required to coordinate state. 47 */ 48 #define psci_flush_dcache_range(addr, size) flush_dcache_range(addr, size) 49 #define psci_flush_cpu_data(member) flush_cpu_data(member) 50 #define psci_inv_cpu_data(member) inv_cpu_data(member) 51 52 #define psci_dsbish() dsbish() 53 54 /* 55 * Use bakery locks for state coordination as not all PSCI participants are 56 * cache coherent. 57 */ 58 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 59 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 60 61 #define psci_lock_get(non_cpu_pd_node) \ 62 bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index]) 63 #define psci_lock_release(non_cpu_pd_node) \ 64 bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index]) 65 66 #endif 67 68 #define psci_lock_init(_non_cpu_pd_node, _idx) \ 69 ((_non_cpu_pd_node)[(_idx)].lock_index = (_idx)) 70 71 /* 72 * The PSCI capability which are provided by the generic code but does not 73 * depend on the platform or spd capabilities. 74 */ 75 #define PSCI_GENERIC_CAP \ 76 (define_psci_cap(PSCI_VERSION) | \ 77 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 78 define_psci_cap(PSCI_FEATURES)) 79 80 /* 81 * The PSCI capabilities mask for 64 bit functions. 82 */ 83 #define PSCI_CAP_64BIT_MASK \ 84 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 85 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 86 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 87 define_psci_cap(PSCI_MIG_AARCH64) | \ 88 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 89 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 90 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 91 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 92 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 93 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 94 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 95 96 /* 97 * Helper functions to get/set the fields of PSCI per-cpu data. 98 */ 99 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 100 { 101 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 102 } 103 104 static inline aff_info_state_t psci_get_aff_info_state(void) 105 { 106 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 107 } 108 109 static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx) 110 { 111 return get_cpu_data_by_index((unsigned int)idx, 112 psci_svc_cpu_data.aff_info_state); 113 } 114 115 static inline void psci_set_aff_info_state_by_idx(int idx, 116 aff_info_state_t aff_state) 117 { 118 set_cpu_data_by_index((unsigned int)idx, 119 psci_svc_cpu_data.aff_info_state, aff_state); 120 } 121 122 static inline unsigned int psci_get_suspend_pwrlvl(void) 123 { 124 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 125 } 126 127 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 128 { 129 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 130 } 131 132 static inline void psci_set_cpu_local_state(plat_local_state_t state) 133 { 134 set_cpu_data(psci_svc_cpu_data.local_state, state); 135 } 136 137 static inline plat_local_state_t psci_get_cpu_local_state(void) 138 { 139 return get_cpu_data(psci_svc_cpu_data.local_state); 140 } 141 142 static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx) 143 { 144 return get_cpu_data_by_index((unsigned int)idx, 145 psci_svc_cpu_data.local_state); 146 } 147 148 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 149 static inline int is_cpu_standby_req(unsigned int is_power_down_state, 150 unsigned int retn_lvl) 151 { 152 return ((is_power_down_state == 0U) && (retn_lvl == 0U)) ? 1 : 0; 153 } 154 155 /******************************************************************************* 156 * The following two data structures implement the power domain tree. The tree 157 * is used to track the state of all the nodes i.e. power domain instances 158 * described by the platform. The tree consists of nodes that describe CPU power 159 * domains i.e. leaf nodes and all other power domains which are parents of a 160 * CPU power domain i.e. non-leaf nodes. 161 ******************************************************************************/ 162 typedef struct non_cpu_pwr_domain_node { 163 /* 164 * Index of the first CPU power domain node level 0 which has this node 165 * as its parent. 166 */ 167 unsigned int cpu_start_idx; 168 169 /* 170 * Number of CPU power domains which are siblings of the domain indexed 171 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 172 * -> cpu_start_idx + ncpus' have this node as their parent. 173 */ 174 unsigned int ncpus; 175 176 /* 177 * Index of the parent power domain node. 178 * TODO: Figure out whether to whether using pointer is more efficient. 179 */ 180 unsigned int parent_node; 181 182 plat_local_state_t local_state; 183 184 unsigned char level; 185 186 /* For indexing the psci_lock array*/ 187 unsigned char lock_index; 188 } non_cpu_pd_node_t; 189 190 typedef struct cpu_pwr_domain_node { 191 u_register_t mpidr; 192 193 /* 194 * Index of the parent power domain node. 195 * TODO: Figure out whether to whether using pointer is more efficient. 196 */ 197 unsigned int parent_node; 198 199 /* 200 * A CPU power domain does not require state coordination like its 201 * parent power domains. Hence this node does not include a bakery 202 * lock. A spinlock is required by the CPU_ON handler to prevent a race 203 * when multiple CPUs try to turn ON the same target CPU. 204 */ 205 spinlock_t cpu_lock; 206 } cpu_pd_node_t; 207 208 /******************************************************************************* 209 * Data prototypes 210 ******************************************************************************/ 211 extern const plat_psci_ops_t *psci_plat_pm_ops; 212 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 213 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 214 extern unsigned int psci_caps; 215 216 /* One lock is required per non-CPU power domain node */ 217 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 218 219 /******************************************************************************* 220 * SPD's power management hooks registered with PSCI 221 ******************************************************************************/ 222 extern const spd_pm_ops_t *psci_spd_pm; 223 224 /******************************************************************************* 225 * Function prototypes 226 ******************************************************************************/ 227 /* Private exported functions from psci_common.c */ 228 int psci_validate_power_state(unsigned int power_state, 229 psci_power_state_t *state_info); 230 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 231 int psci_validate_mpidr(u_register_t mpidr); 232 void psci_init_req_local_pwr_states(void); 233 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 234 psci_power_state_t *target_state); 235 int psci_validate_entry_point(entry_point_info_t *ep, 236 uintptr_t entrypoint, u_register_t context_id); 237 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 238 unsigned int end_lvl, 239 unsigned int node_index[]); 240 void psci_do_state_coordination(unsigned int end_pwrlvl, 241 psci_power_state_t *state_info); 242 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 243 unsigned int cpu_idx); 244 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 245 unsigned int cpu_idx); 246 int psci_validate_suspend_req(const psci_power_state_t *state_info, 247 unsigned int is_power_down_state); 248 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 249 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 250 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 251 void psci_print_power_domain_map(void); 252 unsigned int psci_is_last_on_cpu(void); 253 int psci_spd_migrate_info(u_register_t *mpidr); 254 void psci_do_pwrdown_sequence(unsigned int power_level); 255 256 /* 257 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 258 * available. Otherwise, this needs post-call stack maintenance, which is 259 * handled in assembly. 260 */ 261 void prepare_cpu_pwr_dwn(unsigned int power_level); 262 263 /* Private exported functions from psci_on.c */ 264 int psci_cpu_on_start(u_register_t target_cpu, 265 entry_point_info_t *ep); 266 267 void psci_cpu_on_finish(unsigned int cpu_idx, 268 psci_power_state_t *state_info); 269 270 /* Private exported functions from psci_off.c */ 271 int psci_do_cpu_off(unsigned int end_pwrlvl); 272 273 /* Private exported functions from psci_suspend.c */ 274 void psci_cpu_suspend_start(entry_point_info_t *ep, 275 unsigned int end_pwrlvl, 276 psci_power_state_t *state_info, 277 unsigned int is_power_down_state); 278 279 void psci_cpu_suspend_finish(unsigned int cpu_idx, 280 psci_power_state_t *state_info); 281 282 /* Private exported functions from psci_helpers.S */ 283 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 284 void psci_do_pwrup_cache_maintenance(void); 285 286 /* Private exported functions from psci_system_off.c */ 287 void __dead2 psci_system_off(void); 288 void __dead2 psci_system_reset(void); 289 int psci_system_reset2(uint32_t reset_type, u_register_t cookie); 290 291 /* Private exported functions from psci_stat.c */ 292 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 293 const psci_power_state_t *state_info); 294 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 295 const psci_power_state_t *state_info); 296 u_register_t psci_stat_residency(u_register_t target_cpu, 297 unsigned int power_state); 298 u_register_t psci_stat_count(u_register_t target_cpu, 299 unsigned int power_state); 300 301 /* Private exported functions from psci_mem_protect.c */ 302 int psci_mem_protect(unsigned int enable); 303 int psci_mem_chk_range(uintptr_t base, u_register_t length); 304 305 #endif /* PSCI_PRIVATE_H */ 306