1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arm_def.h> 7 #include <assert.h> 8 #include <generic_delay_timer.h> 9 #include <plat_arm.h> 10 #include <platform.h> 11 12 #pragma weak bl2_el3_early_platform_setup 13 #pragma weak bl2_el3_plat_arch_setup 14 #pragma weak bl2_el3_plat_prepare_exit 15 16 #define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \ 17 bl2_el3_tzram_layout.total_base, \ 18 bl2_el3_tzram_layout.total_size, \ 19 MT_MEMORY | MT_RW | MT_SECURE) 20 21 static meminfo_t bl2_el3_tzram_layout; 22 23 /* 24 * Perform arm specific early platform setup. At this moment we only initialize 25 * the console and the memory layout. 26 */ 27 void arm_bl2_el3_early_platform_setup(void) 28 { 29 /* Initialize the console to provide early debug support */ 30 arm_console_boot_init(); 31 32 /* 33 * Allow BL2 to see the whole Trusted RAM. This is determined 34 * statically since we cannot rely on BL1 passing this information 35 * in the BL2_AT_EL3 case. 36 */ 37 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; 38 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE; 39 40 /* Initialise the IO layer and register platform IO devices */ 41 plat_arm_io_setup(); 42 } 43 44 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 45 u_register_t arg1 __unused, 46 u_register_t arg2 __unused, 47 u_register_t arg3 __unused) 48 { 49 arm_bl2_el3_early_platform_setup(); 50 51 /* 52 * Initialize Interconnect for this cluster during cold boot. 53 * No need for locks as no other CPU is active. 54 */ 55 plat_arm_interconnect_init(); 56 /* 57 * Enable Interconnect coherency for the primary CPU's cluster. 58 */ 59 plat_arm_interconnect_enter_coherency(); 60 61 generic_delay_timer_init(); 62 } 63 64 /******************************************************************************* 65 * Perform the very early platform specific architectural setup here. At the 66 * moment this is only initializes the mmu in a quick and dirty way. 67 ******************************************************************************/ 68 void arm_bl2_el3_plat_arch_setup(void) 69 { 70 71 #if USE_COHERENT_MEM 72 /* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */ 73 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U); 74 #endif 75 76 const mmap_region_t bl_regions[] = { 77 MAP_BL2_EL3_TOTAL, 78 ARM_MAP_BL_RO, 79 {0} 80 }; 81 82 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 83 84 #ifdef AARCH32 85 enable_mmu_secure(0); 86 #else 87 enable_mmu_el3(0); 88 #endif 89 } 90 91 void bl2_el3_plat_arch_setup(void) 92 { 93 arm_bl2_el3_plat_arch_setup(); 94 } 95 96 void bl2_el3_plat_prepare_exit(void) 97 { 98 } 99