| cb4ec47b | 05-Aug-2021 |
johpow01 <john.powell@arm.com> |
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
show more ...
|
| 95fe195d | 16-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.
S
errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
show more ...
|
| b3210f4d | 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
show more ...
|
| b84a8508 | 15-Apr-2019 |
Etienne Carriere <etienne.carriere@st.com> |
feat(lib/optee): introduce optee_header_is_valid()
This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_I
feat(lib/optee): introduce optee_header_is_valid()
This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_IMAGE_ID) or from a single OP-TEE binary image.
The function tee_validate_header() is reworked to return a boolean,
and is now silent.
Change-Id: Idc7dde091f2ada8898f40d02e68c3834ca39d8e8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
|
| 7cfae932 | 30-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Neoverse N2 erratum 2189731
Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 whi
errata: workaround for Neoverse N2 erratum 2189731
Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03
show more ...
|
| afc2ed63 | 31-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1
errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
show more ...
|
| 213afde9 | 31-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Cortex-A710 erratum 2055002
Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] t
errata: workaround for Cortex-A710 erratum 2055002
Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81
show more ...
|
| 4618b2bf | 31-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which
errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
show more ...
|
| 65e04f27 | 30-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force
errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21
show more ...
|
| d0464435 | 26-Aug-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration |
| 8fcd3d96 | 08-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| d4582d30 | 29-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when N
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 813524ea | 02-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when N
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 6657c1e3 | 25-Aug-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "cpu: add support for Demeter CPU" into integration |
| b4f8d445 | 19-Aug-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(el3_runtime): correct CASSERT for pauth
clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:
include/lib/el3_runtime/cpu_data.h:135:
fix(el3_runtime): correct CASSERT for pauth
clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:
include/lib/el3_runtime/cpu_data.h:135:2: error: redefinition of typedef
'assert_cpu_data_crash_stack_offset_mismatch' is a C11 feature [-Werror,
-Wtypedef-redefinition]
assert_cpu_data_crash_stack_offset_mismatch);
^
include/lib/el3_runtime/cpu_data.h:128:2: note: previous definition is here
assert_cpu_data_crash_stack_offset_mismatch);
^
1 error generated.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I22c8c45a94a64620007979d55412dbb57b11b813
show more ...
|
| 47d6f5ff | 27-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| f4616efa | 07-Jul-2021 |
johpow01 <john.powell@arm.com> |
cpu: add support for Demeter CPU
This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patc
cpu: add support for Demeter CPU
This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f
show more ...
|
| 741dd04c | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found he
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
show more ...
|
| 143b1965 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
show more ...
|
| 4789cf66 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
show more ...
|
| 68ac5ed0 | 08-Jul-2021 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon e
fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
show more ...
|
| 586aafa3 | 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1791573" into integration |
| 33e3e925 | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
show more ...
|
| 52698a62 | 09-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(mpam): remove unused function declaration
Change-Id: Ia660b6554fe4544effd1810e1aca202f95e3c447
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| 81a8b2da | 30-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): enable SVE for the secure world" into integration |