1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 #if SPM_MM 23 #include <services/spm_mm_partition.h> 24 #endif 25 26 #include "fvp_private.h" 27 28 /* Defines for GIC Driver build time selection */ 29 #define FVP_GICV2 1 30 #define FVP_GICV3 2 31 32 /******************************************************************************* 33 * arm_config holds the characteristics of the differences between the three FVP 34 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 35 * at each boot stage by the primary before enabling the MMU (to allow 36 * interconnect configuration) & used thereafter. Each BL will have its own copy 37 * to allow independent operation. 38 ******************************************************************************/ 39 arm_config_t arm_config; 40 41 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 42 DEVICE0_SIZE, \ 43 MT_DEVICE | MT_RW | MT_SECURE) 44 45 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 46 DEVICE1_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 /* 50 * Need to be mapped with write permissions in order to set a new non-volatile 51 * counter value. 52 */ 53 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 54 DEVICE2_SIZE, \ 55 MT_DEVICE | MT_RW | MT_SECURE) 56 57 /* 58 * Table of memory regions for various BL stages to map using the MMU. 59 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 60 * of mapping it. 61 * 62 * The flash needs to be mapped as writable in order to erase the FIP's Table of 63 * Contents in case of unrecoverable error (see plat_error_handler()). 64 */ 65 #ifdef IMAGE_BL1 66 const mmap_region_t plat_arm_mmap[] = { 67 ARM_MAP_SHARED_RAM, 68 V2M_MAP_FLASH0_RW, 69 V2M_MAP_IOFPGA, 70 MAP_DEVICE0, 71 MAP_DEVICE1, 72 #if TRUSTED_BOARD_BOOT 73 /* To access the Root of Trust Public Key registers. */ 74 MAP_DEVICE2, 75 /* Map DRAM to authenticate NS_BL2U image. */ 76 ARM_MAP_NS_DRAM1, 77 #endif 78 {0} 79 }; 80 #endif 81 #ifdef IMAGE_BL2 82 const mmap_region_t plat_arm_mmap[] = { 83 ARM_MAP_SHARED_RAM, 84 V2M_MAP_FLASH0_RW, 85 V2M_MAP_IOFPGA, 86 MAP_DEVICE0, 87 MAP_DEVICE1, 88 ARM_MAP_NS_DRAM1, 89 #ifdef __aarch64__ 90 ARM_MAP_DRAM2, 91 #endif 92 #if defined(SPD_spmd) 93 ARM_MAP_TRUSTED_DRAM, 94 #endif 95 #ifdef SPD_tspd 96 ARM_MAP_TSP_SEC_MEM, 97 #endif 98 #if TRUSTED_BOARD_BOOT 99 /* To access the Root of Trust Public Key registers. */ 100 MAP_DEVICE2, 101 #if !BL2_AT_EL3 102 ARM_MAP_BL1_RW, 103 #endif 104 #endif /* TRUSTED_BOARD_BOOT */ 105 #if SPM_MM 106 ARM_SP_IMAGE_MMAP, 107 #endif 108 #if ARM_BL31_IN_DRAM 109 ARM_MAP_BL31_SEC_DRAM, 110 #endif 111 #ifdef SPD_opteed 112 ARM_MAP_OPTEE_CORE_MEM, 113 ARM_OPTEE_PAGEABLE_LOAD_MEM, 114 #endif 115 {0} 116 }; 117 #endif 118 #ifdef IMAGE_BL2U 119 const mmap_region_t plat_arm_mmap[] = { 120 MAP_DEVICE0, 121 V2M_MAP_IOFPGA, 122 {0} 123 }; 124 #endif 125 #ifdef IMAGE_BL31 126 const mmap_region_t plat_arm_mmap[] = { 127 ARM_MAP_SHARED_RAM, 128 #if USE_DEBUGFS 129 /* Required by devfip, can be removed if devfip is not used */ 130 V2M_MAP_FLASH0_RW, 131 #endif /* USE_DEBUGFS */ 132 ARM_MAP_EL3_TZC_DRAM, 133 V2M_MAP_IOFPGA, 134 MAP_DEVICE0, 135 MAP_DEVICE1, 136 ARM_V2M_MAP_MEM_PROTECT, 137 #if SPM_MM 138 ARM_SPM_BUF_EL3_MMAP, 139 #endif 140 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 141 ARM_DTB_DRAM_NS, 142 {0} 143 }; 144 145 #if defined(IMAGE_BL31) && SPM_MM 146 const mmap_region_t plat_arm_secure_partition_mmap[] = { 147 V2M_MAP_IOFPGA_EL0, /* for the UART */ 148 MAP_REGION_FLAT(DEVICE0_BASE, \ 149 DEVICE0_SIZE, \ 150 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 151 ARM_SP_IMAGE_MMAP, 152 ARM_SP_IMAGE_NS_BUF_MMAP, 153 ARM_SP_IMAGE_RW_MMAP, 154 ARM_SPM_BUF_EL0_MMAP, 155 {0} 156 }; 157 #endif 158 #endif 159 #ifdef IMAGE_BL32 160 const mmap_region_t plat_arm_mmap[] = { 161 #ifndef __aarch64__ 162 ARM_MAP_SHARED_RAM, 163 ARM_V2M_MAP_MEM_PROTECT, 164 #endif 165 V2M_MAP_IOFPGA, 166 MAP_DEVICE0, 167 MAP_DEVICE1, 168 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 169 ARM_DTB_DRAM_NS, 170 {0} 171 }; 172 #endif 173 174 ARM_CASSERT_MMAP 175 176 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 177 static const int fvp_cci400_map[] = { 178 PLAT_FVP_CCI400_CLUS0_SL_PORT, 179 PLAT_FVP_CCI400_CLUS1_SL_PORT, 180 }; 181 182 static const int fvp_cci5xx_map[] = { 183 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 184 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 185 }; 186 187 static unsigned int get_interconnect_master(void) 188 { 189 unsigned int master; 190 u_register_t mpidr; 191 192 mpidr = read_mpidr_el1(); 193 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 194 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 195 196 assert(master < FVP_CLUSTER_COUNT); 197 return master; 198 } 199 #endif 200 201 #if defined(IMAGE_BL31) && SPM_MM 202 /* 203 * Boot information passed to a secure partition during initialisation. Linear 204 * indices in MP information will be filled at runtime. 205 */ 206 static spm_mm_mp_info_t sp_mp_info[] = { 207 [0] = {0x80000000, 0}, 208 [1] = {0x80000001, 0}, 209 [2] = {0x80000002, 0}, 210 [3] = {0x80000003, 0}, 211 [4] = {0x80000100, 0}, 212 [5] = {0x80000101, 0}, 213 [6] = {0x80000102, 0}, 214 [7] = {0x80000103, 0}, 215 }; 216 217 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 218 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 219 .h.version = VERSION_1, 220 .h.size = sizeof(spm_mm_boot_info_t), 221 .h.attr = 0, 222 .sp_mem_base = ARM_SP_IMAGE_BASE, 223 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 224 .sp_image_base = ARM_SP_IMAGE_BASE, 225 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 226 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 227 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 228 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 229 .sp_image_size = ARM_SP_IMAGE_SIZE, 230 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 231 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 232 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 233 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 234 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 235 .num_cpus = PLATFORM_CORE_COUNT, 236 .mp_info = &sp_mp_info[0], 237 }; 238 239 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 240 { 241 return plat_arm_secure_partition_mmap; 242 } 243 244 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 245 void *cookie) 246 { 247 return &plat_arm_secure_partition_boot_info; 248 } 249 #endif 250 251 /******************************************************************************* 252 * A single boot loader stack is expected to work on both the Foundation FVP 253 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 254 * SYS_ID register provides a mechanism for detecting the differences between 255 * these platforms. This information is stored in a per-BL array to allow the 256 * code to take the correct path.Per BL platform configuration. 257 ******************************************************************************/ 258 void __init fvp_config_setup(void) 259 { 260 unsigned int rev, hbi, bld, arch, sys_id; 261 262 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 263 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 264 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 265 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 266 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 267 268 if (arch != ARCH_MODEL) { 269 ERROR("This firmware is for FVP models\n"); 270 panic(); 271 } 272 273 /* 274 * The build field in the SYS_ID tells which variant of the GIC 275 * memory is implemented by the model. 276 */ 277 switch (bld) { 278 case BLD_GIC_VE_MMAP: 279 ERROR("Legacy Versatile Express memory map for GIC peripheral" 280 " is not supported\n"); 281 panic(); 282 break; 283 case BLD_GIC_A53A57_MMAP: 284 break; 285 default: 286 ERROR("Unsupported board build %x\n", bld); 287 panic(); 288 } 289 290 /* 291 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 292 * for the Foundation FVP. 293 */ 294 switch (hbi) { 295 case HBI_FOUNDATION_FVP: 296 arm_config.flags = 0; 297 298 /* 299 * Check for supported revisions of Foundation FVP 300 * Allow future revisions to run but emit warning diagnostic 301 */ 302 switch (rev) { 303 case REV_FOUNDATION_FVP_V2_0: 304 case REV_FOUNDATION_FVP_V2_1: 305 case REV_FOUNDATION_FVP_v9_1: 306 case REV_FOUNDATION_FVP_v9_6: 307 break; 308 default: 309 WARN("Unrecognized Foundation FVP revision %x\n", rev); 310 break; 311 } 312 break; 313 case HBI_BASE_FVP: 314 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 315 316 /* 317 * Check for supported revisions 318 * Allow future revisions to run but emit warning diagnostic 319 */ 320 switch (rev) { 321 case REV_BASE_FVP_V0: 322 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 323 break; 324 case REV_BASE_FVP_REVC: 325 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 326 ARM_CONFIG_FVP_HAS_CCI5XX); 327 break; 328 default: 329 WARN("Unrecognized Base FVP revision %x\n", rev); 330 break; 331 } 332 break; 333 default: 334 ERROR("Unsupported board HBI number 0x%x\n", hbi); 335 panic(); 336 } 337 338 /* 339 * We assume that the presence of MT bit, and therefore shifted 340 * affinities, is uniform across the platform: either all CPUs, or no 341 * CPUs implement it. 342 */ 343 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 344 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 345 } 346 347 348 void __init fvp_interconnect_init(void) 349 { 350 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 351 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 352 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 353 panic(); 354 } 355 356 plat_arm_interconnect_init(); 357 #else 358 uintptr_t cci_base = 0U; 359 const int *cci_map = NULL; 360 unsigned int map_size = 0U; 361 362 /* Initialize the right interconnect */ 363 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 364 cci_base = PLAT_FVP_CCI5XX_BASE; 365 cci_map = fvp_cci5xx_map; 366 map_size = ARRAY_SIZE(fvp_cci5xx_map); 367 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 368 cci_base = PLAT_FVP_CCI400_BASE; 369 cci_map = fvp_cci400_map; 370 map_size = ARRAY_SIZE(fvp_cci400_map); 371 } else { 372 return; 373 } 374 375 assert(cci_base != 0U); 376 assert(cci_map != NULL); 377 cci_init(cci_base, cci_map, map_size); 378 #endif 379 } 380 381 void fvp_interconnect_enable(void) 382 { 383 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 384 plat_arm_interconnect_enter_coherency(); 385 #else 386 unsigned int master; 387 388 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 389 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 390 master = get_interconnect_master(); 391 cci_enable_snoop_dvm_reqs(master); 392 } 393 #endif 394 } 395 396 void fvp_interconnect_disable(void) 397 { 398 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 399 plat_arm_interconnect_exit_coherency(); 400 #else 401 unsigned int master; 402 403 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 404 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 405 master = get_interconnect_master(); 406 cci_disable_snoop_dvm_reqs(master); 407 } 408 #endif 409 } 410 411 #if TRUSTED_BOARD_BOOT 412 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 413 { 414 assert(heap_addr != NULL); 415 assert(heap_size != NULL); 416 417 return arm_get_mbedtls_heap(heap_addr, heap_size); 418 } 419 #endif 420 421 void fvp_timer_init(void) 422 { 423 #if FVP_USE_SP804_TIMER 424 /* Enable the clock override for SP804 timer 0, which means that no 425 * clock dividers are applied and the raw (35MHz) clock will be used. 426 */ 427 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 428 429 /* Initialize delay timer driver using SP804 dual timer 0 */ 430 sp804_timer_init(V2M_SP804_TIMER0_BASE, 431 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 432 #else 433 generic_delay_timer_init(); 434 435 /* Enable System level generic timer */ 436 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 437 CNTCR_FCREQ(0U) | CNTCR_EN); 438 #endif /* FVP_USE_SP804_TIMER */ 439 } 440