1 /* 2 * Copyright (C) 2016-2019 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #ifndef __ASSEMBLER__ 12 #include <stdio.h> 13 #endif /* __ASSEMBLER__ */ 14 15 #include <board_marvell_def.h> 16 #include <mvebu_def.h> 17 18 /* 19 * Most platform porting definitions provided by included headers 20 */ 21 22 /* 23 * DRAM Memory layout: 24 * +-----------------------+ 25 * : : 26 * : Linux : 27 * 0x04X00000-->+-----------------------+ 28 * | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 29 * |-----------------------| } | 30 * | BL3-[0,1, 2] | }---------------------------------> | 31 * |-----------------------| } || | 32 * | BL2 | }->FIP (loaded by || | 33 * |-----------------------| } BootROM to DRAM) || | 34 * | FIP_TOC | } || | 35 * 0x04120000-->|-----------------------| || | 36 * | BL1 (RO) | || | 37 * 0x04100000-->+-----------------------+ || | 38 * : : || | 39 * : Trusted SRAM section : \/ | 40 * 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ | 41 * | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | | 42 * 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| | 43 * | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | | 44 * 0x04023000-->|-----------------------| +----------------+ | 45 * | BL2 | | 46 * |-----------------------| | 47 * | | | 48 * 0x04001000-->|-----------------------| | 49 * | Shared | | 50 * 0x04000000-->+-----------------------+ | 51 * : : | 52 * : Linux : | 53 * : : | 54 * |-----------------------| | 55 * | | U-Boot(BL3-3) Loaded by BL2 | 56 * | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 57 * 0x00000000-->+-----------------------+ 58 * 59 * Trusted SRAM section 0x4000000..0x4200000: 60 * ---------------------------------------- 61 * SRAM_BASE = 0x4001000 62 * BL2_BASE = 0x4006000 63 * BL2_LIMIT = BL31_BASE 64 * BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000) 65 * BL31_PROGBITS_LIMIT = BL1_RW_BASE 66 * BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000) 67 * BL1_RW_LIMIT = BL31_LIMIT = 0x4040000 68 * 69 * 70 * PLAT_MARVELL_FIP_BASE = 0x4120000 71 */ 72 73 #define PLAT_MARVELL_ATF_BASE 0x4000000 74 #define PLAT_MARVELL_ATF_LOAD_ADDR \ 75 (PLAT_MARVELL_ATF_BASE + 0x100000) 76 77 #define PLAT_MARVELL_FIP_BASE \ 78 (PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000) 79 #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 80 81 #define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) 82 /* DRAM[2MB..66MB] is used as Trusted ROM */ 83 #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR 84 /* 4 MB for FIP image */ 85 #define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000 86 /* Reserve 12M for SCP (Secure PayLoad) Trusted RAM 87 * OP-TEE SHMEM follows this region 88 */ 89 #define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000 90 #define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */ 91 92 /* 93 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 94 * plus a little space for growth. 95 */ 96 #define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000 97 98 /* 99 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 100 * little space for growth. 101 */ 102 #define PLAT_MARVELL_MAX_BL2_SIZE 0xF000 103 104 /* 105 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 106 * little space for growth. 107 */ 108 #define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000 109 110 #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE 111 112 /* GIC related definitions */ 113 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) 114 #define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) 115 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) 116 117 #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ 118 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 119 GIC_INTR_CFG_LEVEL), \ 120 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 121 GIC_INTR_CFG_LEVEL) 122 123 #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ 124 INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, \ 125 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 126 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 127 GIC_INTR_CFG_LEVEL), \ 128 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 129 GIC_INTR_CFG_LEVEL), \ 130 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_LEVEL), \ 132 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_LEVEL), \ 134 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_LEVEL), \ 136 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_LEVEL) 138 139 140 #define PLAT_MARVELL_SHARED_RAM_CACHED 1 141 142 /* CCI related constants */ 143 #define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE) 144 #define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3 145 #define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4 146 147 /* 148 * Load address of BL3-3 for this platform port 149 */ 150 #define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0 151 152 /* System Reference Clock*/ 153 #define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY 154 155 /* 156 * PL011 related constants 157 */ 158 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000) 159 #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800 160 161 #define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 162 #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 163 164 #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 165 #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 166 167 /* Required platform porting definitions */ 168 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 169 170 /* System timer related constants */ 171 #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 172 173 /* Mailbox base address */ 174 #define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400) 175 #define PLAT_MARVELL_MAILBOX_SIZE 0x100 176 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ 177 178 /* DRAM CS memory map registers related constants */ 179 #define MVEBU_CS_MMAP_LOW(cs_num) \ 180 (MVEBU_CS_MMAP_REG_BASE + (cs_num) * 0x8) 181 #define MVEBU_CS_MMAP_ENABLE 0x1 182 #define MVEBU_CS_MMAP_AREA_LEN_OFFS 16 183 #define MVEBU_CS_MMAP_AREA_LEN_MASK \ 184 (0x1f << MVEBU_CS_MMAP_AREA_LEN_OFFS) 185 #define MVEBU_CS_MMAP_START_ADDR_LOW_OFFS 23 186 #define MVEBU_CS_MMAP_START_ADDR_LOW_MASK \ 187 (0x1ff << MVEBU_CS_MMAP_START_ADDR_LOW_OFFS) 188 189 #define MVEBU_CS_MMAP_HIGH(cs_num) \ 190 (MVEBU_CS_MMAP_REG_BASE + 0x4 + (cs_num) * 0x8) 191 192 /* DRAM max CS number */ 193 #define MVEBU_MAX_CS_MMAP_NUM (2) 194 195 /* CPU decoder window related constants */ 196 #define CPU_DEC_WIN_CTRL_REG(win_num) \ 197 (MVEBU_CPU_DEC_WIN_REG_BASE + (win_num) * 0x10) 198 #define CPU_DEC_CR_WIN_ENABLE 0x1 199 #define CPU_DEC_CR_WIN_TARGET_OFFS 4 200 #define CPU_DEC_CR_WIN_TARGET_MASK \ 201 (0xf << CPU_DEC_CR_WIN_TARGET_OFFS) 202 203 #define CPU_DEC_WIN_SIZE_REG(win_num) \ 204 (MVEBU_CPU_DEC_WIN_REG_BASE + 0x4 + (win_num) * 0x10) 205 #define CPU_DEC_CR_WIN_SIZE_OFFS 0 206 #define CPU_DEC_CR_WIN_SIZE_MASK \ 207 (0xffff << CPU_DEC_CR_WIN_SIZE_OFFS) 208 #define CPU_DEC_CR_WIN_SIZE_ALIGNMENT 0x10000 209 210 #define CPU_DEC_WIN_BASE_REG(win_num) \ 211 (MVEBU_CPU_DEC_WIN_REG_BASE + 0x8 + (win_num) * 0x10) 212 #define CPU_DEC_BR_BASE_OFFS 0 213 #define CPU_DEC_BR_BASE_MASK \ 214 (0xffff << CPU_DEC_BR_BASE_OFFS) 215 216 #define CPU_DEC_REMAP_LOW_REG(win_num) \ 217 (MVEBU_CPU_DEC_WIN_REG_BASE + 0xC + (win_num) * 0x10) 218 #define CPU_DEC_RLR_REMAP_LOW_OFFS 0 219 #define CPU_DEC_RLR_REMAP_LOW_MASK \ 220 (0xffff << CPU_DEC_BR_BASE_OFFS) 221 222 /* Securities */ 223 #define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER 224 225 #endif /* PLATFORM_DEF_H */ 226