1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.9 Build 41, unless otherwise stated. 16 17- ``FVP_Base_AEMv8A-AEMv8A`` 18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` 19- ``FVP_Base_RevC-2xAEMv8A`` 20- ``FVP_Base_Cortex-A32x4`` 21- ``FVP_Base_Cortex-A35x4`` 22- ``FVP_Base_Cortex-A53x4`` 23- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 24- ``FVP_Base_Cortex-A55x4`` 25- ``FVP_Base_Cortex-A57x1-A53x1`` 26- ``FVP_Base_Cortex-A57x2-A53x4`` 27- ``FVP_Base_Cortex-A57x4-A53x4`` 28- ``FVP_Base_Cortex-A57x4`` 29- ``FVP_Base_Cortex-A65x4`` 30- ``FVP_Base_Cortex-A65AEx8`` 31- ``FVP_Base_Cortex-A72x4-A53x4`` 32- ``FVP_Base_Cortex-A72x4`` 33- ``FVP_Base_Cortex-A73x4-A53x4`` 34- ``FVP_Base_Cortex-A73x4`` 35- ``FVP_Base_Cortex-A75x4`` 36- ``FVP_Base_Cortex-A76x4`` 37- ``FVP_Base_Cortex-A76AEx4`` 38- ``FVP_Base_Cortex-A76AEx8`` 39- ``FVP_Base_Cortex-A77x4`` 40- ``FVP_Base_Neoverse-E1x1`` 41- ``FVP_Base_Neoverse-E1x2`` 42- ``FVP_Base_Neoverse-E1x4`` 43- ``FVP_Base_Neoverse-N1x4`` 44- ``FVP_Base_Zeusx4`` 45- ``FVP_CSS_SGI-575`` (Version 11.10 build 25) 46- ``FVP_CSS_SGM-775`` 47- ``FVP_RD_E1Edge`` 48- ``FVP_RD_N1Edge`` (Version 11.10 build 25) 49- ``Foundation_Platform`` 50 51The latest version of the AArch32 build of TF-A has been tested on the 52following Arm FVPs without shifted affinities, and that do not support threaded 53CPU cores (64-bit host machine only). 54 55- ``FVP_Base_AEMv8A-AEMv8A`` 56- ``FVP_Base_Cortex-A32x4`` 57 58.. note:: 59 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which 60 is not compatible with legacy GIC configurations. Therefore this FVP does not 61 support these legacy GIC configurations. 62 63The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 64FVP website`_. The Cortex-A models listed above are also available to download 65from `Arm's website`_. 66 67.. note:: 68 The build numbers quoted above are those reported by launching the FVP 69 with the ``--version`` parameter. 70 71.. note:: 72 Linaro provides a ramdisk image in prebuilt FVP configurations and full 73 file systems that can be downloaded separately. To run an FVP with a virtio 74 file system image an additional FVP configuration option 75 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 76 used. 77 78.. note:: 79 The software will not work on Version 1.0 of the Foundation FVP. 80 The commands below would report an ``unhandled argument`` error in this case. 81 82.. note:: 83 FVPs can be launched with ``--cadi-server`` option such that a 84 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 85 its execution. 86 87.. warning:: 88 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 89 the internal synchronisation timings changed compared to older versions of 90 the models. The models can be launched with ``-Q 100`` option if they are 91 required to match the run time characteristics of the older versions. 92 93All the above platforms have been tested with `Linaro Release 19.06`_. 94 95.. _build_options_arm_fvp_platform: 96 97Arm FVP Platform Specific Build Options 98--------------------------------------- 99 100- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 101 build the topology tree within TF-A. By default TF-A is configured for dual 102 cluster topology and this option can be used to override the default value. 103 104- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 105 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 106 explained in the options below: 107 108 - ``FVP_CCI`` : The CCI driver is selected. This is the default 109 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 110 - ``FVP_CCN`` : The CCN driver is selected. This is the default 111 if ``FVP_CLUSTER_COUNT`` > 2. 112 113- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 114 a single cluster. This option defaults to 4. 115 116- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 117 in the system. This option defaults to 1. Note that the build option 118 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 119 120- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 121 122 - ``FVP_GICV2`` : The GICv2 only driver is selected 123 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 124 125- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer 126 for functions that wait for an arbitrary time length (udelay and mdelay). 127 The default value is 0. 128 129- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 130 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 131 details on HW_CONFIG. By default, this is initialized to a sensible DTS 132 file in ``fdts/`` folder depending on other build options. But some cases, 133 like shifted affinity format for MPIDR, cannot be detected at build time 134 and this option is needed to specify the appropriate DTS file. 135 136- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 137 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 138 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 139 HW_CONFIG blob instead of the DTS file. This option is useful to override 140 the default HW_CONFIG selected by the build system. 141 142Booting Firmware Update images 143------------------------------ 144 145When Firmware Update (FWU) is enabled there are at least 2 new images 146that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 147FWU FIP. 148 149The additional fip images must be loaded with: 150 151:: 152 153 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 154 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 155 156The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 157In the same way, the address ns_bl2u_base_address is the value of 158NS_BL2U_BASE. 159 160Booting an EL3 payload 161---------------------- 162 163The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 164the secondary CPUs holding pen to work properly. Unfortunately, its reset value 165is undefined on the FVP platform and the FVP platform code doesn't clear it. 166Therefore, one must modify the way the model is normally invoked in order to 167clear the mailbox at start-up. 168 169One way to do that is to create an 8-byte file containing all zero bytes using 170the following command: 171 172.. code:: shell 173 174 dd if=/dev/zero of=mailbox.dat bs=1 count=8 175 176and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 177using the following model parameters: 178 179:: 180 181 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 182 --data=mailbox.dat@0x04000000 [Foundation FVP] 183 184To provide the model with the EL3 payload image, the following methods may be 185used: 186 187#. If the EL3 payload is able to execute in place, it may be programmed into 188 flash memory. On Base Cortex and AEM FVPs, the following model parameter 189 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 190 used for the FIP): 191 192 :: 193 194 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 195 196 On Foundation FVP, there is no flash loader component and the EL3 payload 197 may be programmed anywhere in flash using method 3 below. 198 199#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 200 command may be used to load the EL3 payload ELF image over JTAG: 201 202 :: 203 204 load <path-to>/el3-payload.elf 205 206#. The EL3 payload may be pre-loaded in volatile memory using the following 207 model parameters: 208 209 :: 210 211 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 212 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 213 214 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 215 used when building TF-A. 216 217Booting a preloaded kernel image (Base FVP) 218------------------------------------------- 219 220The following example uses a simplified boot flow by directly jumping from the 221TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 222useful if both the kernel and the device tree blob (DTB) are already present in 223memory (like in FVP). 224 225For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 226address ``0x82000000``, the firmware can be built like this: 227 228.. code:: shell 229 230 CROSS_COMPILE=aarch64-none-elf- \ 231 make PLAT=fvp DEBUG=1 \ 232 RESET_TO_BL31=1 \ 233 ARM_LINUX_KERNEL_AS_BL33=1 \ 234 PRELOADED_BL33_BASE=0x80080000 \ 235 ARM_PRELOADED_DTB_BASE=0x82000000 \ 236 all fip 237 238Now, it is needed to modify the DTB so that the kernel knows the address of the 239ramdisk. The following script generates a patched DTB from the provided one, 240assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 241script assumes that the user is using a ramdisk image prepared for U-Boot, like 242the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 243offset in ``INITRD_START`` has to be removed. 244 245.. code:: bash 246 247 #!/bin/bash 248 249 # Path to the input DTB 250 KERNEL_DTB=<path-to>/<fdt> 251 # Path to the output DTB 252 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 253 # Base address of the ramdisk 254 INITRD_BASE=0x84000000 255 # Path to the ramdisk 256 INITRD=<path-to>/<ramdisk.img> 257 258 # Skip uboot header (64 bytes) 259 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 260 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 261 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 262 263 CHOSEN_NODE=$(echo \ 264 "/ { \ 265 chosen { \ 266 linux,initrd-start = <${INITRD_START}>; \ 267 linux,initrd-end = <${INITRD_END}>; \ 268 }; \ 269 };") 270 271 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 272 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 273 274And the FVP binary can be run with the following command: 275 276.. code:: shell 277 278 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 279 -C pctl.startup=0.0.0.0 \ 280 -C bp.secure_memory=1 \ 281 -C cluster0.NUM_CORES=4 \ 282 -C cluster1.NUM_CORES=4 \ 283 -C cache_state_modelled=1 \ 284 -C cluster0.cpu0.RVBAR=0x04001000 \ 285 -C cluster0.cpu1.RVBAR=0x04001000 \ 286 -C cluster0.cpu2.RVBAR=0x04001000 \ 287 -C cluster0.cpu3.RVBAR=0x04001000 \ 288 -C cluster1.cpu0.RVBAR=0x04001000 \ 289 -C cluster1.cpu1.RVBAR=0x04001000 \ 290 -C cluster1.cpu2.RVBAR=0x04001000 \ 291 -C cluster1.cpu3.RVBAR=0x04001000 \ 292 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 293 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 294 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 295 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 296 297Obtaining the Flattened Device Trees 298^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 299 300Depending on the FVP configuration and Linux configuration used, different 301FDT files are required. FDT source files for the Foundation and Base FVPs can 302be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 303a subset of the Base FVP components. For example, the Foundation FVP lacks 304CLCD and MMC support, and has only one CPU cluster. 305 306.. note:: 307 It is not recommended to use the FDTs built along the kernel because not 308 all FDTs are available from there. 309 310The dynamic configuration capability is enabled in the firmware for FVPs. 311This means that the firmware can authenticate and load the FDT if present in 312FIP. A default FDT is packaged into FIP during the build based on 313the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 314or ``FVP_HW_CONFIG_DTS`` build options (refer to 315:ref:`build_options_arm_fvp_platform` for details on the options). 316 317- ``fvp-base-gicv2-psci.dts`` 318 319 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 320 affinities and with Base memory map configuration. 321 322- ``fvp-base-gicv2-psci-aarch32.dts`` 323 324 For use with models such as the Cortex-A32 Base FVPs without shifted 325 affinities and running Linux in AArch32 state with Base memory map 326 configuration. 327 328- ``fvp-base-gicv3-psci.dts`` 329 330 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 331 affinities and with Base memory map configuration and Linux GICv3 support. 332 333- ``fvp-base-gicv3-psci-1t.dts`` 334 335 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 336 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 337 338- ``fvp-base-gicv3-psci-dynamiq.dts`` 339 340 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 341 single cluster, single threaded CPUs, Base memory map configuration and Linux 342 GICv3 support. 343 344- ``fvp-base-gicv3-psci-aarch32.dts`` 345 346 For use with models such as the Cortex-A32 Base FVPs without shifted 347 affinities and running Linux in AArch32 state with Base memory map 348 configuration and Linux GICv3 support. 349 350- ``fvp-foundation-gicv2-psci.dts`` 351 352 For use with Foundation FVP with Base memory map configuration. 353 354- ``fvp-foundation-gicv3-psci.dts`` 355 356 (Default) For use with Foundation FVP with Base memory map configuration 357 and Linux GICv3 support. 358 359 360Running on the Foundation FVP with reset to BL1 entrypoint 361^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 362 363The following ``Foundation_Platform`` parameters should be used to boot Linux with 3644 CPUs using the AArch64 build of TF-A. 365 366.. code:: shell 367 368 <path-to>/Foundation_Platform \ 369 --cores=4 \ 370 --arm-v8.0 \ 371 --secure-memory \ 372 --visualization \ 373 --gicv3 \ 374 --data="<path-to>/<bl1-binary>"@0x0 \ 375 --data="<path-to>/<FIP-binary>"@0x08000000 \ 376 --data="<path-to>/<kernel-binary>"@0x80080000 \ 377 --data="<path-to>/<ramdisk-binary>"@0x84000000 378 379Notes: 380 381- BL1 is loaded at the start of the Trusted ROM. 382- The Firmware Image Package is loaded at the start of NOR FLASH0. 383- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 384 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. 385- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 386 and enable the GICv3 device in the model. Note that without this option, 387 the Foundation FVP defaults to legacy (Versatile Express) memory map which 388 is not supported by TF-A. 389- In order for TF-A to run correctly on the Foundation FVP, the architecture 390 versions must match. The Foundation FVP defaults to the highest v8.x 391 version it supports but the default build for TF-A is for v8.0. To avoid 392 issues either start the Foundation FVP to use v8.0 architecture using the 393 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 394 ``ARM_ARCH_MINOR``. 395 396Running on the AEMv8 Base FVP with reset to BL1 entrypoint 397^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 398 399The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 400with 8 CPUs using the AArch64 build of TF-A. 401 402.. code:: shell 403 404 <path-to>/FVP_Base_RevC-2xAEMv8A \ 405 -C pctl.startup=0.0.0.0 \ 406 -C bp.secure_memory=1 \ 407 -C bp.tzc_400.diagnostics=1 \ 408 -C cluster0.NUM_CORES=4 \ 409 -C cluster1.NUM_CORES=4 \ 410 -C cache_state_modelled=1 \ 411 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 412 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 413 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 414 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 415 416.. note:: 417 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 418 a specific DTS for all the CPUs to be loaded. 419 420Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 421^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 422 423The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 424with 8 CPUs using the AArch32 build of TF-A. 425 426.. code:: shell 427 428 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 429 -C pctl.startup=0.0.0.0 \ 430 -C bp.secure_memory=1 \ 431 -C bp.tzc_400.diagnostics=1 \ 432 -C cluster0.NUM_CORES=4 \ 433 -C cluster1.NUM_CORES=4 \ 434 -C cache_state_modelled=1 \ 435 -C cluster0.cpu0.CONFIG64=0 \ 436 -C cluster0.cpu1.CONFIG64=0 \ 437 -C cluster0.cpu2.CONFIG64=0 \ 438 -C cluster0.cpu3.CONFIG64=0 \ 439 -C cluster1.cpu0.CONFIG64=0 \ 440 -C cluster1.cpu1.CONFIG64=0 \ 441 -C cluster1.cpu2.CONFIG64=0 \ 442 -C cluster1.cpu3.CONFIG64=0 \ 443 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 444 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 445 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 446 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 447 448Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 449^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 450 451The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 452boot Linux with 8 CPUs using the AArch64 build of TF-A. 453 454.. code:: shell 455 456 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 457 -C pctl.startup=0.0.0.0 \ 458 -C bp.secure_memory=1 \ 459 -C bp.tzc_400.diagnostics=1 \ 460 -C cache_state_modelled=1 \ 461 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 462 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 463 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 464 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 465 466Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 467^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 468 469The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 470boot Linux with 4 CPUs using the AArch32 build of TF-A. 471 472.. code:: shell 473 474 <path-to>/FVP_Base_Cortex-A32x4 \ 475 -C pctl.startup=0.0.0.0 \ 476 -C bp.secure_memory=1 \ 477 -C bp.tzc_400.diagnostics=1 \ 478 -C cache_state_modelled=1 \ 479 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 480 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 481 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 482 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 483 484 485Running on the AEMv8 Base FVP with reset to BL31 entrypoint 486^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 487 488The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 489with 8 CPUs using the AArch64 build of TF-A. 490 491.. code:: shell 492 493 <path-to>/FVP_Base_RevC-2xAEMv8A \ 494 -C pctl.startup=0.0.0.0 \ 495 -C bp.secure_memory=1 \ 496 -C bp.tzc_400.diagnostics=1 \ 497 -C cluster0.NUM_CORES=4 \ 498 -C cluster1.NUM_CORES=4 \ 499 -C cache_state_modelled=1 \ 500 -C cluster0.cpu0.RVBAR=0x04010000 \ 501 -C cluster0.cpu1.RVBAR=0x04010000 \ 502 -C cluster0.cpu2.RVBAR=0x04010000 \ 503 -C cluster0.cpu3.RVBAR=0x04010000 \ 504 -C cluster1.cpu0.RVBAR=0x04010000 \ 505 -C cluster1.cpu1.RVBAR=0x04010000 \ 506 -C cluster1.cpu2.RVBAR=0x04010000 \ 507 -C cluster1.cpu3.RVBAR=0x04010000 \ 508 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 509 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 510 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 511 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 512 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 513 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 514 515Notes: 516 517- If Position Independent Executable (PIE) support is enabled for BL31 518 in this config, it can be loaded at any valid address for execution. 519 520- Since a FIP is not loaded when using BL31 as reset entrypoint, the 521 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 522 parameter is needed to load the individual bootloader images in memory. 523 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 524 Payload. For the same reason, the FDT needs to be compiled from the DT source 525 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 526 parameter. 527 528- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 529 specific DTS for all the CPUs to be loaded. 530 531- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 532 X and Y are the cluster and CPU numbers respectively, is used to set the 533 reset vector for each core. 534 535- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 536 changing the value of 537 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 538 ``BL32_BASE``. 539 540 541Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 542^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 543 544The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 545with 8 CPUs using the AArch32 build of TF-A. 546 547.. code:: shell 548 549 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 550 -C pctl.startup=0.0.0.0 \ 551 -C bp.secure_memory=1 \ 552 -C bp.tzc_400.diagnostics=1 \ 553 -C cluster0.NUM_CORES=4 \ 554 -C cluster1.NUM_CORES=4 \ 555 -C cache_state_modelled=1 \ 556 -C cluster0.cpu0.CONFIG64=0 \ 557 -C cluster0.cpu1.CONFIG64=0 \ 558 -C cluster0.cpu2.CONFIG64=0 \ 559 -C cluster0.cpu3.CONFIG64=0 \ 560 -C cluster1.cpu0.CONFIG64=0 \ 561 -C cluster1.cpu1.CONFIG64=0 \ 562 -C cluster1.cpu2.CONFIG64=0 \ 563 -C cluster1.cpu3.CONFIG64=0 \ 564 -C cluster0.cpu0.RVBAR=0x04002000 \ 565 -C cluster0.cpu1.RVBAR=0x04002000 \ 566 -C cluster0.cpu2.RVBAR=0x04002000 \ 567 -C cluster0.cpu3.RVBAR=0x04002000 \ 568 -C cluster1.cpu0.RVBAR=0x04002000 \ 569 -C cluster1.cpu1.RVBAR=0x04002000 \ 570 -C cluster1.cpu2.RVBAR=0x04002000 \ 571 -C cluster1.cpu3.RVBAR=0x04002000 \ 572 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 573 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 574 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 575 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 576 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 577 578.. note:: 579 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. 580 It should match the address programmed into the RVBAR register as well. 581 582Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 583^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 584 585The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 586boot Linux with 8 CPUs using the AArch64 build of TF-A. 587 588.. code:: shell 589 590 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 591 -C pctl.startup=0.0.0.0 \ 592 -C bp.secure_memory=1 \ 593 -C bp.tzc_400.diagnostics=1 \ 594 -C cache_state_modelled=1 \ 595 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 596 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 597 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 598 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 599 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 600 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 601 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 602 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 603 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 604 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 605 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 606 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 607 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 608 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 609 610Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 611^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 612 613The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 614boot Linux with 4 CPUs using the AArch32 build of TF-A. 615 616.. code:: shell 617 618 <path-to>/FVP_Base_Cortex-A32x4 \ 619 -C pctl.startup=0.0.0.0 \ 620 -C bp.secure_memory=1 \ 621 -C bp.tzc_400.diagnostics=1 \ 622 -C cache_state_modelled=1 \ 623 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 624 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 625 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 626 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 627 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 628 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 629 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 630 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 631 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 632 633-------------- 634 635*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 636 637.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts 638.. _Arm's website: `FVP models`_ 639.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 640.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 641.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 642