1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <spe.h> 25 #include <tegra_def.h> 26 #include <tegra_platform.h> 27 #include <tegra_private.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 30 /* ID for spe-console */ 31 #define TEGRA_CONSOLE_SPE_ID 0xFE 32 33 /******************************************************************************* 34 * Structure to store the SCR addresses and its expected settings. 35 ******************************************************************************* 36 */ 37 typedef struct { 38 uint32_t scr_addr; 39 uint32_t scr_val; 40 } scr_settings_t; 41 42 static const scr_settings_t t194_scr_settings[] = { 43 { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL }, 44 { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL }, 45 { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL }, 46 { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL }, 47 { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL }, 48 { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL }, 49 { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL }, 50 { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL }, 51 { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL } 52 }; 53 54 /******************************************************************************* 55 * The Tegra power domain tree has a single system level power domain i.e. a 56 * single root node. The first entry in the power domain descriptor specifies 57 * the number of power domains at the highest power level. 58 ******************************************************************************* 59 */ 60 static const uint8_t tegra_power_domain_tree_desc[] = { 61 /* No of root nodes */ 62 1, 63 /* No of clusters */ 64 PLATFORM_CLUSTER_COUNT, 65 /* No of CPU cores - cluster0 */ 66 PLATFORM_MAX_CPUS_PER_CLUSTER, 67 /* No of CPU cores - cluster1 */ 68 PLATFORM_MAX_CPUS_PER_CLUSTER, 69 /* No of CPU cores - cluster2 */ 70 PLATFORM_MAX_CPUS_PER_CLUSTER, 71 /* No of CPU cores - cluster3 */ 72 PLATFORM_MAX_CPUS_PER_CLUSTER 73 }; 74 75 /******************************************************************************* 76 * This function returns the Tegra default topology tree information. 77 ******************************************************************************/ 78 const uint8_t *plat_get_power_domain_tree_desc(void) 79 { 80 return tegra_power_domain_tree_desc; 81 } 82 83 /* 84 * Table of regions to map using the MMU. 85 */ 86 static const mmap_region_t tegra_mmap[] = { 87 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ 88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ 90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ 92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ 94 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 95 #if !ENABLE_CONSOLE_SPE 96 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 97 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 99 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 102 #endif 103 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ 104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 105 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ 106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 107 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ 108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 109 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ 110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 111 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ 112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 113 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ 114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 115 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ 116 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 117 #if ENABLE_CONSOLE_SPE 118 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ 119 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 120 #endif 121 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ 122 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 123 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ 124 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 125 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ 126 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 127 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ 128 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 129 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ 130 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 131 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ 132 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 133 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 134 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 135 {0} 136 }; 137 138 /******************************************************************************* 139 * Set up the pagetables as per the platform memory map & initialize the MMU 140 ******************************************************************************/ 141 const mmap_region_t *plat_get_mmio_map(void) 142 { 143 /* MMIO space */ 144 return tegra_mmap; 145 } 146 147 /******************************************************************************* 148 * Handler to get the System Counter Frequency 149 ******************************************************************************/ 150 uint32_t plat_get_syscnt_freq2(void) 151 { 152 return 31250000; 153 } 154 155 #if !ENABLE_CONSOLE_SPE 156 /******************************************************************************* 157 * Maximum supported UART controllers 158 ******************************************************************************/ 159 #define TEGRA194_MAX_UART_PORTS 7 160 161 /******************************************************************************* 162 * This variable holds the UART port base addresses 163 ******************************************************************************/ 164 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 165 0, /* undefined - treated as an error case */ 166 TEGRA_UARTA_BASE, 167 TEGRA_UARTB_BASE, 168 TEGRA_UARTC_BASE, 169 TEGRA_UARTD_BASE, 170 TEGRA_UARTE_BASE, 171 TEGRA_UARTF_BASE, 172 TEGRA_UARTG_BASE 173 }; 174 #endif 175 176 /******************************************************************************* 177 * Enable console corresponding to the console ID 178 ******************************************************************************/ 179 void plat_enable_console(int32_t id) 180 { 181 uint32_t console_clock = 0U; 182 183 #if ENABLE_CONSOLE_SPE 184 static console_t spe_console; 185 186 if (id == TEGRA_CONSOLE_SPE_ID) { 187 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, 188 console_clock, 189 TEGRA_CONSOLE_BAUDRATE, 190 &spe_console); 191 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT | 192 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 193 } 194 #else 195 static console_t uart_console; 196 197 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { 198 /* 199 * Reference clock used by the FPGAs is a lot slower. 200 */ 201 if (tegra_platform_is_fpga()) { 202 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 203 } else { 204 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 205 } 206 207 (void)console_16550_register(tegra194_uart_addresses[id], 208 console_clock, 209 TEGRA_CONSOLE_BAUDRATE, 210 &uart_console); 211 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | 212 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 213 } 214 #endif 215 } 216 217 /******************************************************************************* 218 * Verify SCR settings 219 ******************************************************************************/ 220 static inline bool tegra194_is_scr_valid(void) 221 { 222 uint32_t scr_val; 223 bool ret = true; 224 225 for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) { 226 scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr); 227 if (scr_val != t194_scr_settings[i].scr_val) { 228 ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr); 229 ret = false; 230 } 231 } 232 return ret; 233 } 234 235 /******************************************************************************* 236 * Handler for early platform setup 237 ******************************************************************************/ 238 void plat_early_platform_setup(void) 239 { 240 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 241 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; 242 uint64_t actlr_elx; 243 244 /* Verify chip id is t194 */ 245 assert(tegra_chipid_is_t194()); 246 247 /* Verify SCR settings */ 248 if (tegra_platform_is_silicon()) { 249 assert(tegra194_is_scr_valid()); 250 } 251 252 /* sanity check MCE firmware compatibility */ 253 mce_verify_firmware_version(); 254 255 #if RAS_EXTENSION 256 /* Enable Uncorrectable RAS error */ 257 tegra194_ras_enable(); 258 #endif 259 260 /* 261 * Program XUSB STREAMIDs 262 * ====================== 263 * T19x XUSB has support for XUSB virtualization. It will have one 264 * physical function (PF) and four Virtual function (VF) 265 * 266 * There were below two SIDs for XUSB until T186. 267 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 268 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 269 * 270 * We have below four new SIDs added for VF(s) 271 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 272 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 273 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 274 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 275 * 276 * When virtualization is enabled then we have to disable SID override 277 * and program above SIDs in below newly added SID registers in XUSB 278 * PADCTL MMIO space. These registers are TZ protected and so need to 279 * be done in ATF. 280 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 281 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 282 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 283 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 284 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 285 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 286 * 287 * This change disables SID override and programs XUSB SIDs in 288 * above registers to support both virtualization and 289 * non-virtualization platforms 290 */ 291 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 292 293 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 294 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 295 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 296 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST); 297 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 298 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 299 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 300 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0); 301 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 302 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 303 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 304 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1); 305 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 306 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 307 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 308 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2); 309 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 310 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 311 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 312 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3); 313 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 314 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 315 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 316 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV); 317 } 318 319 /* 320 * Enable dual execution optimized translations for all ELx. 321 */ 322 if (enable_ccplex_lock_step != 0U) { 323 actlr_elx = read_actlr_el3(); 324 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; 325 write_actlr_el3(actlr_elx); 326 /* check if the bit is actually set */ 327 assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL); 328 329 actlr_elx = read_actlr_el2(); 330 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; 331 write_actlr_el2(actlr_elx); 332 /* check if the bit is actually set */ 333 assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL); 334 335 actlr_elx = read_actlr_el1(); 336 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; 337 write_actlr_el1(actlr_elx); 338 /* check if the bit is actually set */ 339 assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL); 340 } 341 } 342 343 /* Secure IRQs for Tegra194 */ 344 static const interrupt_prop_t tegra194_interrupt_props[] = { 345 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI, 346 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 347 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO, 348 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 349 }; 350 351 /******************************************************************************* 352 * Initialize the GIC and SGIs 353 ******************************************************************************/ 354 void plat_gic_setup(void) 355 { 356 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 357 tegra_gic_init(); 358 359 /* 360 * Initialize the FIQ handler 361 */ 362 tegra_fiq_handler_setup(); 363 } 364 365 /******************************************************************************* 366 * Return pointer to the BL31 params from previous bootloader 367 ******************************************************************************/ 368 struct tegra_bl31_params *plat_get_bl31_params(void) 369 { 370 uint64_t val; 371 372 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & 373 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; 374 val <<= 32; 375 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); 376 377 return (struct tegra_bl31_params *)(uintptr_t)val; 378 } 379 380 /******************************************************************************* 381 * Return pointer to the BL31 platform params from previous bootloader 382 ******************************************************************************/ 383 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 384 { 385 uint64_t val; 386 387 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & 388 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; 389 val <<= 32; 390 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); 391 392 return (plat_params_from_bl2_t *)(uintptr_t)val; 393 } 394 395 /******************************************************************************* 396 * Handler for late platform setup 397 ******************************************************************************/ 398 void plat_late_platform_setup(void) 399 { 400 #if ENABLE_STRICT_CHECKING_MODE 401 /* 402 * Enable strict checking after programming the GSC for 403 * enabling TZSRAM and TZDRAM 404 */ 405 mce_enable_strict_checking(); 406 mce_verify_strict_checking(); 407 #endif 408 } 409 410 /******************************************************************************* 411 * Handler to indicate support for System Suspend 412 ******************************************************************************/ 413 bool plat_supports_system_suspend(void) 414 { 415 return true; 416 } 417