1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11 12#if CTX_INCLUDE_EL2_REGS 13 .global el2_sysregs_context_save 14 .global el2_sysregs_context_restore 15#endif 16 17 .global el1_sysregs_context_save 18 .global el1_sysregs_context_restore 19#if CTX_INCLUDE_FPREGS 20 .global fpregs_context_save 21 .global fpregs_context_restore 22#endif 23 .global save_gp_pmcr_pauth_regs 24 .global restore_gp_pmcr_pauth_regs 25 .global el3_exit 26 27#if CTX_INCLUDE_EL2_REGS 28 29/* ----------------------------------------------------- 30 * The following function strictly follows the AArch64 31 * PCS to use x9-x17 (temporary caller-saved registers) 32 * to save EL2 system register context. It assumes that 33 * 'x0' is pointing to a 'el2_sys_regs' structure where 34 * the register context will be saved. 35 * 36 * The following registers are not added. 37 * AMEVCNTVOFF0<n>_EL2 38 * AMEVCNTVOFF1<n>_EL2 39 * ICH_AP0R<n>_EL2 40 * ICH_AP1R<n>_EL2 41 * ICH_LR<n>_EL2 42 * ----------------------------------------------------- 43 */ 44 45func el2_sysregs_context_save 46 mrs x9, actlr_el2 47 mrs x10, afsr0_el2 48 stp x9, x10, [x0, #CTX_ACTLR_EL2] 49 50 mrs x11, afsr1_el2 51 mrs x12, amair_el2 52 stp x11, x12, [x0, #CTX_AFSR1_EL2] 53 54 mrs x13, cnthctl_el2 55 mrs x14, cnthp_ctl_el2 56 stp x13, x14, [x0, #CTX_CNTHCTL_EL2] 57 58 mrs x15, cnthp_cval_el2 59 mrs x16, cnthp_tval_el2 60 stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 61 62 mrs x17, cntvoff_el2 63 mrs x9, cptr_el2 64 stp x17, x9, [x0, #CTX_CNTVOFF_EL2] 65 66 mrs x10, dbgvcr32_el2 67 mrs x11, elr_el2 68 stp x10, x11, [x0, #CTX_DBGVCR32_EL2] 69 70 mrs x14, esr_el2 71 mrs x15, far_el2 72 stp x14, x15, [x0, #CTX_ESR_EL2] 73 74 mrs x16, hacr_el2 75 mrs x17, hcr_el2 76 stp x16, x17, [x0, #CTX_HACR_EL2] 77 78 mrs x9, hpfar_el2 79 mrs x10, hstr_el2 80 stp x9, x10, [x0, #CTX_HPFAR_EL2] 81 82 mrs x11, ICC_SRE_EL2 83 mrs x12, ICH_HCR_EL2 84 stp x11, x12, [x0, #CTX_ICC_SRE_EL2] 85 86 mrs x13, ICH_VMCR_EL2 87 mrs x14, mair_el2 88 stp x13, x14, [x0, #CTX_ICH_VMCR_EL2] 89 90 mrs x15, mdcr_el2 91 mrs x16, PMSCR_EL2 92 stp x15, x16, [x0, #CTX_MDCR_EL2] 93 94 mrs x17, sctlr_el2 95 mrs x9, spsr_el2 96 stp x17, x9, [x0, #CTX_SCTLR_EL2] 97 98 mrs x10, sp_el2 99 mrs x11, tcr_el2 100 stp x10, x11, [x0, #CTX_SP_EL2] 101 102 mrs x12, tpidr_el2 103 mrs x13, ttbr0_el2 104 stp x12, x13, [x0, #CTX_TPIDR_EL2] 105 106 mrs x14, vbar_el2 107 mrs x15, vmpidr_el2 108 stp x14, x15, [x0, #CTX_VBAR_EL2] 109 110 mrs x16, vpidr_el2 111 mrs x17, vtcr_el2 112 stp x16, x17, [x0, #CTX_VPIDR_EL2] 113 114 mrs x9, vttbr_el2 115 str x9, [x0, #CTX_VTTBR_EL2] 116 117#if CTX_INCLUDE_MTE_REGS 118 mrs x10, TFSR_EL2 119 str x10, [x0, #CTX_TFSR_EL2] 120#endif 121 122#if ENABLE_MPAM_FOR_LOWER_ELS 123 mrs x9, MPAM2_EL2 124 mrs x10, MPAMHCR_EL2 125 stp x9, x10, [x0, #CTX_MPAM2_EL2] 126 127 mrs x11, MPAMVPM0_EL2 128 mrs x12, MPAMVPM1_EL2 129 stp x11, x12, [x0, #CTX_MPAMVPM0_EL2] 130 131 mrs x13, MPAMVPM2_EL2 132 mrs x14, MPAMVPM3_EL2 133 stp x13, x14, [x0, #CTX_MPAMVPM2_EL2] 134 135 mrs x15, MPAMVPM4_EL2 136 mrs x16, MPAMVPM5_EL2 137 stp x15, x16, [x0, #CTX_MPAMVPM4_EL2] 138 139 mrs x17, MPAMVPM6_EL2 140 mrs x9, MPAMVPM7_EL2 141 stp x17, x9, [x0, #CTX_MPAMVPM6_EL2] 142 143 mrs x10, MPAMVPMV_EL2 144 str x10, [x0, #CTX_MPAMVPMV_EL2] 145#endif 146 147 148#if ARM_ARCH_AT_LEAST(8, 6) 149 mrs x11, HAFGRTR_EL2 150 mrs x12, HDFGRTR_EL2 151 stp x11, x12, [x0, #CTX_HAFGRTR_EL2] 152 153 mrs x13, HDFGWTR_EL2 154 mrs x14, HFGITR_EL2 155 stp x13, x14, [x0, #CTX_HDFGWTR_EL2] 156 157 mrs x15, HFGRTR_EL2 158 mrs x16, HFGWTR_EL2 159 stp x15, x16, [x0, #CTX_HFGRTR_EL2] 160 161 mrs x17, CNTPOFF_EL2 162 str x17, [x0, #CTX_CNTPOFF_EL2] 163#endif 164 165#if ARM_ARCH_AT_LEAST(8, 4) 166 mrs x9, cnthps_ctl_el2 167 mrs x10, cnthps_cval_el2 168 stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] 169 170 mrs x11, cnthps_tval_el2 171 mrs x12, cnthvs_ctl_el2 172 stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] 173 174 mrs x13, cnthvs_cval_el2 175 mrs x14, cnthvs_tval_el2 176 stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] 177 178 mrs x15, cnthv_ctl_el2 179 mrs x16, cnthv_cval_el2 180 stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] 181 182 mrs x17, cnthv_tval_el2 183 mrs x9, contextidr_el2 184 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] 185 186 mrs x10, sder32_el2 187 str x10, [x0, #CTX_SDER32_EL2] 188 189 mrs x11, ttbr1_el2 190 str x11, [x0, #CTX_TTBR1_EL2] 191 192 mrs x12, vdisr_el2 193 str x12, [x0, #CTX_VDISR_EL2] 194 195 mrs x13, vncr_el2 196 str x13, [x0, #CTX_VNCR_EL2] 197 198 mrs x14, vsesr_el2 199 str x14, [x0, #CTX_VSESR_EL2] 200 201 mrs x15, vstcr_el2 202 str x15, [x0, #CTX_VSTCR_EL2] 203 204 mrs x16, vsttbr_el2 205 str x16, [x0, #CTX_VSTTBR_EL2] 206 207 mrs x17, TRFCR_EL2 208 str x17, [x0, #CTX_TRFCR_EL2] 209#endif 210 211#if ARM_ARCH_AT_LEAST(8, 5) 212 mrs x9, scxtnum_el2 213 str x9, [x0, #CTX_SCXTNUM_EL2] 214#endif 215 216 ret 217endfunc el2_sysregs_context_save 218 219/* ----------------------------------------------------- 220 * The following function strictly follows the AArch64 221 * PCS to use x9-x17 (temporary caller-saved registers) 222 * to restore EL2 system register context. It assumes 223 * that 'x0' is pointing to a 'el2_sys_regs' structure 224 * from where the register context will be restored 225 226 * The following registers are not restored 227 * AMEVCNTVOFF0<n>_EL2 228 * AMEVCNTVOFF1<n>_EL2 229 * ICH_AP0R<n>_EL2 230 * ICH_AP1R<n>_EL2 231 * ICH_LR<n>_EL2 232 * ----------------------------------------------------- 233 */ 234func el2_sysregs_context_restore 235 236 ldp x9, x10, [x0, #CTX_ACTLR_EL2] 237 msr actlr_el2, x9 238 msr afsr0_el2, x10 239 240 ldp x11, x12, [x0, #CTX_AFSR1_EL2] 241 msr afsr1_el2, x11 242 msr amair_el2, x12 243 244 ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] 245 msr cnthctl_el2, x13 246 msr cnthp_ctl_el2, x14 247 248 ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] 249 msr cnthp_cval_el2, x15 250 msr cnthp_tval_el2, x16 251 252 ldp x17, x9, [x0, #CTX_CNTVOFF_EL2] 253 msr cntvoff_el2, x17 254 msr cptr_el2, x9 255 256 ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] 257 msr dbgvcr32_el2, x10 258 msr elr_el2, x11 259 260 ldp x14, x15, [x0, #CTX_ESR_EL2] 261 msr esr_el2, x14 262 msr far_el2, x15 263 264 ldp x16, x17, [x0, #CTX_HACR_EL2] 265 msr hacr_el2, x16 266 msr hcr_el2, x17 267 268 ldp x9, x10, [x0, #CTX_HPFAR_EL2] 269 msr hpfar_el2, x9 270 msr hstr_el2, x10 271 272 ldp x11, x12, [x0, #CTX_ICC_SRE_EL2] 273 msr ICC_SRE_EL2, x11 274 msr ICH_HCR_EL2, x12 275 276 ldp x13, x14, [x0, #CTX_ICH_VMCR_EL2] 277 msr ICH_VMCR_EL2, x13 278 msr mair_el2, x14 279 280 ldp x15, x16, [x0, #CTX_MDCR_EL2] 281 msr mdcr_el2, x15 282 msr PMSCR_EL2, x16 283 284 ldp x17, x9, [x0, #CTX_SCTLR_EL2] 285 msr sctlr_el2, x17 286 msr spsr_el2, x9 287 288 ldp x10, x11, [x0, #CTX_SP_EL2] 289 msr sp_el2, x10 290 msr tcr_el2, x11 291 292 ldp x12, x13, [x0, #CTX_TPIDR_EL2] 293 msr tpidr_el2, x12 294 msr ttbr0_el2, x13 295 296 ldp x13, x14, [x0, #CTX_VBAR_EL2] 297 msr vbar_el2, x13 298 msr vmpidr_el2, x14 299 300 ldp x15, x16, [x0, #CTX_VPIDR_EL2] 301 msr vpidr_el2, x15 302 msr vtcr_el2, x16 303 304 ldr x17, [x0, #CTX_VTTBR_EL2] 305 msr vttbr_el2, x17 306 307#if CTX_INCLUDE_MTE_REGS 308 ldr x9, [x0, #CTX_TFSR_EL2] 309 msr TFSR_EL2, x9 310#endif 311 312#if ENABLE_MPAM_FOR_LOWER_ELS 313 ldp x10, x11, [x0, #CTX_MPAM2_EL2] 314 msr MPAM2_EL2, x10 315 msr MPAMHCR_EL2, x11 316 317 ldp x12, x13, [x0, #CTX_MPAMVPM0_EL2] 318 msr MPAMVPM0_EL2, x12 319 msr MPAMVPM1_EL2, x13 320 321 ldp x14, x15, [x0, #CTX_MPAMVPM2_EL2] 322 msr MPAMVPM2_EL2, x14 323 msr MPAMVPM3_EL2, x15 324 325 ldp x16, x17, [x0, #CTX_MPAMVPM4_EL2] 326 msr MPAMVPM4_EL2, x16 327 msr MPAMVPM5_EL2, x17 328 329 ldp x9, x10, [x0, #CTX_MPAMVPM6_EL2] 330 msr MPAMVPM6_EL2, x9 331 msr MPAMVPM7_EL2, x10 332 333 ldr x11, [x0, #CTX_MPAMVPMV_EL2] 334 msr MPAMVPMV_EL2, x11 335#endif 336 337#if ARM_ARCH_AT_LEAST(8, 6) 338 ldp x12, x13, [x0, #CTX_HAFGRTR_EL2] 339 msr HAFGRTR_EL2, x12 340 msr HDFGRTR_EL2, x13 341 342 ldp x14, x15, [x0, #CTX_HDFGWTR_EL2] 343 msr HDFGWTR_EL2, x14 344 msr HFGITR_EL2, x15 345 346 ldp x16, x17, [x0, #CTX_HFGRTR_EL2] 347 msr HFGRTR_EL2, x16 348 msr HFGWTR_EL2, x17 349 350 ldr x9, [x0, #CTX_CNTPOFF_EL2] 351 msr CNTPOFF_EL2, x9 352#endif 353 354#if ARM_ARCH_AT_LEAST(8, 4) 355 ldp x10, x11, [x0, #CTX_CNTHPS_CTL_EL2] 356 msr cnthps_ctl_el2, x10 357 msr cnthps_cval_el2, x11 358 359 ldp x12, x13, [x0, #CTX_CNTHPS_TVAL_EL2] 360 msr cnthps_tval_el2, x12 361 msr cnthvs_ctl_el2, x13 362 363 ldp x14, x15, [x0, #CTX_CNTHVS_CVAL_EL2] 364 msr cnthvs_cval_el2, x14 365 msr cnthvs_tval_el2, x15 366 367 ldp x16, x17, [x0, #CTX_CNTHV_CTL_EL2] 368 msr cnthv_ctl_el2, x16 369 msr cnthv_cval_el2, x17 370 371 ldp x9, x10, [x0, #CTX_CNTHV_TVAL_EL2] 372 msr cnthv_tval_el2, x9 373 msr contextidr_el2, x10 374 375 ldr x11, [x0, #CTX_SDER32_EL2] 376 msr sder32_el2, x11 377 378 ldr x12, [x0, #CTX_TTBR1_EL2] 379 msr ttbr1_el2, x12 380 381 ldr x13, [x0, #CTX_VDISR_EL2] 382 msr vdisr_el2, x13 383 384 ldr x14, [x0, #CTX_VNCR_EL2] 385 msr vncr_el2, x14 386 387 ldr x15, [x0, #CTX_VSESR_EL2] 388 msr vsesr_el2, x15 389 390 ldr x16, [x0, #CTX_VSTCR_EL2] 391 msr vstcr_el2, x16 392 393 ldr x17, [x0, #CTX_VSTTBR_EL2] 394 msr vsttbr_el2, x17 395 396 ldr x9, [x0, #CTX_TRFCR_EL2] 397 msr TRFCR_EL2, x9 398#endif 399 400#if ARM_ARCH_AT_LEAST(8, 5) 401 ldr x10, [x0, #CTX_SCXTNUM_EL2] 402 msr scxtnum_el2, x10 403#endif 404 405 ret 406endfunc el2_sysregs_context_restore 407 408#endif /* CTX_INCLUDE_EL2_REGS */ 409 410/* ------------------------------------------------------------------ 411 * The following function strictly follows the AArch64 PCS to use 412 * x9-x17 (temporary caller-saved registers) to save EL1 system 413 * register context. It assumes that 'x0' is pointing to a 414 * 'el1_sys_regs' structure where the register context will be saved. 415 * ------------------------------------------------------------------ 416 */ 417func el1_sysregs_context_save 418 419 mrs x9, spsr_el1 420 mrs x10, elr_el1 421 stp x9, x10, [x0, #CTX_SPSR_EL1] 422 423 mrs x15, sctlr_el1 424 mrs x16, tcr_el1 425 stp x15, x16, [x0, #CTX_SCTLR_EL1] 426 427 mrs x17, cpacr_el1 428 mrs x9, csselr_el1 429 stp x17, x9, [x0, #CTX_CPACR_EL1] 430 431 mrs x10, sp_el1 432 mrs x11, esr_el1 433 stp x10, x11, [x0, #CTX_SP_EL1] 434 435 mrs x12, ttbr0_el1 436 mrs x13, ttbr1_el1 437 stp x12, x13, [x0, #CTX_TTBR0_EL1] 438 439 mrs x14, mair_el1 440 mrs x15, amair_el1 441 stp x14, x15, [x0, #CTX_MAIR_EL1] 442 443 mrs x16, actlr_el1 444 mrs x17, tpidr_el1 445 stp x16, x17, [x0, #CTX_ACTLR_EL1] 446 447 mrs x9, tpidr_el0 448 mrs x10, tpidrro_el0 449 stp x9, x10, [x0, #CTX_TPIDR_EL0] 450 451 mrs x13, par_el1 452 mrs x14, far_el1 453 stp x13, x14, [x0, #CTX_PAR_EL1] 454 455 mrs x15, afsr0_el1 456 mrs x16, afsr1_el1 457 stp x15, x16, [x0, #CTX_AFSR0_EL1] 458 459 mrs x17, contextidr_el1 460 mrs x9, vbar_el1 461 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 462 463 /* Save AArch32 system registers if the build has instructed so */ 464#if CTX_INCLUDE_AARCH32_REGS 465 mrs x11, spsr_abt 466 mrs x12, spsr_und 467 stp x11, x12, [x0, #CTX_SPSR_ABT] 468 469 mrs x13, spsr_irq 470 mrs x14, spsr_fiq 471 stp x13, x14, [x0, #CTX_SPSR_IRQ] 472 473 mrs x15, dacr32_el2 474 mrs x16, ifsr32_el2 475 stp x15, x16, [x0, #CTX_DACR32_EL2] 476#endif 477 478 /* Save NS timer registers if the build has instructed so */ 479#if NS_TIMER_SWITCH 480 mrs x10, cntp_ctl_el0 481 mrs x11, cntp_cval_el0 482 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 483 484 mrs x12, cntv_ctl_el0 485 mrs x13, cntv_cval_el0 486 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 487 488 mrs x14, cntkctl_el1 489 str x14, [x0, #CTX_CNTKCTL_EL1] 490#endif 491 492 /* Save MTE system registers if the build has instructed so */ 493#if CTX_INCLUDE_MTE_REGS 494 mrs x15, TFSRE0_EL1 495 mrs x16, TFSR_EL1 496 stp x15, x16, [x0, #CTX_TFSRE0_EL1] 497 498 mrs x9, RGSR_EL1 499 mrs x10, GCR_EL1 500 stp x9, x10, [x0, #CTX_RGSR_EL1] 501#endif 502 503 ret 504endfunc el1_sysregs_context_save 505 506/* ------------------------------------------------------------------ 507 * The following function strictly follows the AArch64 PCS to use 508 * x9-x17 (temporary caller-saved registers) to restore EL1 system 509 * register context. It assumes that 'x0' is pointing to a 510 * 'el1_sys_regs' structure from where the register context will be 511 * restored 512 * ------------------------------------------------------------------ 513 */ 514func el1_sysregs_context_restore 515 516 ldp x9, x10, [x0, #CTX_SPSR_EL1] 517 msr spsr_el1, x9 518 msr elr_el1, x10 519 520 ldp x15, x16, [x0, #CTX_SCTLR_EL1] 521 msr sctlr_el1, x15 522 msr tcr_el1, x16 523 524 ldp x17, x9, [x0, #CTX_CPACR_EL1] 525 msr cpacr_el1, x17 526 msr csselr_el1, x9 527 528 ldp x10, x11, [x0, #CTX_SP_EL1] 529 msr sp_el1, x10 530 msr esr_el1, x11 531 532 ldp x12, x13, [x0, #CTX_TTBR0_EL1] 533 msr ttbr0_el1, x12 534 msr ttbr1_el1, x13 535 536 ldp x14, x15, [x0, #CTX_MAIR_EL1] 537 msr mair_el1, x14 538 msr amair_el1, x15 539 540 ldp x16, x17, [x0, #CTX_ACTLR_EL1] 541 msr actlr_el1, x16 542 msr tpidr_el1, x17 543 544 ldp x9, x10, [x0, #CTX_TPIDR_EL0] 545 msr tpidr_el0, x9 546 msr tpidrro_el0, x10 547 548 ldp x13, x14, [x0, #CTX_PAR_EL1] 549 msr par_el1, x13 550 msr far_el1, x14 551 552 ldp x15, x16, [x0, #CTX_AFSR0_EL1] 553 msr afsr0_el1, x15 554 msr afsr1_el1, x16 555 556 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 557 msr contextidr_el1, x17 558 msr vbar_el1, x9 559 560 /* Restore AArch32 system registers if the build has instructed so */ 561#if CTX_INCLUDE_AARCH32_REGS 562 ldp x11, x12, [x0, #CTX_SPSR_ABT] 563 msr spsr_abt, x11 564 msr spsr_und, x12 565 566 ldp x13, x14, [x0, #CTX_SPSR_IRQ] 567 msr spsr_irq, x13 568 msr spsr_fiq, x14 569 570 ldp x15, x16, [x0, #CTX_DACR32_EL2] 571 msr dacr32_el2, x15 572 msr ifsr32_el2, x16 573#endif 574 /* Restore NS timer registers if the build has instructed so */ 575#if NS_TIMER_SWITCH 576 ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 577 msr cntp_ctl_el0, x10 578 msr cntp_cval_el0, x11 579 580 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 581 msr cntv_ctl_el0, x12 582 msr cntv_cval_el0, x13 583 584 ldr x14, [x0, #CTX_CNTKCTL_EL1] 585 msr cntkctl_el1, x14 586#endif 587 /* Restore MTE system registers if the build has instructed so */ 588#if CTX_INCLUDE_MTE_REGS 589 ldp x11, x12, [x0, #CTX_TFSRE0_EL1] 590 msr TFSRE0_EL1, x11 591 msr TFSR_EL1, x12 592 593 ldp x13, x14, [x0, #CTX_RGSR_EL1] 594 msr RGSR_EL1, x13 595 msr GCR_EL1, x14 596#endif 597 598 /* No explict ISB required here as ERET covers it */ 599 ret 600endfunc el1_sysregs_context_restore 601 602/* ------------------------------------------------------------------ 603 * The following function follows the aapcs_64 strictly to use 604 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 605 * to save floating point register context. It assumes that 'x0' is 606 * pointing to a 'fp_regs' structure where the register context will 607 * be saved. 608 * 609 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 610 * However currently we don't use VFP registers nor set traps in 611 * Trusted Firmware, and assume it's cleared. 612 * 613 * TODO: Revisit when VFP is used in secure world 614 * ------------------------------------------------------------------ 615 */ 616#if CTX_INCLUDE_FPREGS 617func fpregs_context_save 618 stp q0, q1, [x0, #CTX_FP_Q0] 619 stp q2, q3, [x0, #CTX_FP_Q2] 620 stp q4, q5, [x0, #CTX_FP_Q4] 621 stp q6, q7, [x0, #CTX_FP_Q6] 622 stp q8, q9, [x0, #CTX_FP_Q8] 623 stp q10, q11, [x0, #CTX_FP_Q10] 624 stp q12, q13, [x0, #CTX_FP_Q12] 625 stp q14, q15, [x0, #CTX_FP_Q14] 626 stp q16, q17, [x0, #CTX_FP_Q16] 627 stp q18, q19, [x0, #CTX_FP_Q18] 628 stp q20, q21, [x0, #CTX_FP_Q20] 629 stp q22, q23, [x0, #CTX_FP_Q22] 630 stp q24, q25, [x0, #CTX_FP_Q24] 631 stp q26, q27, [x0, #CTX_FP_Q26] 632 stp q28, q29, [x0, #CTX_FP_Q28] 633 stp q30, q31, [x0, #CTX_FP_Q30] 634 635 mrs x9, fpsr 636 str x9, [x0, #CTX_FP_FPSR] 637 638 mrs x10, fpcr 639 str x10, [x0, #CTX_FP_FPCR] 640 641#if CTX_INCLUDE_AARCH32_REGS 642 mrs x11, fpexc32_el2 643 str x11, [x0, #CTX_FP_FPEXC32_EL2] 644#endif 645 ret 646endfunc fpregs_context_save 647 648/* ------------------------------------------------------------------ 649 * The following function follows the aapcs_64 strictly to use x9-x17 650 * (temporary caller-saved registers according to AArch64 PCS) to 651 * restore floating point register context. It assumes that 'x0' is 652 * pointing to a 'fp_regs' structure from where the register context 653 * will be restored. 654 * 655 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 656 * However currently we don't use VFP registers nor set traps in 657 * Trusted Firmware, and assume it's cleared. 658 * 659 * TODO: Revisit when VFP is used in secure world 660 * ------------------------------------------------------------------ 661 */ 662func fpregs_context_restore 663 ldp q0, q1, [x0, #CTX_FP_Q0] 664 ldp q2, q3, [x0, #CTX_FP_Q2] 665 ldp q4, q5, [x0, #CTX_FP_Q4] 666 ldp q6, q7, [x0, #CTX_FP_Q6] 667 ldp q8, q9, [x0, #CTX_FP_Q8] 668 ldp q10, q11, [x0, #CTX_FP_Q10] 669 ldp q12, q13, [x0, #CTX_FP_Q12] 670 ldp q14, q15, [x0, #CTX_FP_Q14] 671 ldp q16, q17, [x0, #CTX_FP_Q16] 672 ldp q18, q19, [x0, #CTX_FP_Q18] 673 ldp q20, q21, [x0, #CTX_FP_Q20] 674 ldp q22, q23, [x0, #CTX_FP_Q22] 675 ldp q24, q25, [x0, #CTX_FP_Q24] 676 ldp q26, q27, [x0, #CTX_FP_Q26] 677 ldp q28, q29, [x0, #CTX_FP_Q28] 678 ldp q30, q31, [x0, #CTX_FP_Q30] 679 680 ldr x9, [x0, #CTX_FP_FPSR] 681 msr fpsr, x9 682 683 ldr x10, [x0, #CTX_FP_FPCR] 684 msr fpcr, x10 685 686#if CTX_INCLUDE_AARCH32_REGS 687 ldr x11, [x0, #CTX_FP_FPEXC32_EL2] 688 msr fpexc32_el2, x11 689#endif 690 /* 691 * No explict ISB required here as ERET to 692 * switch to secure EL1 or non-secure world 693 * covers it 694 */ 695 696 ret 697endfunc fpregs_context_restore 698#endif /* CTX_INCLUDE_FPREGS */ 699 700/* ------------------------------------------------------------------ 701 * The following function is used to save and restore all the general 702 * purpose and ARMv8.3-PAuth (if enabled) registers. 703 * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 704 * when ARMv8.5-PMU is implemented, and if called from Non-secure 705 * state saves PMCR_EL0 and disables Cycle Counter. 706 * 707 * Ideally we would only save and restore the callee saved registers 708 * when a world switch occurs but that type of implementation is more 709 * complex. So currently we will always save and restore these 710 * registers on entry and exit of EL3. 711 * These are not macros to ensure their invocation fits within the 32 712 * instructions per exception vector. 713 * clobbers: x18 714 * ------------------------------------------------------------------ 715 */ 716func save_gp_pmcr_pauth_regs 717 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 718 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 719 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 720 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 721 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 722 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 723 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 724 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 725 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 726 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 727 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 728 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 729 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 730 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 731 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 732 mrs x18, sp_el0 733 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 734 735 /* ---------------------------------------------------------- 736 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 737 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 738 * should be saved in non-secure context. 739 * ---------------------------------------------------------- 740 */ 741 mrs x9, mdcr_el3 742 tst x9, #MDCR_SCCD_BIT 743 bne 1f 744 745 /* Secure Cycle Counter is not disabled */ 746 mrs x9, pmcr_el0 747 748 /* Check caller's security state */ 749 mrs x10, scr_el3 750 tst x10, #SCR_NS_BIT 751 beq 2f 752 753 /* Save PMCR_EL0 if called from Non-secure state */ 754 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 755 756 /* Disable cycle counter when event counting is prohibited */ 7572: orr x9, x9, #PMCR_EL0_DP_BIT 758 msr pmcr_el0, x9 759 isb 7601: 761#if CTX_INCLUDE_PAUTH_REGS 762 /* ---------------------------------------------------------- 763 * Save the ARMv8.3-PAuth keys as they are not banked 764 * by exception level 765 * ---------------------------------------------------------- 766 */ 767 add x19, sp, #CTX_PAUTH_REGS_OFFSET 768 769 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 770 mrs x21, APIAKeyHi_EL1 771 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 772 mrs x23, APIBKeyHi_EL1 773 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 774 mrs x25, APDAKeyHi_EL1 775 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 776 mrs x27, APDBKeyHi_EL1 777 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 778 mrs x29, APGAKeyHi_EL1 779 780 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 781 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 782 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 783 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 784 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 785#endif /* CTX_INCLUDE_PAUTH_REGS */ 786 787 ret 788endfunc save_gp_pmcr_pauth_regs 789 790/* ------------------------------------------------------------------ 791 * This function restores ARMv8.3-PAuth (if enabled) and all general 792 * purpose registers except x30 from the CPU context. 793 * x30 register must be explicitly restored by the caller. 794 * ------------------------------------------------------------------ 795 */ 796func restore_gp_pmcr_pauth_regs 797#if CTX_INCLUDE_PAUTH_REGS 798 /* Restore the ARMv8.3 PAuth keys */ 799 add x10, sp, #CTX_PAUTH_REGS_OFFSET 800 801 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 802 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 803 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 804 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 805 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 806 807 msr APIAKeyLo_EL1, x0 808 msr APIAKeyHi_EL1, x1 809 msr APIBKeyLo_EL1, x2 810 msr APIBKeyHi_EL1, x3 811 msr APDAKeyLo_EL1, x4 812 msr APDAKeyHi_EL1, x5 813 msr APDBKeyLo_EL1, x6 814 msr APDBKeyHi_EL1, x7 815 msr APGAKeyLo_EL1, x8 816 msr APGAKeyHi_EL1, x9 817#endif /* CTX_INCLUDE_PAUTH_REGS */ 818 819 /* ---------------------------------------------------------- 820 * Restore PMCR_EL0 when returning to Non-secure state if 821 * Secure Cycle Counter is not disabled in MDCR_EL3 when 822 * ARMv8.5-PMU is implemented. 823 * ---------------------------------------------------------- 824 */ 825 mrs x0, scr_el3 826 tst x0, #SCR_NS_BIT 827 beq 2f 828 829 /* ---------------------------------------------------------- 830 * Back to Non-secure state. 831 * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, 832 * meaning that ARMv8-PMU is not implemented and PMCR_EL0 833 * should be restored from non-secure context. 834 * ---------------------------------------------------------- 835 */ 836 mrs x0, mdcr_el3 837 tst x0, #MDCR_SCCD_BIT 838 bne 2f 839 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 840 msr pmcr_el0, x0 8412: 842 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 843 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 844 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 845 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 846 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 847 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 848 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 849 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 850 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 851 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 852 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 853 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 854 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 855 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 856 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 857 msr sp_el0, x28 858 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 859 ret 860endfunc restore_gp_pmcr_pauth_regs 861 862/* ------------------------------------------------------------------ 863 * This routine assumes that the SP_EL3 is pointing to a valid 864 * context structure from where the gp regs and other special 865 * registers can be retrieved. 866 * ------------------------------------------------------------------ 867 */ 868func el3_exit 869#if ENABLE_ASSERTIONS 870 /* el3_exit assumes SP_EL0 on entry */ 871 mrs x17, spsel 872 cmp x17, #MODE_SP_EL0 873 ASM_ASSERT(eq) 874#endif 875 876 /* ---------------------------------------------------------- 877 * Save the current SP_EL0 i.e. the EL3 runtime stack which 878 * will be used for handling the next SMC. 879 * Then switch to SP_EL3. 880 * ---------------------------------------------------------- 881 */ 882 mov x17, sp 883 msr spsel, #MODE_SP_ELX 884 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 885 886 /* ---------------------------------------------------------- 887 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 888 * ---------------------------------------------------------- 889 */ 890 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 891 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 892 msr scr_el3, x18 893 msr spsr_el3, x16 894 msr elr_el3, x17 895 896#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 897 /* ---------------------------------------------------------- 898 * Restore mitigation state as it was on entry to EL3 899 * ---------------------------------------------------------- 900 */ 901 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 902 cbz x17, 1f 903 blr x17 9041: 905#endif 906 /* ---------------------------------------------------------- 907 * Restore general purpose (including x30), PMCR_EL0 and 908 * ARMv8.3-PAuth registers. 909 * Exit EL3 via ERET to a lower exception level. 910 * ---------------------------------------------------------- 911 */ 912 bl restore_gp_pmcr_pauth_regs 913 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 914 915#if IMAGE_BL31 && RAS_EXTENSION 916 /* ---------------------------------------------------------- 917 * Issue Error Synchronization Barrier to synchronize SErrors 918 * before exiting EL3. We're running with EAs unmasked, so 919 * any synchronized errors would be taken immediately; 920 * therefore no need to inspect DISR_EL1 register. 921 * ---------------------------------------------------------- 922 */ 923 esb 924#endif 925 exception_return 926 927endfunc el3_exit 928