1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <drivers/arm/smmu_v3.h> 10 #include <fconf_hw_config_getter.h> 11 #include <lib/fconf/fconf.h> 12 #include <lib/mmio.h> 13 #include <plat/arm/common/arm_config.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 17 #include "fvp_private.h" 18 19 uintptr_t hw_config_dtb; 20 21 void __init bl31_early_platform_setup2(u_register_t arg0, 22 u_register_t arg1, u_register_t arg2, u_register_t arg3) 23 { 24 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 25 26 /* Initialize the platform config for future decision making */ 27 fvp_config_setup(); 28 29 /* 30 * Initialize the correct interconnect for this cluster during cold 31 * boot. No need for locks as no other CPU is active. 32 */ 33 fvp_interconnect_init(); 34 35 /* 36 * Enable coherency in interconnect for the primary CPU's cluster. 37 * Earlier bootloader stages might already do this (e.g. Trusted 38 * Firmware's BL1 does it) but we can't assume so. There is no harm in 39 * executing this code twice anyway. 40 * FVP PSCI code will enable coherency for other clusters. 41 */ 42 fvp_interconnect_enable(); 43 44 /* Initialize System level generic or SP804 timer */ 45 fvp_timer_init(); 46 47 /* On FVP RevC, initialize SMMUv3 */ 48 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) 49 smmuv3_init(PLAT_FVP_SMMUV3_BASE); 50 51 hw_config_dtb = arg2; 52 } 53 54 void __init bl31_plat_arch_setup(void) 55 { 56 arm_bl31_plat_arch_setup(); 57 58 /* 59 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run. 60 * So there is no BL2 to load the HW_CONFIG dtb into memory before 61 * control is passed to BL31. 62 */ 63 #if !RESET_TO_BL31 && !BL2_AT_EL3 64 assert(hw_config_dtb != 0U); 65 66 INFO("BL31 FCONF: HW_CONFIG address = %p\n", (void *)hw_config_dtb); 67 fconf_populate("HW_CONFIG", hw_config_dtb); 68 #endif 69 } 70 71 unsigned int plat_get_syscnt_freq2(void) 72 { 73 unsigned int counter_base_frequency; 74 75 #if !RESET_TO_BL31 && !BL2_AT_EL3 76 /* Get the frequency through FCONF API for HW_CONFIG */ 77 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq); 78 if (counter_base_frequency > 0U) { 79 return counter_base_frequency; 80 } 81 #endif 82 83 /* Read the frequency from Frequency modes table */ 84 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 85 86 /* The first entry of the frequency modes table must not be 0 */ 87 if (counter_base_frequency == 0U) { 88 panic(); 89 } 90 91 return counter_base_frequency; 92 } 93