1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Chip specific cluster and cpu numbers 14 ******************************************************************************/ 15 #define PLATFORM_CLUSTER_COUNT U(4) 16 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 17 18 /******************************************************************************* 19 * Chip specific page table and MMU setup constants 20 ******************************************************************************/ 21 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) 22 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 23 24 /******************************************************************************* 25 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 26 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 27 * parameter. 28 ******************************************************************************/ 29 #define PSTATE_ID_CORE_IDLE U(6) 30 #define PSTATE_ID_CORE_POWERDN U(7) 31 #define PSTATE_ID_SOC_POWERDN U(2) 32 33 /******************************************************************************* 34 * Platform power states (used by PSCI framework) 35 * 36 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 37 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 38 ******************************************************************************/ 39 #define PLAT_MAX_RET_STATE U(1) 40 #define PLAT_MAX_OFF_STATE U(8) 41 42 /******************************************************************************* 43 * Secure IRQ definitions 44 ******************************************************************************/ 45 #define TEGRA194_MAX_SEC_IRQS U(2) 46 #define TEGRA194_TOP_WDT_IRQ U(49) 47 #define TEGRA194_AON_WDT_IRQ U(50) 48 49 #define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ 50 51 /******************************************************************************* 52 * Clock identifier for the SE device 53 ******************************************************************************/ 54 #define TEGRA194_CLK_SE U(124) 55 #define TEGRA_CLK_SE TEGRA194_CLK_SE 56 57 /******************************************************************************* 58 * Tegra Miscellanous register constants 59 ******************************************************************************/ 60 #define TEGRA_MISC_BASE U(0x00100000) 61 62 #define HARDWARE_REVISION_OFFSET U(0x4) 63 #define MISCREG_EMU_REVID U(0x3160) 64 #define BOARD_MASK_BITS U(0xFF) 65 #define BOARD_SHIFT_BITS U(24) 66 #define MISCREG_PFCFG U(0x200C) 67 68 /******************************************************************************* 69 * Tegra General Purpose Centralised DMA constants 70 ******************************************************************************/ 71 #define TEGRA_GPCDMA_BASE U(0x02610000) 72 73 /******************************************************************************* 74 * Tegra Memory Controller constants 75 ******************************************************************************/ 76 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 77 #define TEGRA_MC_BASE U(0x02C10000) 78 79 /* General Security Carveout register macros */ 80 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 81 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 82 #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) 83 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 84 #define MC_GSC_BASE_LO_SHIFT U(12) 85 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 86 #define MC_GSC_BASE_HI_SHIFT U(0) 87 #define MC_GSC_BASE_HI_MASK U(3) 88 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 89 90 /* TZDRAM carveout configuration registers */ 91 #define MC_SECURITY_CFG0_0 U(0x70) 92 #define MC_SECURITY_CFG1_0 U(0x74) 93 #define MC_SECURITY_CFG3_0 U(0x9BC) 94 95 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 96 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 97 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 98 99 #define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) 100 #define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) 101 #define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0) 102 #define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1) 103 104 /* Video Memory carveout configuration registers */ 105 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 106 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 107 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 108 #define MC_VIDEO_PROTECT_REG_CTRL U(0x650) 109 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) 110 111 /* 112 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 113 * non-overlapping Video memory region 114 */ 115 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 116 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 117 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 118 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 119 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 120 121 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 122 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 123 #define MC_TZRAM_BASE_LO U(0x2194) 124 #define MC_TZRAM_BASE_HI U(0x2198) 125 #define MC_TZRAM_SIZE U(0x219C) 126 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 127 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 128 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 129 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 130 131 /* Memory Controller Reset Control registers */ 132 #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) 133 #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) 134 #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) 135 #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) 136 137 /******************************************************************************* 138 * Tegra UART Controller constants 139 ******************************************************************************/ 140 #define TEGRA_UARTA_BASE U(0x03100000) 141 #define TEGRA_UARTB_BASE U(0x03110000) 142 #define TEGRA_UARTC_BASE U(0x0C280000) 143 #define TEGRA_UARTD_BASE U(0x03130000) 144 #define TEGRA_UARTE_BASE U(0x03140000) 145 #define TEGRA_UARTF_BASE U(0x03150000) 146 #define TEGRA_UARTG_BASE U(0x0C290000) 147 148 /******************************************************************************* 149 * XUSB PADCTL 150 ******************************************************************************/ 151 #define TEGRA_XUSB_PADCTL_BASE U(0x03520000) 152 #define TEGRA_XUSB_PADCTL_SIZE U(0x10000) 153 #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) 154 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) 155 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) 156 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) 157 #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) 158 #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) 159 160 /******************************************************************************* 161 * Tegra Fuse Controller related constants 162 ******************************************************************************/ 163 #define TEGRA_FUSE_BASE U(0x03820000) 164 #define OPT_SUBREVISION U(0x248) 165 #define SUBREVISION_MASK U(0xF) 166 167 /******************************************************************************* 168 * GICv2 & interrupt handling related constants 169 ******************************************************************************/ 170 #define TEGRA_GICD_BASE U(0x03881000) 171 #define TEGRA_GICC_BASE U(0x03882000) 172 173 /******************************************************************************* 174 * Security Engine related constants 175 ******************************************************************************/ 176 #define TEGRA_SE0_BASE U(0x03AC0000) 177 #define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 178 #define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC) 179 #define TEGRA_PKA1_BASE U(0x03AD0000) 180 #define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144) 181 #define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL 182 #define TEGRA_RNG1_BASE U(0x03AE0000) 183 #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 184 185 /******************************************************************************* 186 * Tegra HSP doorbell #0 constants 187 ******************************************************************************/ 188 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) 189 #define HSP_DBELL_1_ENABLE U(0x104) 190 #define HSP_DBELL_3_TRIGGER U(0x300) 191 #define HSP_DBELL_3_ENABLE U(0x304) 192 193 /******************************************************************************* 194 * Tegra hardware synchronization primitives for the SPE engine 195 ******************************************************************************/ 196 #define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) 197 #define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000)) 198 199 /******************************************************************************* 200 * Tegra micro-seconds timer constants 201 ******************************************************************************/ 202 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 203 #define TEGRA_TMRUS_SIZE U(0x10000) 204 205 /******************************************************************************* 206 * Tegra Power Mgmt Controller constants 207 ******************************************************************************/ 208 #define TEGRA_PMC_BASE U(0x0C360000) 209 210 /******************************************************************************* 211 * Tegra scratch registers constants 212 ******************************************************************************/ 213 #define TEGRA_SCRATCH_BASE U(0x0C390000) 214 #define SECURE_SCRATCH_RSV68_LO U(0x284) 215 #define SECURE_SCRATCH_RSV68_HI U(0x288) 216 #define SECURE_SCRATCH_RSV69_LO U(0x28C) 217 #define SECURE_SCRATCH_RSV69_HI U(0x290) 218 #define SECURE_SCRATCH_RSV70_LO U(0x294) 219 #define SECURE_SCRATCH_RSV70_HI U(0x298) 220 #define SECURE_SCRATCH_RSV71_LO U(0x29C) 221 #define SECURE_SCRATCH_RSV71_HI U(0x2A0) 222 #define SECURE_SCRATCH_RSV72_LO U(0x2A4) 223 #define SECURE_SCRATCH_RSV72_HI U(0x2A8) 224 #define SECURE_SCRATCH_RSV75 U(0x2BC) 225 #define SECURE_SCRATCH_RSV81_LO U(0x2EC) 226 #define SECURE_SCRATCH_RSV81_HI U(0x2F0) 227 #define SECURE_SCRATCH_RSV97 U(0x36C) 228 #define SECURE_SCRATCH_RSV99_LO U(0x37C) 229 #define SECURE_SCRATCH_RSV99_HI U(0x380) 230 #define SECURE_SCRATCH_RSV109_LO U(0x3CC) 231 #define SECURE_SCRATCH_RSV109_HI U(0x3D0) 232 233 #define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 234 #define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) 235 #define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) 236 #define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO 237 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 238 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) 239 #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) 240 #define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI 241 #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 242 #define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO 243 #define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI 244 #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO 245 #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI 246 247 /******************************************************************************* 248 * Tegra Memory Mapped Control Register Access Bus constants 249 ******************************************************************************/ 250 #define TEGRA_MMCRAB_BASE U(0x0E000000) 251 252 /******************************************************************************* 253 * Tegra SMMU Controller constants 254 ******************************************************************************/ 255 #define TEGRA_SMMU0_BASE U(0x12000000) 256 #define TEGRA_SMMU1_BASE U(0x11000000) 257 #define TEGRA_SMMU2_BASE U(0x10000000) 258 259 /******************************************************************************* 260 * Tegra TZRAM constants 261 ******************************************************************************/ 262 #define TEGRA_TZRAM_BASE U(0x40000000) 263 #define TEGRA_TZRAM_SIZE U(0x40000) 264 265 /******************************************************************************* 266 * Tegra CCPLEX-BPMP IPC constants 267 ******************************************************************************/ 268 #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) 269 #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) 270 #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ 271 272 /******************************************************************************* 273 * Tegra Clock and Reset Controller constants 274 ******************************************************************************/ 275 #define TEGRA_CAR_RESET_BASE U(0x20000000) 276 #define TEGRA_GPU_RESET_REG_OFFSET U(0x18) 277 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) 278 #define GPU_RESET_BIT (U(1) << 0) 279 #define GPU_SET_BIT (U(1) << 0) 280 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 281 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 282 283 /******************************************************************************* 284 * Tegra DRAM memory base address 285 ******************************************************************************/ 286 #define TEGRA_DRAM_BASE ULL(0x80000000) 287 #define TEGRA_DRAM_END ULL(0xFFFFFFFFF) 288 289 /******************************************************************************* 290 * XUSB STREAMIDs 291 ******************************************************************************/ 292 #define TEGRA_SID_XUSB_HOST U(0x1b) 293 #define TEGRA_SID_XUSB_DEV U(0x1c) 294 #define TEGRA_SID_XUSB_VF0 U(0x5d) 295 #define TEGRA_SID_XUSB_VF1 U(0x5e) 296 #define TEGRA_SID_XUSB_VF2 U(0x5f) 297 #define TEGRA_SID_XUSB_VF3 U(0x60) 298 299 /******************************************************************************* 300 * SCR addresses and expected settings 301 ******************************************************************************/ 302 #define SCRATCH_RSV68_SCR U(0x0C398110) 303 #define SCRATCH_RSV68_SCR_VAL U(0x38000101) 304 #define SCRATCH_RSV71_SCR U(0x0C39811C) 305 #define SCRATCH_RSV71_SCR_VAL U(0x38000101) 306 #define SCRATCH_RSV72_SCR U(0x0C398120) 307 #define SCRATCH_RSV72_SCR_VAL U(0x38000101) 308 #define SCRATCH_RSV75_SCR U(0x0C39812C) 309 #define SCRATCH_RSV75_SCR_VAL U(0x3A000005) 310 #define SCRATCH_RSV81_SCR U(0x0C398144) 311 #define SCRATCH_RSV81_SCR_VAL U(0x3A000105) 312 #define SCRATCH_RSV97_SCR U(0x0C398184) 313 #define SCRATCH_RSV97_SCR_VAL U(0x38000101) 314 #define SCRATCH_RSV99_SCR U(0x0C39818C) 315 #define SCRATCH_RSV99_SCR_VAL U(0x38000101) 316 #define SCRATCH_RSV109_SCR U(0x0C3981B4) 317 #define SCRATCH_RSV109_SCR_VAL U(0x38000101) 318 #define MISCREG_SCR_SCRTZWELCK U(0x00109000) 319 #define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100) 320 321 #endif /* TEGRA_DEF_H */ 322