| 591d80c8 | 04-Dec-2019 |
Lionel Debieve <lionel.debieve@st.com> |
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by: Lionel Debieve <
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 63d21598 | 02-Mar-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the driver, depending on the plaftorm characteristics.
Change-Id: I38161b659
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the driver, depending on the plaftorm characteristics.
Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
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| 88f4fb8f | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR.
Change-Id
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR.
Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 5def13eb | 10-Sep-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Sig
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
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| 258bef91 | 10-May-2019 |
Yann Gautier <yann.gautier@st.com> |
feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required. For this we need to: - disable vmmc-supply regulator - make the power cycle required for
feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required. For this we need to: - disable vmmc-supply regulator - make the power cycle required for SDMMC2 peripheral - enable regulators
Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 85fb175b | 27-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.
Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a Signed-off-by: Pascal Paillet <p.paillet@s
feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.
Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| d5b4a2c4 | 15-Dec-2020 |
Pascal Paillet <p.paillet@st.com> |
feat(regulator): add a regulator framework
Add a regulator framework to: - provide an interface to consumers and drivers, - connect consumers with drivers, - handle most of devicetree-parsing, - han
feat(regulator): add a regulator framework
Add a regulator framework to: - provide an interface to consumers and drivers, - connect consumers with drivers, - handle most of devicetree-parsing, - handle always-on and boot-on regulators, - handle min/max voltages,
Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53 Signed-off-by: Pascal Paillet <p.paillet@st.com>
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| ea552bf5 | 15-Dec-2020 |
Pascal Paillet <p.paillet@st.com> |
feat(stpmic1): add new services
Add support for ICC, sink mode, bypass mode, active discharge and list voltages. Handle LDO3 sink source mode in a different way to avoid setting voltage while in sin
feat(stpmic1): add new services
Add support for ICC, sink mode, bypass mode, active discharge and list voltages. Handle LDO3 sink source mode in a different way to avoid setting voltage while in sink source mode.
Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534 Signed-off-by: Pascal Paillet <p.paillet@st.com>
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| 13fbfe04 | 10-Jan-2020 |
Etienne Carriere <etienne.carriere@st.com> |
feat(stpmic1): add USB OTG regulators
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are needed since manipulated durin
feat(stpmic1): add USB OTG regulators
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are needed since manipulated during the suspend/resume power sequence as per FDT description for stm32mp15x-xxx boards from STMicroelectronics.
Change-Id: I6217de707e49882bd5a9100db43e0d354908800d Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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