1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory@c0000000 { 24 device_type = "memory"; 25 reg = <0xC0000000 0x40000000>; 26 }; 27 28 aliases { 29 serial0 = &uart4; 30 }; 31}; 32 33&bsec { 34 board_id: board_id@ec { 35 reg = <0xec 0x4>; 36 status = "okay"; 37 secure-status = "okay"; 38 }; 39}; 40 41&clk_hse { 42 st,digbypass; 43}; 44 45&cpu0 { 46 cpu-supply = <&vddcore>; 47}; 48 49&cpu1 { 50 cpu-supply = <&vddcore>; 51}; 52 53&cryp1 { 54 status = "okay"; 55}; 56 57&hash1 { 58 status = "okay"; 59}; 60 61&i2c4 { 62 pinctrl-names = "default"; 63 pinctrl-0 = <&i2c4_pins_a>; 64 i2c-scl-rising-time-ns = <185>; 65 i2c-scl-falling-time-ns = <20>; 66 clock-frequency = <400000>; 67 status = "okay"; 68 69 pmic: stpmic@33 { 70 compatible = "st,stpmic1"; 71 reg = <0x33>; 72 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 73 interrupt-controller; 74 #interrupt-cells = <2>; 75 status = "okay"; 76 77 regulators { 78 compatible = "st,stpmic1-regulators"; 79 ldo1-supply = <&v3v3>; 80 ldo2-supply = <&v3v3>; 81 ldo3-supply = <&vdd_ddr>; 82 ldo5-supply = <&v3v3>; 83 ldo6-supply = <&v3v3>; 84 pwr_sw1-supply = <&bst_out>; 85 pwr_sw2-supply = <&bst_out>; 86 87 vddcore: buck1 { 88 regulator-name = "vddcore"; 89 regulator-min-microvolt = <1200000>; 90 regulator-max-microvolt = <1350000>; 91 regulator-always-on; 92 regulator-initial-mode = <0>; 93 regulator-over-current-protection; 94 }; 95 96 vdd_ddr: buck2 { 97 regulator-name = "vdd_ddr"; 98 regulator-min-microvolt = <1350000>; 99 regulator-max-microvolt = <1350000>; 100 regulator-always-on; 101 regulator-initial-mode = <0>; 102 regulator-over-current-protection; 103 }; 104 105 vdd: buck3 { 106 regulator-name = "vdd"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 st,mask-reset; 111 regulator-initial-mode = <0>; 112 regulator-over-current-protection; 113 }; 114 115 v3v3: buck4 { 116 regulator-name = "v3v3"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 regulator-always-on; 120 regulator-over-current-protection; 121 regulator-initial-mode = <0>; 122 }; 123 124 vdda: ldo1 { 125 regulator-name = "vdda"; 126 regulator-min-microvolt = <2900000>; 127 regulator-max-microvolt = <2900000>; 128 }; 129 130 v2v8: ldo2 { 131 regulator-name = "v2v8"; 132 regulator-min-microvolt = <2800000>; 133 regulator-max-microvolt = <2800000>; 134 }; 135 136 vtt_ddr: ldo3 { 137 regulator-name = "vtt_ddr"; 138 regulator-always-on; 139 regulator-over-current-protection; 140 st,regulator-sink-source; 141 }; 142 143 vdd_usb: ldo4 { 144 regulator-name = "vdd_usb"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 }; 148 149 vdd_sd: ldo5 { 150 regulator-name = "vdd_sd"; 151 regulator-min-microvolt = <2900000>; 152 regulator-max-microvolt = <2900000>; 153 regulator-boot-on; 154 }; 155 156 v1v8: ldo6 { 157 regulator-name = "v1v8"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 }; 161 162 vref_ddr: vref_ddr { 163 regulator-name = "vref_ddr"; 164 regulator-always-on; 165 }; 166 167 bst_out: boost { 168 regulator-name = "bst_out"; 169 }; 170 171 vbus_otg: pwr_sw1 { 172 regulator-name = "vbus_otg"; 173 }; 174 175 vbus_sw: pwr_sw2 { 176 regulator-name = "vbus_sw"; 177 regulator-active-discharge = <1>; 178 }; 179 }; 180 181 onkey { 182 compatible = "st,stpmic1-onkey"; 183 power-off-time-sec = <10>; 184 status = "okay"; 185 }; 186 187 watchdog { 188 compatible = "st,stpmic1-wdt"; 189 status = "disabled"; 190 }; 191 }; 192}; 193 194&iwdg2 { 195 timeout-sec = <32>; 196 status = "okay"; 197}; 198 199&nvmem_layout { 200 nvmem-cells = <&cfg0_otp>, 201 <&part_number_otp>, 202 <&monotonic_otp>, 203 <&nand_otp>, 204 <&uid_otp>, 205 <&package_otp>, 206 <&hw2_otp>, 207 <&board_id>; 208 209 nvmem-cell-names = "cfg0_otp", 210 "part_number_otp", 211 "monotonic_otp", 212 "nand_otp", 213 "uid_otp", 214 "package_otp", 215 "hw2_otp", 216 "board_id"; 217}; 218 219&pwr_regulators { 220 vdd-supply = <&vdd>; 221 vdd_3v3_usbfs-supply = <&vdd_usb>; 222}; 223 224&rcc { 225 secure-status = "disabled"; 226 st,clksrc = < 227 CLK_MPU_PLL1P 228 CLK_AXI_PLL2P 229 CLK_MCU_PLL3P 230 CLK_PLL12_HSE 231 CLK_PLL3_HSE 232 CLK_PLL4_HSE 233 CLK_RTC_LSE 234 CLK_MCO1_DISABLED 235 CLK_MCO2_DISABLED 236 >; 237 238 st,clkdiv = < 239 1 /*MPU*/ 240 0 /*AXI*/ 241 0 /*MCU*/ 242 1 /*APB1*/ 243 1 /*APB2*/ 244 1 /*APB3*/ 245 1 /*APB4*/ 246 2 /*APB5*/ 247 23 /*RTC*/ 248 0 /*MCO1*/ 249 0 /*MCO2*/ 250 >; 251 252 st,pkcs = < 253 CLK_CKPER_HSE 254 CLK_FMC_ACLK 255 CLK_QSPI_ACLK 256 CLK_ETH_PLL4P 257 CLK_SDMMC12_PLL4P 258 CLK_DSI_DSIPLL 259 CLK_STGEN_HSE 260 CLK_USBPHY_HSE 261 CLK_SPI2S1_PLL3Q 262 CLK_SPI2S23_PLL3Q 263 CLK_SPI45_HSI 264 CLK_SPI6_HSI 265 CLK_I2C46_HSI 266 CLK_SDMMC3_PLL4P 267 CLK_USBO_USBPHY 268 CLK_ADC_CKPER 269 CLK_CEC_LSE 270 CLK_I2C12_HSI 271 CLK_I2C35_HSI 272 CLK_UART1_HSI 273 CLK_UART24_HSI 274 CLK_UART35_HSI 275 CLK_UART6_HSI 276 CLK_UART78_HSI 277 CLK_SPDIF_PLL4P 278 CLK_FDCAN_PLL4R 279 CLK_SAI1_PLL3Q 280 CLK_SAI2_PLL3Q 281 CLK_SAI3_PLL3Q 282 CLK_SAI4_PLL3Q 283 CLK_RNG1_LSI 284 CLK_RNG2_LSI 285 CLK_LPTIM1_PCLK1 286 CLK_LPTIM23_PCLK3 287 CLK_LPTIM45_LSE 288 >; 289 290 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 291 pll1: st,pll@0 { 292 compatible = "st,stm32mp1-pll"; 293 reg = <0>; 294 cfg = <2 80 0 0 0 PQR(1,0,0)>; 295 frac = <0x800>; 296 }; 297 298 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 299 pll2: st,pll@1 { 300 compatible = "st,stm32mp1-pll"; 301 reg = <1>; 302 cfg = <2 65 1 0 0 PQR(1,1,1)>; 303 frac = <0x1400>; 304 }; 305 306 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 307 pll3: st,pll@2 { 308 compatible = "st,stm32mp1-pll"; 309 reg = <2>; 310 cfg = <1 33 1 16 36 PQR(1,1,1)>; 311 frac = <0x1a04>; 312 }; 313 314 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 315 pll4: st,pll@3 { 316 compatible = "st,stm32mp1-pll"; 317 reg = <3>; 318 cfg = <3 98 5 7 7 PQR(1,1,1)>; 319 }; 320}; 321 322&rng1 { 323 status = "okay"; 324}; 325 326&rtc { 327 status = "okay"; 328}; 329 330&sdmmc1 { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 333 disable-wp; 334 st,sig-dir; 335 st,neg-edge; 336 st,use-ckin; 337 bus-width = <4>; 338 vmmc-supply = <&vdd_sd>; 339 sd-uhs-sdr12; 340 sd-uhs-sdr25; 341 sd-uhs-sdr50; 342 sd-uhs-ddr50; 343 status = "okay"; 344}; 345 346&sdmmc2 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 349 non-removable; 350 no-sd; 351 no-sdio; 352 st,neg-edge; 353 bus-width = <8>; 354 vmmc-supply = <&v3v3>; 355 vqmmc-supply = <&vdd>; 356 mmc-ddr-3_3v; 357 status = "okay"; 358}; 359 360&uart4 { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&uart4_pins_a>; 363 status = "okay"; 364}; 365