1 /* 2 * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <drivers/st/regulator.h> 13 #include <drivers/st/stm32_i2c.h> 14 #include <drivers/st/stm32mp_pmic.h> 15 #include <drivers/st/stpmic1.h> 16 #include <lib/mmio.h> 17 #include <lib/utils_def.h> 18 #include <libfdt.h> 19 20 #include <platform_def.h> 21 22 #define PMIC_NODE_NOT_FOUND 1 23 #define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2)) 24 #define STPMIC1_LDO12356_OUTPUT_SHIFT 2 25 #define STPMIC1_LDO3_MODE (uint8_t)(BIT(7)) 26 #define STPMIC1_LDO3_DDR_SEL 31U 27 #define STPMIC1_LDO3_1800000 (9U << STPMIC1_LDO12356_OUTPUT_SHIFT) 28 29 #define STPMIC1_BUCK_OUTPUT_SHIFT 2 30 #define STPMIC1_BUCK3_1V8 (39U << STPMIC1_BUCK_OUTPUT_SHIFT) 31 32 #define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 33 34 static struct i2c_handle_s i2c_handle; 35 static uint32_t pmic_i2c_addr; 36 37 static int register_pmic(void); 38 39 static int dt_get_pmic_node(void *fdt) 40 { 41 static int node = -FDT_ERR_BADOFFSET; 42 43 if (node == -FDT_ERR_BADOFFSET) { 44 node = fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1"); 45 } 46 47 return node; 48 } 49 50 int dt_pmic_status(void) 51 { 52 static int status = -FDT_ERR_BADVALUE; 53 int node; 54 void *fdt; 55 56 if (status != -FDT_ERR_BADVALUE) { 57 return status; 58 } 59 60 if (fdt_get_address(&fdt) == 0) { 61 return -ENOENT; 62 } 63 64 node = dt_get_pmic_node(fdt); 65 if (node <= 0) { 66 status = -FDT_ERR_NOTFOUND; 67 68 return status; 69 } 70 71 status = (int)fdt_get_status(node); 72 73 return status; 74 } 75 76 static bool dt_pmic_is_secure(void) 77 { 78 int status = dt_pmic_status(); 79 80 return (status >= 0) && 81 (status == DT_SECURE) && 82 (i2c_handle.dt_status == DT_SECURE); 83 } 84 85 /* 86 * Get PMIC and its I2C bus configuration from the device tree. 87 * Return 0 on success, negative on error, 1 if no PMIC node is defined. 88 */ 89 static int dt_pmic_i2c_config(struct dt_node_info *i2c_info, 90 struct stm32_i2c_init_s *init) 91 { 92 static int i2c_node = -FDT_ERR_NOTFOUND; 93 void *fdt; 94 95 if (fdt_get_address(&fdt) == 0) { 96 return -FDT_ERR_NOTFOUND; 97 } 98 99 if (i2c_node == -FDT_ERR_NOTFOUND) { 100 int pmic_node; 101 const fdt32_t *cuint; 102 103 pmic_node = dt_get_pmic_node(fdt); 104 if (pmic_node < 0) { 105 return PMIC_NODE_NOT_FOUND; 106 } 107 108 cuint = fdt_getprop(fdt, pmic_node, "reg", NULL); 109 if (cuint == NULL) { 110 return -FDT_ERR_NOTFOUND; 111 } 112 113 pmic_i2c_addr = fdt32_to_cpu(*cuint) << 1; 114 if (pmic_i2c_addr > UINT16_MAX) { 115 return -FDT_ERR_BADVALUE; 116 } 117 118 i2c_node = fdt_parent_offset(fdt, pmic_node); 119 if (i2c_node < 0) { 120 return -FDT_ERR_NOTFOUND; 121 } 122 } 123 124 dt_fill_device_info(i2c_info, i2c_node); 125 if (i2c_info->base == 0U) { 126 return -FDT_ERR_NOTFOUND; 127 } 128 129 return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init); 130 } 131 132 bool initialize_pmic_i2c(void) 133 { 134 int ret; 135 struct dt_node_info i2c_info; 136 struct i2c_handle_s *i2c = &i2c_handle; 137 struct stm32_i2c_init_s i2c_init; 138 139 ret = dt_pmic_i2c_config(&i2c_info, &i2c_init); 140 if (ret < 0) { 141 ERROR("I2C configuration failed %d\n", ret); 142 panic(); 143 } 144 145 if (ret != 0) { 146 return false; 147 } 148 149 /* Initialize PMIC I2C */ 150 i2c->i2c_base_addr = i2c_info.base; 151 i2c->dt_status = i2c_info.status; 152 i2c->clock = i2c_info.clock; 153 i2c->i2c_state = I2C_STATE_RESET; 154 i2c_init.own_address1 = pmic_i2c_addr; 155 i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT; 156 i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE; 157 i2c_init.own_address2 = 0; 158 i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK; 159 i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE; 160 i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE; 161 i2c_init.analog_filter = 1; 162 i2c_init.digital_filter_coef = 0; 163 164 ret = stm32_i2c_init(i2c, &i2c_init); 165 if (ret != 0) { 166 ERROR("Cannot initialize I2C %x (%d)\n", 167 i2c->i2c_base_addr, ret); 168 panic(); 169 } 170 171 if (!stm32_i2c_is_device_ready(i2c, pmic_i2c_addr, 1, 172 I2C_TIMEOUT_BUSY_MS)) { 173 ERROR("I2C device not ready\n"); 174 panic(); 175 } 176 177 stpmic1_bind_i2c(i2c, (uint16_t)pmic_i2c_addr); 178 179 return true; 180 } 181 182 static void register_pmic_shared_peripherals(void) 183 { 184 uintptr_t i2c_base = i2c_handle.i2c_base_addr; 185 186 if (dt_pmic_is_secure()) { 187 stm32mp_register_secure_periph_iomem(i2c_base); 188 } else { 189 if (i2c_base != 0U) { 190 stm32mp_register_non_secure_periph_iomem(i2c_base); 191 } 192 } 193 } 194 195 void initialize_pmic(void) 196 { 197 if (!initialize_pmic_i2c()) { 198 VERBOSE("No PMIC\n"); 199 return; 200 } 201 202 register_pmic_shared_peripherals(); 203 204 if (register_pmic() < 0) { 205 panic(); 206 } 207 208 if (stpmic1_powerctrl_on() < 0) { 209 panic(); 210 } 211 212 } 213 214 #if DEBUG 215 void print_pmic_info_and_debug(void) 216 { 217 unsigned long pmic_version; 218 219 if (stpmic1_get_version(&pmic_version) != 0) { 220 ERROR("Failed to access PMIC\n"); 221 panic(); 222 } 223 224 INFO("PMIC version = 0x%02lx\n", pmic_version); 225 } 226 #endif 227 228 int pmic_ddr_power_init(enum ddr_type ddr_type) 229 { 230 bool buck3_at_1v8 = false; 231 uint8_t read_val; 232 int status; 233 234 switch (ddr_type) { 235 case STM32MP_DDR3: 236 /* Set LDO3 to sync mode */ 237 status = stpmic1_register_read(LDO3_CONTROL_REG, &read_val); 238 if (status != 0) { 239 return status; 240 } 241 242 read_val &= ~STPMIC1_LDO3_MODE; 243 read_val &= ~STPMIC1_LDO12356_OUTPUT_MASK; 244 read_val |= STPMIC1_LDO3_DDR_SEL << 245 STPMIC1_LDO12356_OUTPUT_SHIFT; 246 247 status = stpmic1_register_write(LDO3_CONTROL_REG, read_val); 248 if (status != 0) { 249 return status; 250 } 251 252 status = stpmic1_regulator_voltage_set("buck2", 1350); 253 if (status != 0) { 254 return status; 255 } 256 257 status = stpmic1_regulator_enable("buck2"); 258 if (status != 0) { 259 return status; 260 } 261 262 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 263 264 status = stpmic1_regulator_enable("vref_ddr"); 265 if (status != 0) { 266 return status; 267 } 268 269 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 270 271 status = stpmic1_regulator_enable("ldo3"); 272 if (status != 0) { 273 return status; 274 } 275 276 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 277 break; 278 279 case STM32MP_LPDDR2: 280 case STM32MP_LPDDR3: 281 /* 282 * Set LDO3 to 1.8V 283 * Set LDO3 to bypass mode if BUCK3 = 1.8V 284 * Set LDO3 to normal mode if BUCK3 != 1.8V 285 */ 286 status = stpmic1_register_read(BUCK3_CONTROL_REG, &read_val); 287 if (status != 0) { 288 return status; 289 } 290 291 if ((read_val & STPMIC1_BUCK3_1V8) == STPMIC1_BUCK3_1V8) { 292 buck3_at_1v8 = true; 293 } 294 295 status = stpmic1_register_read(LDO3_CONTROL_REG, &read_val); 296 if (status != 0) { 297 return status; 298 } 299 300 read_val &= ~STPMIC1_LDO3_MODE; 301 read_val &= ~STPMIC1_LDO12356_OUTPUT_MASK; 302 read_val |= STPMIC1_LDO3_1800000; 303 if (buck3_at_1v8) { 304 read_val |= STPMIC1_LDO3_MODE; 305 } 306 307 status = stpmic1_register_write(LDO3_CONTROL_REG, read_val); 308 if (status != 0) { 309 return status; 310 } 311 312 status = stpmic1_regulator_voltage_set("buck2", 1200); 313 if (status != 0) { 314 return status; 315 } 316 317 status = stpmic1_regulator_enable("ldo3"); 318 if (status != 0) { 319 return status; 320 } 321 322 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 323 324 status = stpmic1_regulator_enable("buck2"); 325 if (status != 0) { 326 return status; 327 } 328 329 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 330 331 status = stpmic1_regulator_enable("vref_ddr"); 332 if (status != 0) { 333 return status; 334 } 335 336 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); 337 break; 338 339 default: 340 break; 341 }; 342 343 return 0; 344 } 345 346 enum { 347 STPMIC1_BUCK1 = 0, 348 STPMIC1_BUCK2, 349 STPMIC1_BUCK3, 350 STPMIC1_BUCK4, 351 STPMIC1_LDO1, 352 STPMIC1_LDO2, 353 STPMIC1_LDO3, 354 STPMIC1_LDO4, 355 STPMIC1_LDO5, 356 STPMIC1_LDO6, 357 STPMIC1_VREF_DDR, 358 STPMIC1_BOOST, 359 STPMIC1_VBUS_OTG, 360 STPMIC1_SW_OUT, 361 }; 362 363 static int pmic_set_state(const struct regul_description *desc, bool enable) 364 { 365 VERBOSE("%s: set state to %u\n", desc->node_name, enable); 366 367 if (enable == STATE_ENABLE) { 368 return stpmic1_regulator_enable(desc->node_name); 369 } else { 370 return stpmic1_regulator_disable(desc->node_name); 371 } 372 } 373 374 static int pmic_get_state(const struct regul_description *desc) 375 { 376 VERBOSE("%s: get state\n", desc->node_name); 377 378 return stpmic1_is_regulator_enabled(desc->node_name); 379 } 380 381 static int pmic_get_voltage(const struct regul_description *desc) 382 { 383 VERBOSE("%s: get volt\n", desc->node_name); 384 385 return stpmic1_regulator_voltage_get(desc->node_name); 386 } 387 388 static int pmic_set_voltage(const struct regul_description *desc, uint16_t mv) 389 { 390 VERBOSE("%s: get volt\n", desc->node_name); 391 392 return stpmic1_regulator_voltage_set(desc->node_name, mv); 393 } 394 395 static int pmic_list_voltages(const struct regul_description *desc, 396 const uint16_t **levels, size_t *count) 397 { 398 VERBOSE("%s: list volt\n", desc->node_name); 399 400 return stpmic1_regulator_levels_mv(desc->node_name, levels, count); 401 } 402 403 static int pmic_set_flag(const struct regul_description *desc, uint16_t flag) 404 { 405 VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag); 406 407 switch (flag) { 408 case REGUL_OCP: 409 return stpmic1_regulator_icc_set(desc->node_name); 410 411 case REGUL_ACTIVE_DISCHARGE: 412 return stpmic1_active_discharge_mode_set(desc->node_name); 413 414 case REGUL_PULL_DOWN: 415 return stpmic1_regulator_pull_down_set(desc->node_name); 416 417 case REGUL_MASK_RESET: 418 return stpmic1_regulator_mask_reset_set(desc->node_name); 419 420 case REGUL_SINK_SOURCE: 421 return stpmic1_regulator_sink_mode_set(desc->node_name); 422 423 case REGUL_ENABLE_BYPASS: 424 return stpmic1_regulator_bypass_mode_set(desc->node_name); 425 426 default: 427 return -EINVAL; 428 } 429 } 430 431 struct regul_ops pmic_ops = { 432 .set_state = pmic_set_state, 433 .get_state = pmic_get_state, 434 .set_voltage = pmic_set_voltage, 435 .get_voltage = pmic_get_voltage, 436 .list_voltages = pmic_list_voltages, 437 .set_flag = pmic_set_flag, 438 }; 439 440 #define DEFINE_REGU(name) { \ 441 .node_name = name, \ 442 .ops = &pmic_ops, \ 443 .driver_data = NULL, \ 444 .enable_ramp_delay = 1000, \ 445 } 446 447 static const struct regul_description pmic_regs[] = { 448 [STPMIC1_BUCK1] = DEFINE_REGU("buck1"), 449 [STPMIC1_BUCK2] = DEFINE_REGU("buck2"), 450 [STPMIC1_BUCK3] = DEFINE_REGU("buck3"), 451 [STPMIC1_BUCK4] = DEFINE_REGU("buck4"), 452 [STPMIC1_LDO1] = DEFINE_REGU("ldo1"), 453 [STPMIC1_LDO2] = DEFINE_REGU("ldo2"), 454 [STPMIC1_LDO3] = DEFINE_REGU("ldo3"), 455 [STPMIC1_LDO4] = DEFINE_REGU("ldo4"), 456 [STPMIC1_LDO5] = DEFINE_REGU("ldo5"), 457 [STPMIC1_LDO6] = DEFINE_REGU("ldo6"), 458 [STPMIC1_VREF_DDR] = DEFINE_REGU("vref_ddr"), 459 [STPMIC1_BOOST] = DEFINE_REGU("boost"), 460 [STPMIC1_VBUS_OTG] = DEFINE_REGU("pwr_sw1"), 461 [STPMIC1_SW_OUT] = DEFINE_REGU("pwr_sw2"), 462 }; 463 464 #define NB_REG ARRAY_SIZE(pmic_regs) 465 466 static int register_pmic(void) 467 { 468 void *fdt; 469 int pmic_node, regulators_node, subnode; 470 471 VERBOSE("Register pmic\n"); 472 473 if (fdt_get_address(&fdt) == 0) { 474 return -FDT_ERR_NOTFOUND; 475 } 476 477 pmic_node = dt_get_pmic_node(fdt); 478 if (pmic_node < 0) { 479 return pmic_node; 480 } 481 482 regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators"); 483 if (regulators_node < 0) { 484 return -ENOENT; 485 } 486 487 fdt_for_each_subnode(subnode, fdt, regulators_node) { 488 const char *reg_name = fdt_get_name(fdt, subnode, NULL); 489 const struct regul_description *desc; 490 unsigned int i; 491 int ret; 492 493 for (i = 0; i < NB_REG; i++) { 494 desc = &pmic_regs[i]; 495 if (strcmp(desc->node_name, reg_name) == 0) { 496 break; 497 } 498 } 499 assert(i < NB_REG); 500 501 ret = regulator_register(desc, subnode); 502 if (ret != 0) { 503 WARN("%s:%d failed to register %s\n", __func__, 504 __LINE__, reg_name); 505 return ret; 506 } 507 } 508 509 return 0; 510 } 511