1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/stm32_iwdg.h> 19 #include <drivers/st/stm32_uart.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_pwr.h> 22 #include <drivers/st/stm32mp1_ram.h> 23 #include <drivers/st/stm32mp_pmic.h> 24 #include <lib/fconf/fconf.h> 25 #include <lib/fconf/fconf_dyn_cfg_getter.h> 26 #include <lib/mmio.h> 27 #include <lib/optee_utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <platform_def.h> 32 #include <stm32mp1_dbgmcu.h> 33 34 static struct stm32mp_auth_ops stm32mp1_auth_ops; 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 39 40 if (rstsr == 0U) { 41 WARN("Reset reason unknown\n"); 42 return; 43 } 44 45 INFO("Reset reason (0x%x):\n", rstsr); 46 47 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 49 INFO("System exits from STANDBY\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 54 INFO("MPU exits from CSTANDBY\n"); 55 return; 56 } 57 } 58 59 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 60 INFO(" Power-on Reset (rst_por)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 65 INFO(" Brownout Reset (rst_bor)\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 70 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 71 INFO(" System reset generated by MCU (MCSYSRST)\n"); 72 } else { 73 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 74 } 75 return; 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 79 INFO(" System reset generated by MPU (MPSYSRST)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 84 INFO(" Reset due to a clock failure on HSE\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 89 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 94 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 99 INFO(" MPU Processor 0 Reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 104 INFO(" MPU Processor 1 Reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp_save_boot_ctx_address(arg0); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 int ret; 132 133 ret = stm32mp1_ddr_probe(); 134 if (ret < 0) { 135 ERROR("Invalid DDR init: error %d\n", ret); 136 panic(); 137 } 138 139 /* Map DDR for binary load, now with cacheable attribute */ 140 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 141 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 142 if (ret < 0) { 143 ERROR("DDR mapping: error %d\n", ret); 144 panic(); 145 } 146 147 #if STM32MP_USE_STM32IMAGE 148 #ifdef AARCH32_SP_OPTEE 149 INFO("BL2 runs OP-TEE setup\n"); 150 #else 151 INFO("BL2 runs SP_MIN setup\n"); 152 #endif 153 #endif /* STM32MP_USE_STM32IMAGE */ 154 } 155 156 void bl2_el3_plat_arch_setup(void) 157 { 158 int32_t result; 159 const char *board_model; 160 boot_api_context_t *boot_context = 161 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 162 uintptr_t pwr_base; 163 uintptr_t rcc_base; 164 165 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 166 BL_CODE_END - BL_CODE_BASE, 167 MT_CODE | MT_SECURE); 168 169 #if STM32MP_USE_STM32IMAGE 170 #ifdef AARCH32_SP_OPTEE 171 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 172 STM32MP_OPTEE_SIZE, 173 MT_MEMORY | MT_RW | MT_SECURE); 174 #else 175 /* Prevent corruption of preloaded BL32 */ 176 mmap_add_region(BL32_BASE, BL32_BASE, 177 BL32_LIMIT - BL32_BASE, 178 MT_RO_DATA | MT_SECURE); 179 #endif 180 #endif /* STM32MP_USE_STM32IMAGE */ 181 182 /* Prevent corruption of preloaded Device Tree */ 183 mmap_add_region(DTB_BASE, DTB_BASE, 184 DTB_LIMIT - DTB_BASE, 185 MT_RO_DATA | MT_SECURE); 186 187 configure_mmu(); 188 189 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 190 panic(); 191 } 192 193 pwr_base = stm32mp_pwr_base(); 194 rcc_base = stm32mp_rcc_base(); 195 196 /* 197 * Disable the backup domain write protection. 198 * The protection is enable at each reset by hardware 199 * and must be disabled by software. 200 */ 201 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 202 203 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 204 ; 205 } 206 207 if (bsec_probe() != 0) { 208 panic(); 209 } 210 211 /* Reset backup domain on cold boot cases */ 212 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 213 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 214 215 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 216 0U) { 217 ; 218 } 219 220 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 221 } 222 223 /* Disable MCKPROT */ 224 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 225 226 generic_delay_timer_init(); 227 228 #if STM32MP_UART_PROGRAMMER 229 /* Disable programmer UART before changing clock tree */ 230 if (boot_context->boot_interface_selected == 231 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 232 uintptr_t uart_prog_addr = 233 get_uart_address(boot_context->boot_interface_instance); 234 235 stm32_uart_stop(uart_prog_addr); 236 } 237 #endif 238 if (stm32mp1_clk_probe() < 0) { 239 panic(); 240 } 241 242 if (stm32mp1_clk_init() < 0) { 243 panic(); 244 } 245 246 stm32_save_boot_interface(boot_context->boot_interface_selected, 247 boot_context->boot_interface_instance); 248 249 #if STM32MP_USB_PROGRAMMER 250 /* Deconfigure all UART RX pins configured by ROM code */ 251 stm32mp1_deconfigure_uart_pins(); 252 #endif 253 254 if (stm32mp_uart_console_setup() != 0) { 255 goto skip_console_init; 256 } 257 258 stm32mp_print_cpuinfo(); 259 260 board_model = dt_get_board_model(); 261 if (board_model != NULL) { 262 NOTICE("Model: %s\n", board_model); 263 } 264 265 stm32mp_print_boardinfo(); 266 267 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 268 NOTICE("Bootrom authentication %s\n", 269 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 270 "failed" : "succeeded"); 271 } 272 273 skip_console_init: 274 if (dt_pmic_status() > 0) { 275 initialize_pmic(); 276 print_pmic_info_and_debug(); 277 } 278 279 stm32mp1_syscfg_init(); 280 281 if (stm32_iwdg_init() < 0) { 282 panic(); 283 } 284 285 stm32_iwdg_refresh(); 286 287 result = stm32mp1_dbgmcu_freeze_iwdg2(); 288 if (result != 0) { 289 INFO("IWDG2 freeze error : %i\n", result); 290 } 291 292 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 293 stm32mp1_auth_ops.verify_signature = 294 boot_context->bootrom_ecdsa_verify_signature; 295 296 stm32mp_init_auth(&stm32mp1_auth_ops); 297 298 stm32mp1_arch_security_setup(); 299 300 print_reset_reason(); 301 302 #if !STM32MP_USE_STM32IMAGE 303 fconf_populate("TB_FW", STM32MP_DTB_BASE); 304 #endif /* !STM32MP_USE_STM32IMAGE */ 305 306 stm32mp_io_setup(); 307 } 308 309 /******************************************************************************* 310 * This function can be used by the platforms to update/use image 311 * information for given `image_id`. 312 ******************************************************************************/ 313 int bl2_plat_handle_post_image_load(unsigned int image_id) 314 { 315 int err = 0; 316 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 317 bl_mem_params_node_t *bl32_mem_params; 318 bl_mem_params_node_t *pager_mem_params __unused; 319 bl_mem_params_node_t *paged_mem_params __unused; 320 #if !STM32MP_USE_STM32IMAGE 321 const struct dyn_cfg_dtb_info_t *config_info; 322 bl_mem_params_node_t *tos_fw_mem_params; 323 unsigned int i; 324 unsigned int idx; 325 unsigned long long ddr_top __unused; 326 const unsigned int image_ids[] = { 327 BL32_IMAGE_ID, 328 BL33_IMAGE_ID, 329 HW_CONFIG_ID, 330 TOS_FW_CONFIG_ID, 331 }; 332 #endif /* !STM32MP_USE_STM32IMAGE */ 333 334 assert(bl_mem_params != NULL); 335 336 switch (image_id) { 337 #if !STM32MP_USE_STM32IMAGE 338 case FW_CONFIG_ID: 339 /* Set global DTB info for fixed fw_config information */ 340 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 341 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 342 343 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 344 345 /* Iterate through all the fw config IDs */ 346 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 347 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 348 continue; 349 } 350 351 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 352 assert(bl_mem_params != NULL); 353 354 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 355 if (config_info == NULL) { 356 continue; 357 } 358 359 bl_mem_params->image_info.image_base = config_info->config_addr; 360 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 361 362 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 363 364 switch (image_ids[i]) { 365 case BL32_IMAGE_ID: 366 bl_mem_params->ep_info.pc = config_info->config_addr; 367 368 /* In case of OPTEE, initialize address space with tos_fw addr */ 369 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 370 pager_mem_params->image_info.image_base = config_info->config_addr; 371 pager_mem_params->image_info.image_max_size = 372 config_info->config_max_size; 373 374 /* Init base and size for pager if exist */ 375 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 376 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 377 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 378 STM32MP_DDR_SHMEM_SIZE); 379 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 380 break; 381 382 case BL33_IMAGE_ID: 383 bl_mem_params->ep_info.pc = config_info->config_addr; 384 break; 385 386 case HW_CONFIG_ID: 387 case TOS_FW_CONFIG_ID: 388 break; 389 390 default: 391 return -EINVAL; 392 } 393 } 394 break; 395 #endif /* !STM32MP_USE_STM32IMAGE */ 396 397 case BL32_IMAGE_ID: 398 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 399 /* BL32 is OP-TEE header */ 400 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 401 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 402 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 403 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 404 405 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 406 /* Set OP-TEE extra image load areas at run-time */ 407 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 408 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 409 410 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 411 dt_get_ddr_size() - 412 STM32MP_DDR_S_SIZE - 413 STM32MP_DDR_SHMEM_SIZE; 414 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 415 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 416 417 err = parse_optee_header(&bl_mem_params->ep_info, 418 &pager_mem_params->image_info, 419 &paged_mem_params->image_info); 420 if (err) { 421 ERROR("OPTEE header parse error.\n"); 422 panic(); 423 } 424 425 /* Set optee boot info from parsed header data */ 426 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 427 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 428 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 429 } else { 430 #if !STM32MP_USE_STM32IMAGE 431 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 432 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 433 bl_mem_params->image_info.image_max_size += 434 tos_fw_mem_params->image_info.image_max_size; 435 #endif /* !STM32MP_USE_STM32IMAGE */ 436 bl_mem_params->ep_info.args.arg0 = 0; 437 } 438 break; 439 440 case BL33_IMAGE_ID: 441 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 442 assert(bl32_mem_params != NULL); 443 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 444 break; 445 446 default: 447 /* Do nothing in default case */ 448 break; 449 } 450 451 #if STM32MP_SDMMC || STM32MP_EMMC 452 /* 453 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 454 * We take the worst case which is 2 MMC blocks. 455 */ 456 if ((image_id != FW_CONFIG_ID) && 457 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 458 inv_dcache_range(bl_mem_params->image_info.image_base + 459 bl_mem_params->image_info.image_size, 460 2U * MMC_BLOCK_SIZE); 461 } 462 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 463 464 return err; 465 } 466 467 void bl2_el3_plat_prepare_exit(void) 468 { 469 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 470 471 switch (boot_itf) { 472 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 473 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 474 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 475 /* Invalidate the downloaded buffer used with io_memmap */ 476 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 477 break; 478 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 479 default: 480 /* Do nothing in default case */ 481 break; 482 } 483 484 stm32mp1_security_setup(); 485 } 486