1 /* 2 * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdbool.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <lib/mmio.h> 20 #include <lib/utils_def.h> 21 22 #define DT_GPIO_BANK_SHIFT 12 23 #define DT_GPIO_BANK_MASK GENMASK(16, 12) 24 #define DT_GPIO_PIN_SHIFT 8 25 #define DT_GPIO_PIN_MASK GENMASK(11, 8) 26 #define DT_GPIO_MODE_MASK GENMASK(7, 0) 27 28 /******************************************************************************* 29 * This function gets GPIO bank node in DT. 30 * Returns node offset if status is okay in DT, else return 0 31 ******************************************************************************/ 32 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 33 { 34 int pinctrl_subnode; 35 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); 36 37 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 38 const fdt32_t *cuint; 39 40 if (fdt_getprop(fdt, pinctrl_subnode, 41 "gpio-controller", NULL) == NULL) { 42 continue; 43 } 44 45 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 46 if (cuint == NULL) { 47 continue; 48 } 49 50 if ((fdt32_to_cpu(*cuint) == bank_offset) && 51 (fdt_get_status(pinctrl_subnode) != DT_DISABLED)) { 52 return pinctrl_subnode; 53 } 54 } 55 56 return 0; 57 } 58 59 /******************************************************************************* 60 * This function gets the pin settings from DT information. 61 * When analyze and parsing is done, set the GPIO registers. 62 * Returns 0 on success and a negative FDT error code on failure. 63 ******************************************************************************/ 64 static int dt_set_gpio_config(void *fdt, int node, uint8_t status) 65 { 66 const fdt32_t *cuint, *slewrate; 67 int len; 68 int pinctrl_node; 69 uint32_t i; 70 uint32_t speed = GPIO_SPEED_LOW; 71 uint32_t pull = GPIO_NO_PULL; 72 73 cuint = fdt_getprop(fdt, node, "pinmux", &len); 74 if (cuint == NULL) { 75 return -FDT_ERR_NOTFOUND; 76 } 77 78 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 79 if (pinctrl_node < 0) { 80 return -FDT_ERR_NOTFOUND; 81 } 82 83 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 84 if (slewrate != NULL) { 85 speed = fdt32_to_cpu(*slewrate); 86 } 87 88 if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) { 89 pull = GPIO_PULL_UP; 90 } else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) { 91 pull = GPIO_PULL_DOWN; 92 } else { 93 VERBOSE("No bias configured in node %d\n", node); 94 } 95 96 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 97 uint32_t pincfg; 98 uint32_t bank; 99 uint32_t pin; 100 uint32_t mode; 101 uint32_t alternate = GPIO_ALTERNATE_(0); 102 int bank_node; 103 int clk; 104 105 pincfg = fdt32_to_cpu(*cuint); 106 cuint++; 107 108 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 109 110 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 111 112 mode = pincfg & DT_GPIO_MODE_MASK; 113 114 switch (mode) { 115 case 0: 116 mode = GPIO_MODE_INPUT; 117 break; 118 case 1 ... 16: 119 alternate = mode - 1U; 120 mode = GPIO_MODE_ALTERNATE; 121 break; 122 case 17: 123 mode = GPIO_MODE_ANALOG; 124 break; 125 default: 126 mode = GPIO_MODE_OUTPUT; 127 break; 128 } 129 130 if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) { 131 mode |= GPIO_OPEN_DRAIN; 132 } 133 134 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); 135 if (bank_node == 0) { 136 ERROR("PINCTRL inconsistent in DT\n"); 137 panic(); 138 } 139 140 clk = fdt_get_clock_id(bank_node); 141 if (clk < 0) { 142 return -FDT_ERR_NOTFOUND; 143 } 144 145 /* Platform knows the clock: assert it is okay */ 146 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); 147 148 set_gpio(bank, pin, mode, speed, pull, alternate, status); 149 } 150 151 return 0; 152 } 153 154 /******************************************************************************* 155 * This function gets the pin settings from DT information. 156 * When analyze and parsing is done, set the GPIO registers. 157 * Returns 0 on success and a negative FDT/ERRNO error code on failure. 158 ******************************************************************************/ 159 int dt_set_pinctrl_config(int node) 160 { 161 const fdt32_t *cuint; 162 int lenp = 0; 163 uint32_t i; 164 uint8_t status; 165 void *fdt; 166 167 if (fdt_get_address(&fdt) == 0) { 168 return -FDT_ERR_NOTFOUND; 169 } 170 171 status = fdt_get_status(node); 172 if (status == DT_DISABLED) { 173 return -FDT_ERR_NOTFOUND; 174 } 175 176 cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp); 177 if (cuint == NULL) { 178 return -FDT_ERR_NOTFOUND; 179 } 180 181 for (i = 0; i < ((uint32_t)lenp / 4U); i++) { 182 int p_node, p_subnode; 183 184 p_node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 185 if (p_node < 0) { 186 return -FDT_ERR_NOTFOUND; 187 } 188 189 fdt_for_each_subnode(p_subnode, fdt, p_node) { 190 int ret = dt_set_gpio_config(fdt, p_subnode, status); 191 192 if (ret < 0) { 193 return ret; 194 } 195 } 196 197 cuint++; 198 } 199 200 return 0; 201 } 202 203 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, 204 uint32_t pull, uint32_t alternate, uint8_t status) 205 { 206 uintptr_t base = stm32_get_gpio_bank_base(bank); 207 unsigned long clock = stm32_get_gpio_bank_clock(bank); 208 209 assert(pin <= GPIO_PIN_MAX); 210 211 stm32mp_clk_enable(clock); 212 213 mmio_clrbits_32(base + GPIO_MODE_OFFSET, 214 ((uint32_t)GPIO_MODE_MASK << (pin << 1))); 215 mmio_setbits_32(base + GPIO_MODE_OFFSET, 216 (mode & ~GPIO_OPEN_DRAIN) << (pin << 1)); 217 218 if ((mode & GPIO_OPEN_DRAIN) != 0U) { 219 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); 220 } else { 221 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); 222 } 223 224 mmio_clrbits_32(base + GPIO_SPEED_OFFSET, 225 ((uint32_t)GPIO_SPEED_MASK << (pin << 1))); 226 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); 227 228 mmio_clrbits_32(base + GPIO_PUPD_OFFSET, 229 ((uint32_t)GPIO_PULL_MASK << (pin << 1))); 230 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); 231 232 if (pin < GPIO_ALT_LOWER_LIMIT) { 233 mmio_clrbits_32(base + GPIO_AFRL_OFFSET, 234 ((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2))); 235 mmio_setbits_32(base + GPIO_AFRL_OFFSET, 236 alternate << (pin << 2)); 237 } else { 238 mmio_clrbits_32(base + GPIO_AFRH_OFFSET, 239 ((uint32_t)GPIO_ALTERNATE_MASK << 240 ((pin - GPIO_ALT_LOWER_LIMIT) << 2))); 241 mmio_setbits_32(base + GPIO_AFRH_OFFSET, 242 alternate << ((pin - GPIO_ALT_LOWER_LIMIT) << 243 2)); 244 } 245 246 VERBOSE("GPIO %u mode set to 0x%x\n", bank, 247 mmio_read_32(base + GPIO_MODE_OFFSET)); 248 VERBOSE("GPIO %u speed set to 0x%x\n", bank, 249 mmio_read_32(base + GPIO_SPEED_OFFSET)); 250 VERBOSE("GPIO %u mode pull to 0x%x\n", bank, 251 mmio_read_32(base + GPIO_PUPD_OFFSET)); 252 VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank, 253 mmio_read_32(base + GPIO_AFRL_OFFSET)); 254 VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, 255 mmio_read_32(base + GPIO_AFRH_OFFSET)); 256 257 stm32mp_clk_disable(clock); 258 259 if (status == DT_SECURE) { 260 stm32mp_register_secure_gpio(bank, pin); 261 set_gpio_secure_cfg(bank, pin, true); 262 263 } else { 264 stm32mp_register_non_secure_gpio(bank, pin); 265 set_gpio_secure_cfg(bank, pin, false); 266 } 267 } 268 269 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) 270 { 271 uintptr_t base = stm32_get_gpio_bank_base(bank); 272 unsigned long clock = stm32_get_gpio_bank_clock(bank); 273 274 assert(pin <= GPIO_PIN_MAX); 275 276 stm32mp_clk_enable(clock); 277 278 if (secure) { 279 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 280 } else { 281 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 282 } 283 284 stm32mp_clk_disable(clock); 285 } 286 287 void set_gpio_reset_cfg(uint32_t bank, uint32_t pin) 288 { 289 set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_SPEED_LOW, 290 GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED); 291 set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank)); 292 } 293