1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <drivers/st/stm32_iwdg.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARCPN_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 24 #define BOARD_ID_VARFG_SHIFT 4 25 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 26 27 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 28 BOARD_ID_BOARD_NB_SHIFT) 29 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 30 BOARD_ID_VARCPN_SHIFT) 31 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 32 BOARD_ID_REVISION_SHIFT) 33 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 34 BOARD_ID_VARFG_SHIFT) 35 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 36 37 #if defined(IMAGE_BL2) 38 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 39 STM32MP_SYSRAM_SIZE, \ 40 MT_MEMORY | \ 41 MT_RW | \ 42 MT_SECURE | \ 43 MT_EXECUTE_NEVER) 44 #elif defined(IMAGE_BL32) 45 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 46 STM32MP_SEC_SYSRAM_SIZE, \ 47 MT_MEMORY | \ 48 MT_RW | \ 49 MT_SECURE | \ 50 MT_EXECUTE_NEVER) 51 52 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 53 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 54 STM32MP_NS_SYSRAM_SIZE, \ 55 MT_DEVICE | \ 56 MT_RW | \ 57 MT_NS | \ 58 MT_EXECUTE_NEVER) 59 #endif 60 61 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 62 STM32MP1_DEVICE1_SIZE, \ 63 MT_DEVICE | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 68 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 69 STM32MP1_DEVICE2_SIZE, \ 70 MT_DEVICE | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 #if defined(IMAGE_BL2) 76 static const mmap_region_t stm32mp1_mmap[] = { 77 MAP_SEC_SYSRAM, 78 MAP_DEVICE1, 79 MAP_DEVICE2, 80 {0} 81 }; 82 #endif 83 #if defined(IMAGE_BL32) 84 static const mmap_region_t stm32mp1_mmap[] = { 85 MAP_SEC_SYSRAM, 86 MAP_NS_SYSRAM, 87 MAP_DEVICE1, 88 MAP_DEVICE2, 89 {0} 90 }; 91 #endif 92 93 void configure_mmu(void) 94 { 95 mmap_add(stm32mp1_mmap); 96 init_xlat_tables(); 97 98 enable_mmu_svc_mon(0); 99 } 100 101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 102 { 103 if (bank == GPIO_BANK_Z) { 104 return GPIOZ_BASE; 105 } 106 107 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 108 109 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 110 } 111 112 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 113 { 114 if (bank == GPIO_BANK_Z) { 115 return 0; 116 } 117 118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 119 120 return bank * GPIO_BANK_OFFSET; 121 } 122 123 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 124 { 125 if (bank == GPIO_BANK_Z) { 126 return true; 127 } 128 129 return false; 130 } 131 132 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 133 { 134 if (bank == GPIO_BANK_Z) { 135 return GPIOZ; 136 } 137 138 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 139 140 return GPIOA + (bank - GPIO_BANK_A); 141 } 142 143 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 144 { 145 switch (bank) { 146 case GPIO_BANK_A: 147 case GPIO_BANK_B: 148 case GPIO_BANK_C: 149 case GPIO_BANK_D: 150 case GPIO_BANK_E: 151 case GPIO_BANK_F: 152 case GPIO_BANK_G: 153 case GPIO_BANK_H: 154 case GPIO_BANK_I: 155 case GPIO_BANK_J: 156 case GPIO_BANK_K: 157 return fdt_path_offset(fdt, "/soc/pin-controller"); 158 case GPIO_BANK_Z: 159 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 160 default: 161 panic(); 162 } 163 } 164 165 #if STM32MP_UART_PROGRAMMER 166 /* 167 * UART Management 168 */ 169 static const uintptr_t stm32mp1_uart_addresses[8] = { 170 USART1_BASE, 171 USART2_BASE, 172 USART3_BASE, 173 UART4_BASE, 174 UART5_BASE, 175 USART6_BASE, 176 UART7_BASE, 177 UART8_BASE, 178 }; 179 180 uintptr_t get_uart_address(uint32_t instance_nb) 181 { 182 if ((instance_nb == 0U) || 183 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 184 return 0U; 185 } 186 187 return stm32mp1_uart_addresses[instance_nb - 1U]; 188 } 189 #endif 190 191 uint32_t stm32mp_get_chip_version(void) 192 { 193 uint32_t version = 0U; 194 195 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 196 INFO("Cannot get CPU version, debug disabled\n"); 197 return 0U; 198 } 199 200 return version; 201 } 202 203 uint32_t stm32mp_get_chip_dev_id(void) 204 { 205 uint32_t dev_id; 206 207 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 208 INFO("Use default chip ID, debug disabled\n"); 209 dev_id = STM32MP1_CHIP_ID; 210 } 211 212 return dev_id; 213 } 214 215 static uint32_t get_part_number(void) 216 { 217 static uint32_t part_number; 218 219 if (part_number != 0U) { 220 return part_number; 221 } 222 223 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 224 panic(); 225 } 226 227 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 228 PART_NUMBER_OTP_PART_SHIFT; 229 230 part_number |= stm32mp_get_chip_dev_id() << 16; 231 232 return part_number; 233 } 234 235 static uint32_t get_cpu_package(void) 236 { 237 uint32_t package; 238 239 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 240 panic(); 241 } 242 243 package = (package & PACKAGE_OTP_PKG_MASK) >> 244 PACKAGE_OTP_PKG_SHIFT; 245 246 return package; 247 } 248 249 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 250 { 251 char *cpu_s, *cpu_r, *pkg; 252 253 /* MPUs Part Numbers */ 254 switch (get_part_number()) { 255 case STM32MP157C_PART_NB: 256 cpu_s = "157C"; 257 break; 258 case STM32MP157A_PART_NB: 259 cpu_s = "157A"; 260 break; 261 case STM32MP153C_PART_NB: 262 cpu_s = "153C"; 263 break; 264 case STM32MP153A_PART_NB: 265 cpu_s = "153A"; 266 break; 267 case STM32MP151C_PART_NB: 268 cpu_s = "151C"; 269 break; 270 case STM32MP151A_PART_NB: 271 cpu_s = "151A"; 272 break; 273 case STM32MP157F_PART_NB: 274 cpu_s = "157F"; 275 break; 276 case STM32MP157D_PART_NB: 277 cpu_s = "157D"; 278 break; 279 case STM32MP153F_PART_NB: 280 cpu_s = "153F"; 281 break; 282 case STM32MP153D_PART_NB: 283 cpu_s = "153D"; 284 break; 285 case STM32MP151F_PART_NB: 286 cpu_s = "151F"; 287 break; 288 case STM32MP151D_PART_NB: 289 cpu_s = "151D"; 290 break; 291 default: 292 cpu_s = "????"; 293 break; 294 } 295 296 /* Package */ 297 switch (get_cpu_package()) { 298 case PKG_AA_LFBGA448: 299 pkg = "AA"; 300 break; 301 case PKG_AB_LFBGA354: 302 pkg = "AB"; 303 break; 304 case PKG_AC_TFBGA361: 305 pkg = "AC"; 306 break; 307 case PKG_AD_TFBGA257: 308 pkg = "AD"; 309 break; 310 default: 311 pkg = "??"; 312 break; 313 } 314 315 /* REVISION */ 316 switch (stm32mp_get_chip_version()) { 317 case STM32MP1_REV_B: 318 cpu_r = "B"; 319 break; 320 case STM32MP1_REV_Z: 321 cpu_r = "Z"; 322 break; 323 default: 324 cpu_r = "?"; 325 break; 326 } 327 328 snprintf(name, STM32_SOC_NAME_SIZE, 329 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 330 } 331 332 void stm32mp_print_cpuinfo(void) 333 { 334 char name[STM32_SOC_NAME_SIZE]; 335 336 stm32mp_get_soc_name(name); 337 NOTICE("CPU: %s\n", name); 338 } 339 340 void stm32mp_print_boardinfo(void) 341 { 342 uint32_t board_id; 343 uint32_t board_otp; 344 int bsec_node, bsec_board_id_node; 345 void *fdt; 346 const fdt32_t *cuint; 347 348 if (fdt_get_address(&fdt) == 0) { 349 panic(); 350 } 351 352 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 353 if (bsec_node < 0) { 354 return; 355 } 356 357 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 358 if (bsec_board_id_node <= 0) { 359 return; 360 } 361 362 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 363 if (cuint == NULL) { 364 panic(); 365 } 366 367 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 368 369 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 370 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 371 return; 372 } 373 374 if (board_id != 0U) { 375 char rev[2]; 376 377 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 378 rev[1] = '\0'; 379 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 380 BOARD_ID2NB(board_id), 381 BOARD_ID2VARCPN(board_id), 382 BOARD_ID2VARFG(board_id), 383 rev, 384 BOARD_ID2BOM(board_id)); 385 } 386 } 387 388 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 389 bool stm32mp_is_single_core(void) 390 { 391 switch (get_part_number()) { 392 case STM32MP151A_PART_NB: 393 case STM32MP151C_PART_NB: 394 case STM32MP151D_PART_NB: 395 case STM32MP151F_PART_NB: 396 return true; 397 default: 398 return false; 399 } 400 } 401 402 /* Return true when device is in closed state */ 403 bool stm32mp_is_closed_device(void) 404 { 405 uint32_t value; 406 407 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 408 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 409 return true; 410 } 411 412 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 413 } 414 415 uint32_t stm32_iwdg_get_instance(uintptr_t base) 416 { 417 switch (base) { 418 case IWDG1_BASE: 419 return IWDG1_INST; 420 case IWDG2_BASE: 421 return IWDG2_INST; 422 default: 423 panic(); 424 } 425 } 426 427 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 428 { 429 uint32_t iwdg_cfg = 0U; 430 uint32_t otp_value; 431 432 #if defined(IMAGE_BL2) 433 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 434 panic(); 435 } 436 #endif 437 438 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 439 panic(); 440 } 441 442 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 443 iwdg_cfg |= IWDG_HW_ENABLED; 444 } 445 446 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 447 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 448 } 449 450 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 451 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 452 } 453 454 return iwdg_cfg; 455 } 456 457 #if defined(IMAGE_BL2) 458 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 459 { 460 uint32_t otp; 461 uint32_t result; 462 463 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 464 panic(); 465 } 466 467 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 468 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 469 } 470 471 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 472 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 473 } 474 475 result = bsec_write_otp(otp, HW2_OTP); 476 if (result != BSEC_OK) { 477 return result; 478 } 479 480 /* Sticky lock OTP_IWDG (read and write) */ 481 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 482 !bsec_write_sw_lock(HW2_OTP, 1U)) { 483 return BSEC_LOCK_FAIL; 484 } 485 486 return BSEC_OK; 487 } 488 #endif 489 490 #if STM32MP_USE_STM32IMAGE 491 /* Get the non-secure DDR size */ 492 uint32_t stm32mp_get_ddr_ns_size(void) 493 { 494 static uint32_t ddr_ns_size; 495 uint32_t ddr_size; 496 497 if (ddr_ns_size != 0U) { 498 return ddr_ns_size; 499 } 500 501 ddr_size = dt_get_ddr_size(); 502 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 503 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 504 panic(); 505 } 506 507 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 508 509 return ddr_ns_size; 510 } 511 #endif /* STM32MP_USE_STM32IMAGE */ 512