feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Cha

feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Change-Id: Ibc3e52f7f1127bba0dd793be0a26bdff15260824
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency

feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency if the module is disabled and calculate the rate based on the
settings found in its registers if the module is turned on.

Change-Id: Id6db92dbdf03f8119875476ad8f7aa268ff6ea93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the r

feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the rate of its parent.

Change-Id: Ie3becd36721f541d0fab11b2fb57aacd66d48220
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is re

feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is returned in case the PLL is off. Otherwise, the frequency
is determined based on settings found in its registers.

Change-Id: Id200d0eff149109a724eee69b063bf750d5cba2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, th

feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, this function routes the request.

Change-Id: I0c1174cb861d2062882319e46cb6ca97bad70aab
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add mor

feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.

Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(smmu): set root port CR0 GPCEN before ACCESSEN" into integration

Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration

* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp co

Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration

* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp collection to psci_pwrdown_cpu
refactor(psci): factor common code out of the standby finisher
refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state
docs(psci): drop outdated cache maintenance comment

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inli

perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.

Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(smmu): set root port CR0 GPCEN before ACCESSEN

In the SMMU root port programming model, changing both
SMMU_ROOT_CR0.GPCEN and ACCESSEN bits in the same MMIO write operation
is permitted by the a

fix(smmu): set root port CR0 GPCEN before ACCESSEN

In the SMMU root port programming model, changing both
SMMU_ROOT_CR0.GPCEN and ACCESSEN bits in the same MMIO write operation
is permitted by the architecture but left to the SMMU IP implementation
to determine the order of completing one or the other operation.

Enforce more determinism by setting CR0.GPCEN, wait for CR0ACK.GPCEN
completion, then setting CR0.ACCESSEN and wait for CR0ACK.ACCESSEN
completion.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I36ba5fbc13d06c6243226008d18a2d57477b0d28

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refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c24718

refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c2471877ecc833270c511749ff845046f10
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fi

fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fits due to its size, and where it makes use of
non-volatile PMIC registers to alternate between loading and
starting A or B copy of the BL2. The PMIC registers are used
because CPU registers are lost across reset.

In case the B copy is loaded, it is loaded from 8 MiB offset
from start of HF. In case the B copy fails to boot, a simple
reset of the system will switch back to booting previously
known working A copy and allow recovery.

The A/B loader sets MFIS bit MFISBTSTSR_BOOT_PARTITION to
pass the information which A/B copy is currently booting on
to TFA, which then loads the follow up components from 0 MiB
or 8 MiB offset, depending on whether the A or B copy is being
booted.

The MFISBTSTSR_BOOT_PARTITION interferes with regular A/B
switching during boot from eMMC as the boot media, where
the BootROM also sets MFISBTSTSR_BOOT_PARTITION bit in case
the system boots from SECOND eMMC HW BOOT partition.

Since the A/B loader is meant as a development and CI tool,
isolate the A/B loader use to RPC HF only and furthermore
isolate it behind new RCAR_RPC_HYPERFLASH_ABLOADER option
which is disabled by default.

[1] https://github.com/marex/abloader

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04ecd50fa1405b78e1ba3949d54029034d4f22d8

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fix(mbedtls): fix error return code for calc_hash

Make this function return values from crypto_ret_value.
The previous method of returning the mbedtls error code
on failure meant that the authentica

fix(mbedtls): fix error return code for calc_hash

Make this function return values from crypto_ret_value.
The previous method of returning the mbedtls error code
on failure meant that the authentication module couldn't
correctly parse failures from this function.

Change-Id: I9fe6eba1fc79e8f81004f8cd202781aea907e963
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(psa): fix P-384 PSA key signature verification

The buffer size allocated for the raw ECDSA signatures
was too small for P-384 signatures. This led to mbedtls
aborting the generation of the raw s

fix(psa): fix P-384 PSA key signature verification

The buffer size allocated for the raw ECDSA signatures
was too small for P-384 signatures. This led to mbedtls
aborting the generation of the raw sig.

Fix this by increasing the buffer size to the required
value.

Change-Id: I06a9cfe1f4cb2603c5fbe945714e90460c24edb8
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(st-ddr): move skipddc_dat definition

The skipddc_dat variable is only use at one place in dfixlat_program()
function. Move its definition and update there to avoid compilation
issues about varia

fix(st-ddr): move skipddc_dat definition

The skipddc_dat variable is only use at one place in dfixlat_program()
function. Move its definition and update there to avoid compilation
issues about variables being set but not used.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6b5273365f1da26773fc46f898362cb9af170506

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fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "refactor(delay-timer): add timer callback functions" into integration

Merge changes from topic "xlnx_fix_plat_console_changes" into integration

* changes:
feat(xilinx): add none console
feat(versal2): add dtb & runtime console
feat(versal-net): add DTB console t

Merge changes from topic "xlnx_fix_plat_console_changes" into integration

* changes:
feat(xilinx): add none console
feat(versal2): add dtb & runtime console
feat(versal-net): add DTB console to platform.mk
feat(versal-net): dedicate console for boot and runtime
feat(versal): add DTB console to platform.mk
feat(versal): dedicate console for boot and runtime
refactor(xilinx): register runtime console directly
refactor(xilinx): console registration through console holder structure
feat(zynqmp): add DTB console to platform.mk
feat(zynqmp): dedicate console for boot and runtime
fix(xilinx): dcc to support runtime console scope
refactor(xilinx): create generic function for DT console
refactor(xilinx): rename setup_runtime_console to generic
chore(xilinx): rename console variables
chore(xilinx): rename runtime console to DT console

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refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header

refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header file and into the source files, so that they can be built if
needed.

Move timer functions from delay_timer.h into generic_delay_timer.c. Add
them as callback functions which are then called in delay_timer.c.

Change-Id: I96a1eac8948b1a7b1e481899b67a083db4c9b97d
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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fix(xilinx): dcc to support runtime console scope

DCC driver to support boot and runtime console scope
switch for dedicated boot and runtime consoles.

Change-Id: I7769dc44860a5fda99ca42ce17a3a60092

fix(xilinx): dcc to support runtime console scope

DCC driver to support boot and runtime console scope
switch for dedicated boot and runtime consoles.

Change-Id: I7769dc44860a5fda99ca42ce17a3a6009288d7e7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GIC

fix(gicv3): do not assume redistributors are powered down

When initialising a GICv3 compatible interrupt controller, we currently
assume that the GIC is still in its reset state, which means
the GICR_WAKER.ProcessorSleep bit is set. There is an "assert" in the
GIC setup function to check this.
However when using RESET_TO_BL31, there might be prior firmware running,
and it might have used the GIC already. This is for instance the case on
the Allwinner A523 SoC, where the BootROM initialises the GIC to use it
when handling the built-in USB debug protocol.

Drop the assert, which is not the right thing to do here anyway: it's
not checking an internal state. Instead return early when the
redistributor is already marked as active.
Also keep waiting if ChildrenAsleep is unexpectedly set, but warn about
this.

This fixes booting TF-A on an Allwinner A523 SoC when using the USB
debug mode.

Change-Id: I5be9e1b0489d33b8371fff484e526483d5f3d937
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(st-ddr): fix coverity issue in ddrphyinit" into integration

fix(st-ddr): fix coverity issue in ddrphyinit

Address issue CID 445362 and CID 445361 found during coverity scan.

Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <ma

fix(st-ddr): fix coverity issue in ddrphyinit

Address issue CID 445362 and CID 445361 found during coverity scan.

Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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