1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <errno.h> 7 #include <common/debug.h> 8 #include <drivers/clk.h> 9 #include <lib/mmio.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <s32cc-clk-ids.h> 12 #include <s32cc-clk-modules.h> 13 #include <s32cc-clk-regs.h> 14 #include <s32cc-clk-utils.h> 15 #include <s32cc-mc-me.h> 16 17 #define MAX_STACK_DEPTH (40U) 18 19 /* This is used for floating-point precision calculations. */ 20 #define FP_PRECISION (100000000UL) 21 22 struct s32cc_clk_drv { 23 uintptr_t fxosc_base; 24 uintptr_t armpll_base; 25 uintptr_t periphpll_base; 26 uintptr_t armdfs_base; 27 uintptr_t cgm0_base; 28 uintptr_t cgm1_base; 29 uintptr_t cgm5_base; 30 uintptr_t ddrpll_base; 31 uintptr_t mc_me; 32 uintptr_t mc_rgm; 33 uintptr_t rdc; 34 }; 35 36 static int set_module_rate(const struct s32cc_clk_obj *module, 37 unsigned long rate, unsigned long *orate, 38 unsigned int *depth); 39 static int get_module_rate(const struct s32cc_clk_obj *module, 40 const struct s32cc_clk_drv *drv, 41 unsigned long *rate, 42 unsigned int depth); 43 44 static int update_stack_depth(unsigned int *depth) 45 { 46 if (*depth == 0U) { 47 return -ENOMEM; 48 } 49 50 (*depth)--; 51 return 0; 52 } 53 54 static struct s32cc_clk_drv *get_drv(void) 55 { 56 static struct s32cc_clk_drv driver = { 57 .fxosc_base = FXOSC_BASE_ADDR, 58 .armpll_base = ARMPLL_BASE_ADDR, 59 .periphpll_base = PERIPHPLL_BASE_ADDR, 60 .armdfs_base = ARM_DFS_BASE_ADDR, 61 .cgm0_base = CGM0_BASE_ADDR, 62 .cgm1_base = CGM1_BASE_ADDR, 63 .cgm5_base = MC_CGM5_BASE_ADDR, 64 .ddrpll_base = DDRPLL_BASE_ADDR, 65 .mc_me = MC_ME_BASE_ADDR, 66 .mc_rgm = MC_RGM_BASE_ADDR, 67 .rdc = RDC_BASE_ADDR, 68 }; 69 70 return &driver; 71 } 72 73 static int enable_module(struct s32cc_clk_obj *module, 74 const struct s32cc_clk_drv *drv, 75 unsigned int depth); 76 77 static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module) 78 { 79 const struct s32cc_clk *clk = s32cc_obj2clk(module); 80 81 if (clk->module != NULL) { 82 return clk->module; 83 } 84 85 if (clk->pclock != NULL) { 86 return &clk->pclock->desc; 87 } 88 89 return NULL; 90 } 91 92 static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv, 93 uintptr_t *base) 94 { 95 int ret = 0; 96 97 switch (id) { 98 case S32CC_FXOSC: 99 *base = drv->fxosc_base; 100 break; 101 case S32CC_ARM_PLL: 102 *base = drv->armpll_base; 103 break; 104 case S32CC_PERIPH_PLL: 105 *base = drv->periphpll_base; 106 break; 107 case S32CC_DDR_PLL: 108 *base = drv->ddrpll_base; 109 break; 110 case S32CC_ARM_DFS: 111 *base = drv->armdfs_base; 112 break; 113 case S32CC_CGM0: 114 *base = drv->cgm0_base; 115 break; 116 case S32CC_CGM1: 117 *base = drv->cgm1_base; 118 break; 119 case S32CC_CGM5: 120 *base = drv->cgm5_base; 121 break; 122 case S32CC_FIRC: 123 break; 124 case S32CC_SIRC: 125 break; 126 default: 127 ret = -EINVAL; 128 break; 129 } 130 131 if (ret != 0) { 132 ERROR("Unknown clock source id: %u\n", id); 133 } 134 135 return ret; 136 } 137 138 static void enable_fxosc(const struct s32cc_clk_drv *drv) 139 { 140 uintptr_t fxosc_base = drv->fxosc_base; 141 uint32_t ctrl; 142 143 ctrl = mmio_read_32(FXOSC_CTRL(fxosc_base)); 144 if ((ctrl & FXOSC_CTRL_OSCON) != U(0)) { 145 return; 146 } 147 148 ctrl = FXOSC_CTRL_COMP_EN; 149 ctrl &= ~FXOSC_CTRL_OSC_BYP; 150 ctrl |= FXOSC_CTRL_EOCV(0x1); 151 ctrl |= FXOSC_CTRL_GM_SEL(0x7); 152 mmio_write_32(FXOSC_CTRL(fxosc_base), ctrl); 153 154 /* Switch ON the crystal oscillator. */ 155 mmio_setbits_32(FXOSC_CTRL(fxosc_base), FXOSC_CTRL_OSCON); 156 157 /* Wait until the clock is stable. */ 158 while ((mmio_read_32(FXOSC_STAT(fxosc_base)) & FXOSC_STAT_OSC_STAT) == U(0)) { 159 } 160 } 161 162 static int enable_osc(struct s32cc_clk_obj *module, 163 const struct s32cc_clk_drv *drv, 164 unsigned int depth) 165 { 166 const struct s32cc_osc *osc = s32cc_obj2osc(module); 167 unsigned int ldepth = depth; 168 int ret = 0; 169 170 ret = update_stack_depth(&ldepth); 171 if (ret != 0) { 172 return ret; 173 } 174 175 switch (osc->source) { 176 case S32CC_FXOSC: 177 enable_fxosc(drv); 178 break; 179 /* FIRC and SIRC oscillators are enabled by default */ 180 case S32CC_FIRC: 181 break; 182 case S32CC_SIRC: 183 break; 184 default: 185 ERROR("Invalid oscillator %d\n", osc->source); 186 ret = -EINVAL; 187 break; 188 }; 189 190 return ret; 191 } 192 193 static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module) 194 { 195 const struct s32cc_pll *pll = s32cc_obj2pll(module); 196 197 if (pll->source == NULL) { 198 ERROR("Failed to identify PLL's parent\n"); 199 } 200 201 return pll->source; 202 } 203 204 static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq, 205 uint32_t *mfi, uint32_t *mfn) 206 207 { 208 unsigned long vco; 209 unsigned long mfn64; 210 211 /* FRAC-N mode */ 212 *mfi = (uint32_t)(pll_vco / ref_freq); 213 214 /* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */ 215 mfn64 = pll_vco % ref_freq; 216 mfn64 *= FP_PRECISION; 217 mfn64 /= ref_freq; 218 mfn64 *= 18432UL; 219 mfn64 /= FP_PRECISION; 220 221 if (mfn64 > UINT32_MAX) { 222 return -EINVAL; 223 } 224 225 *mfn = (uint32_t)mfn64; 226 227 vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL; 228 vco += (unsigned long)*mfi * FP_PRECISION; 229 vco *= ref_freq; 230 vco /= FP_PRECISION; 231 232 if (vco != pll_vco) { 233 ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n", 234 pll_vco, vco); 235 return -EINVAL; 236 } 237 238 return 0; 239 } 240 241 static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll) 242 { 243 const struct s32cc_clk_obj *source = pll->source; 244 const struct s32cc_clk *clk; 245 246 if (source == NULL) { 247 ERROR("Failed to identify PLL's parent\n"); 248 return NULL; 249 } 250 251 if (source->type != s32cc_clk_t) { 252 ERROR("The parent of the PLL isn't a clock\n"); 253 return NULL; 254 } 255 256 clk = s32cc_obj2clk(source); 257 258 if (clk->module == NULL) { 259 ERROR("The clock isn't connected to a module\n"); 260 return NULL; 261 } 262 263 source = clk->module; 264 265 if ((source->type != s32cc_clkmux_t) && 266 (source->type != s32cc_shared_clkmux_t)) { 267 ERROR("The parent of the PLL isn't a MUX\n"); 268 return NULL; 269 } 270 271 return s32cc_obj2clkmux(source); 272 } 273 274 static void disable_odiv(uintptr_t pll_addr, uint32_t div_index) 275 { 276 mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 277 } 278 279 static void enable_odiv(uintptr_t pll_addr, uint32_t div_index) 280 { 281 mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 282 } 283 284 static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs) 285 { 286 uint32_t i; 287 288 for (i = 0; i < ndivs; i++) { 289 disable_odiv(pll_addr, i); 290 } 291 } 292 293 static void enable_pll_hw(uintptr_t pll_addr) 294 { 295 /* Enable the PLL. */ 296 mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0); 297 298 /* Poll until PLL acquires lock. */ 299 while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) { 300 } 301 } 302 303 static void disable_pll_hw(uintptr_t pll_addr) 304 { 305 mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD); 306 } 307 308 static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr, 309 const struct s32cc_clk_drv *drv, uint32_t sclk_id, 310 unsigned long sclk_freq) 311 { 312 uint32_t rdiv = 1, mfi, mfn; 313 int ret; 314 315 ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn); 316 if (ret != 0) { 317 return -EINVAL; 318 } 319 320 /* Disable ODIVs*/ 321 disable_odivs(pll_addr, pll->ndividers); 322 323 /* Disable PLL */ 324 disable_pll_hw(pll_addr); 325 326 /* Program PLLCLKMUX */ 327 mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id); 328 329 /* Program VCO */ 330 mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr), 331 PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK, 332 PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi)); 333 334 mmio_write_32(PLLDIG_PLLFD(pll_addr), 335 PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN); 336 337 enable_pll_hw(pll_addr); 338 339 return ret; 340 } 341 342 static int enable_pll(struct s32cc_clk_obj *module, 343 const struct s32cc_clk_drv *drv, 344 unsigned int depth) 345 { 346 const struct s32cc_pll *pll = s32cc_obj2pll(module); 347 const struct s32cc_clkmux *mux; 348 uintptr_t pll_addr = UL(0x0); 349 unsigned int ldepth = depth; 350 unsigned long sclk_freq; 351 uint32_t sclk_id; 352 int ret; 353 354 ret = update_stack_depth(&ldepth); 355 if (ret != 0) { 356 return ret; 357 } 358 359 mux = get_pll_mux(pll); 360 if (mux == NULL) { 361 return -EINVAL; 362 } 363 364 if (pll->instance != mux->module) { 365 ERROR("MUX type is not in sync with PLL ID\n"); 366 return -EINVAL; 367 } 368 369 ret = get_base_addr(pll->instance, drv, &pll_addr); 370 if (ret != 0) { 371 ERROR("Failed to detect PLL instance\n"); 372 return ret; 373 } 374 375 switch (mux->source_id) { 376 case S32CC_CLK_FIRC: 377 sclk_freq = 48U * MHZ; 378 sclk_id = 0; 379 break; 380 case S32CC_CLK_FXOSC: 381 sclk_freq = 40U * MHZ; 382 sclk_id = 1; 383 break; 384 default: 385 ERROR("Invalid source selection for PLL 0x%lx\n", 386 pll_addr); 387 return -EINVAL; 388 }; 389 390 return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq); 391 } 392 393 static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv) 394 { 395 const struct s32cc_clk_obj *parent; 396 397 parent = pdiv->parent; 398 if (parent == NULL) { 399 ERROR("Failed to identify PLL divider's parent\n"); 400 return NULL; 401 } 402 403 if (parent->type != s32cc_pll_t) { 404 ERROR("The parent of the divider is not a PLL instance\n"); 405 return NULL; 406 } 407 408 return s32cc_obj2pll(parent); 409 } 410 411 static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc) 412 { 413 uint32_t pllodiv; 414 uint32_t pdiv; 415 416 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index)); 417 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 418 419 if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) { 420 return; 421 } 422 423 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 424 disable_odiv(pll_addr, div_index); 425 } 426 427 pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U); 428 mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv); 429 430 enable_odiv(pll_addr, div_index); 431 } 432 433 static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module) 434 { 435 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 436 437 if (pdiv->parent == NULL) { 438 ERROR("Failed to identify PLL DIV's parent\n"); 439 } 440 441 return pdiv->parent; 442 } 443 444 static int enable_pll_div(struct s32cc_clk_obj *module, 445 const struct s32cc_clk_drv *drv, 446 unsigned int depth) 447 { 448 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 449 uintptr_t pll_addr = 0x0ULL; 450 unsigned int ldepth = depth; 451 const struct s32cc_pll *pll; 452 uint32_t dc; 453 int ret; 454 455 ret = update_stack_depth(&ldepth); 456 if (ret != 0) { 457 return ret; 458 } 459 460 pll = get_div_pll(pdiv); 461 if (pll == NULL) { 462 ERROR("The parent of the PLL DIV is invalid\n"); 463 return 0; 464 } 465 466 ret = get_base_addr(pll->instance, drv, &pll_addr); 467 if (ret != 0) { 468 ERROR("Failed to detect PLL instance\n"); 469 return -EINVAL; 470 } 471 472 dc = (uint32_t)(pll->vco_freq / pdiv->freq); 473 474 config_pll_out_div(pll_addr, pdiv->index, dc); 475 476 return 0; 477 } 478 479 static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source, 480 bool safe_clk) 481 { 482 uint32_t css, csc; 483 484 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 485 486 /* Already configured */ 487 if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) && 488 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 489 ((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) { 490 return 0; 491 } 492 493 /* Ongoing clock switch? */ 494 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 495 MC_CGM_MUXn_CSS_SWIP) != 0U) { 496 } 497 498 csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)); 499 500 /* Clear previous source. */ 501 csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK); 502 503 if (!safe_clk) { 504 /* Select the clock source and trigger the clock switch. */ 505 csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW; 506 } else { 507 /* Switch to safe clock */ 508 csc |= MC_CGM_MUXn_CSC_SAFE_SW; 509 } 510 511 mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc); 512 513 /* Wait for configuration bit to auto-clear. */ 514 while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) & 515 MC_CGM_MUXn_CSC_CLK_SW) != 0U) { 516 } 517 518 /* Is the clock switch completed? */ 519 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 520 MC_CGM_MUXn_CSS_SWIP) != 0U) { 521 } 522 523 /* 524 * Check if the switch succeeded. 525 * Check switch trigger cause and the source. 526 */ 527 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 528 if (!safe_clk) { 529 if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 530 (MC_CGM_MUXn_CSS_SELSTAT(css) == source)) { 531 return 0; 532 } 533 534 ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n", 535 mux, source, cgm_addr); 536 } else { 537 if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) || 538 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) && 539 ((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) { 540 return 0; 541 } 542 543 ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n", 544 mux, cgm_addr); 545 } 546 547 return -EINVAL; 548 } 549 550 static int enable_cgm_mux(const struct s32cc_clkmux *mux, 551 const struct s32cc_clk_drv *drv) 552 { 553 uintptr_t cgm_addr = UL(0x0); 554 uint32_t mux_hw_clk; 555 int ret; 556 557 ret = get_base_addr(mux->module, drv, &cgm_addr); 558 if (ret != 0) { 559 return ret; 560 } 561 562 mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id); 563 564 return cgm_mux_clk_config(cgm_addr, mux->index, 565 mux_hw_clk, false); 566 } 567 568 static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module) 569 { 570 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 571 struct s32cc_clk *clk; 572 573 if (mux == NULL) { 574 return NULL; 575 } 576 577 clk = s32cc_get_arch_clk(mux->source_id); 578 if (clk == NULL) { 579 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 580 mux->source_id, mux->index); 581 return NULL; 582 } 583 584 return &clk->desc; 585 } 586 587 static int enable_mux(struct s32cc_clk_obj *module, 588 const struct s32cc_clk_drv *drv, 589 unsigned int depth) 590 { 591 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 592 unsigned int ldepth = depth; 593 const struct s32cc_clk *clk; 594 int ret = 0; 595 596 ret = update_stack_depth(&ldepth); 597 if (ret != 0) { 598 return ret; 599 } 600 601 if (mux == NULL) { 602 return -EINVAL; 603 } 604 605 clk = s32cc_get_arch_clk(mux->source_id); 606 if (clk == NULL) { 607 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 608 mux->source_id, mux->index); 609 return -EINVAL; 610 } 611 612 switch (mux->module) { 613 /* PLL mux will be enabled by PLL setup */ 614 case S32CC_ARM_PLL: 615 case S32CC_PERIPH_PLL: 616 case S32CC_DDR_PLL: 617 break; 618 case S32CC_CGM1: 619 ret = enable_cgm_mux(mux, drv); 620 break; 621 case S32CC_CGM0: 622 ret = enable_cgm_mux(mux, drv); 623 break; 624 case S32CC_CGM5: 625 ret = enable_cgm_mux(mux, drv); 626 break; 627 default: 628 ERROR("Unknown mux parent type: %d\n", mux->module); 629 ret = -EINVAL; 630 break; 631 }; 632 633 return ret; 634 } 635 636 static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module) 637 { 638 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 639 640 if (dfs->parent == NULL) { 641 ERROR("Failed to identify DFS's parent\n"); 642 } 643 644 return dfs->parent; 645 } 646 647 static int enable_dfs(struct s32cc_clk_obj *module, 648 const struct s32cc_clk_drv *drv, 649 unsigned int depth) 650 { 651 unsigned int ldepth = depth; 652 int ret = 0; 653 654 ret = update_stack_depth(&ldepth); 655 if (ret != 0) { 656 return ret; 657 } 658 659 return 0; 660 } 661 662 static int get_dfs_freq(const struct s32cc_clk_obj *module, 663 const struct s32cc_clk_drv *drv, 664 unsigned long *rate, unsigned int depth) 665 { 666 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 667 unsigned int ldepth = depth; 668 uintptr_t dfs_addr; 669 int ret; 670 671 ret = update_stack_depth(&ldepth); 672 if (ret != 0) { 673 return ret; 674 } 675 676 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 677 if (ret != 0) { 678 ERROR("Failed to detect the DFS instance\n"); 679 return ret; 680 } 681 682 return get_module_rate(dfs->parent, drv, rate, ldepth); 683 } 684 685 static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div) 686 { 687 const struct s32cc_clk_obj *parent = dfs_div->parent; 688 689 if (parent->type != s32cc_dfs_t) { 690 ERROR("DFS DIV doesn't have a DFS as parent\n"); 691 return NULL; 692 } 693 694 return s32cc_obj2dfs(parent); 695 } 696 697 static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div, 698 uint32_t *mfi, uint32_t *mfn) 699 { 700 uint64_t factor64, tmp64, ofreq; 701 uint32_t factor32; 702 703 unsigned long in = dfs_freq; 704 unsigned long out = dfs_div->freq; 705 706 /** 707 * factor = (IN / OUT) / 2 708 * MFI = integer(factor) 709 * MFN = (factor - MFI) * 36 710 */ 711 factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL; 712 tmp64 = factor64 / FP_PRECISION; 713 if (tmp64 > UINT32_MAX) { 714 return -EINVAL; 715 } 716 717 factor32 = (uint32_t)tmp64; 718 *mfi = factor32; 719 720 tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION; 721 if (tmp64 > UINT32_MAX) { 722 return -EINVAL; 723 } 724 725 *mfn = (uint32_t)tmp64; 726 727 /* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */ 728 factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL; 729 factor64 += ((uint64_t)*mfi) * FP_PRECISION; 730 factor64 *= 2ULL; 731 ofreq = (((uint64_t)in) * FP_PRECISION) / factor64; 732 733 if (ofreq != dfs_div->freq) { 734 ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n", 735 dfs_div->freq); 736 ERROR("Nearest freq = %" PRIx64 "\n", ofreq); 737 return -EINVAL; 738 } 739 740 return 0; 741 } 742 743 static int init_dfs_port(uintptr_t dfs_addr, uint32_t port, 744 uint32_t mfi, uint32_t mfn) 745 { 746 uint32_t portsr, portolsr; 747 uint32_t mask, old_mfi, old_mfn; 748 uint32_t dvport; 749 bool init_dfs; 750 751 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port)); 752 753 old_mfi = DFS_DVPORTn_MFI(dvport); 754 old_mfn = DFS_DVPORTn_MFN(dvport); 755 756 portsr = mmio_read_32(DFS_PORTSR(dfs_addr)); 757 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 758 759 /* Skip configuration if it's not needed */ 760 if (((portsr & BIT_32(port)) != 0U) && 761 ((portolsr & BIT_32(port)) == 0U) && 762 (mfi == old_mfi) && (mfn == old_mfn)) { 763 return 0; 764 } 765 766 init_dfs = (portsr == 0U); 767 768 if (init_dfs) { 769 mask = DFS_PORTRESET_MASK; 770 } else { 771 mask = DFS_PORTRESET_SET(BIT_32(port)); 772 } 773 774 mmio_write_32(DFS_PORTOLSR(dfs_addr), mask); 775 mmio_write_32(DFS_PORTRESET(dfs_addr), mask); 776 777 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) { 778 } 779 780 if (init_dfs) { 781 mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 782 } 783 784 mmio_write_32(DFS_DVPORTn(dfs_addr, port), 785 DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn)); 786 787 if (init_dfs) { 788 /* DFS clk enable programming */ 789 mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 790 } 791 792 mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port)); 793 794 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) { 795 } 796 797 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 798 if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) { 799 ERROR("Failed to lock DFS divider\n"); 800 return -EINVAL; 801 } 802 803 return 0; 804 } 805 806 static struct s32cc_clk_obj * 807 get_dfs_div_parent(const struct s32cc_clk_obj *module) 808 { 809 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 810 811 if (dfs_div->parent == NULL) { 812 ERROR("Failed to identify DFS divider's parent\n"); 813 } 814 815 return dfs_div->parent; 816 } 817 818 static int enable_dfs_div(struct s32cc_clk_obj *module, 819 const struct s32cc_clk_drv *drv, 820 unsigned int depth) 821 { 822 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 823 unsigned int ldepth = depth; 824 const struct s32cc_dfs *dfs; 825 uintptr_t dfs_addr = 0UL; 826 unsigned long dfs_freq; 827 uint32_t mfi, mfn; 828 int ret = 0; 829 830 ret = update_stack_depth(&ldepth); 831 if (ret != 0) { 832 return ret; 833 } 834 835 dfs = get_div_dfs(dfs_div); 836 if (dfs == NULL) { 837 return -EINVAL; 838 } 839 840 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 841 if ((ret != 0) || (dfs_addr == 0UL)) { 842 return -EINVAL; 843 } 844 845 ret = get_module_rate(&dfs->desc, drv, &dfs_freq, depth); 846 if (ret != 0) { 847 return ret; 848 } 849 850 ret = get_dfs_mfi_mfn(dfs_freq, dfs_div, &mfi, &mfn); 851 if (ret != 0) { 852 return -EINVAL; 853 } 854 855 return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn); 856 } 857 858 typedef int (*enable_clk_t)(struct s32cc_clk_obj *module, 859 const struct s32cc_clk_drv *drv, 860 unsigned int depth); 861 862 static int enable_part(struct s32cc_clk_obj *module, 863 const struct s32cc_clk_drv *drv, 864 unsigned int depth) 865 { 866 const struct s32cc_part *part = s32cc_obj2part(module); 867 uint32_t part_no = part->partition_id; 868 869 if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) { 870 return -EINVAL; 871 } 872 873 return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no); 874 } 875 876 static int enable_part_block(struct s32cc_clk_obj *module, 877 const struct s32cc_clk_drv *drv, 878 unsigned int depth) 879 { 880 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 881 const struct s32cc_part *part = block->part; 882 uint32_t part_no = part->partition_id; 883 unsigned int ldepth = depth; 884 uint32_t cofb; 885 int ret; 886 887 ret = update_stack_depth(&ldepth); 888 if (ret != 0) { 889 return ret; 890 } 891 892 if ((block->block >= s32cc_part_block0) && 893 (block->block <= s32cc_part_block15)) { 894 cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0; 895 mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status); 896 } else { 897 ERROR("Unknown partition block type: %d\n", block->block); 898 return -EINVAL; 899 } 900 901 return 0; 902 } 903 904 static struct s32cc_clk_obj * 905 get_part_block_parent(const struct s32cc_clk_obj *module) 906 { 907 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 908 909 return &block->part->desc; 910 } 911 912 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 913 const struct s32cc_clk_drv *drv, 914 unsigned int depth); 915 916 static int enable_part_block_link(struct s32cc_clk_obj *module, 917 const struct s32cc_clk_drv *drv, 918 unsigned int depth) 919 { 920 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 921 struct s32cc_part_block *block = link->block; 922 unsigned int ldepth = depth; 923 int ret; 924 925 ret = update_stack_depth(&ldepth); 926 if (ret != 0) { 927 return ret; 928 } 929 930 /* Move the enablement algorithm to partition tree */ 931 return enable_module_with_refcount(&block->desc, drv, ldepth); 932 } 933 934 static struct s32cc_clk_obj * 935 get_part_block_link_parent(const struct s32cc_clk_obj *module) 936 { 937 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 938 939 return link->parent; 940 } 941 942 static int get_part_block_link_freq(const struct s32cc_clk_obj *module, 943 const struct s32cc_clk_drv *drv, 944 unsigned long *rate, unsigned int depth) 945 { 946 const struct s32cc_part_block_link *block = s32cc_obj2partblocklink(module); 947 unsigned int ldepth = depth; 948 int ret; 949 950 ret = update_stack_depth(&ldepth); 951 if (ret != 0) { 952 return ret; 953 } 954 955 return get_module_rate(block->parent, drv, rate, ldepth); 956 } 957 958 static int no_enable(struct s32cc_clk_obj *module, 959 const struct s32cc_clk_drv *drv, 960 unsigned int depth) 961 { 962 return 0; 963 } 964 965 static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod, 966 const struct s32cc_clk_drv *drv, bool leaf_node, 967 unsigned int depth) 968 { 969 unsigned int ldepth = depth; 970 int ret = 0; 971 972 if (mod == NULL) { 973 return 0; 974 } 975 976 ret = update_stack_depth(&ldepth); 977 if (ret != 0) { 978 return ret; 979 } 980 981 /* Refcount will be updated as part of the recursivity */ 982 if (leaf_node) { 983 return en_cb(mod, drv, ldepth); 984 } 985 986 if (mod->refcount == 0U) { 987 ret = en_cb(mod, drv, ldepth); 988 } 989 990 if (ret == 0) { 991 mod->refcount++; 992 } 993 994 return ret; 995 } 996 997 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module); 998 999 static int enable_module(struct s32cc_clk_obj *module, 1000 const struct s32cc_clk_drv *drv, 1001 unsigned int depth) 1002 { 1003 struct s32cc_clk_obj *parent = get_module_parent(module); 1004 static const enable_clk_t enable_clbs[12] = { 1005 [s32cc_clk_t] = no_enable, 1006 [s32cc_osc_t] = enable_osc, 1007 [s32cc_pll_t] = enable_pll, 1008 [s32cc_pll_out_div_t] = enable_pll_div, 1009 [s32cc_clkmux_t] = enable_mux, 1010 [s32cc_shared_clkmux_t] = enable_mux, 1011 [s32cc_dfs_t] = enable_dfs, 1012 [s32cc_dfs_div_t] = enable_dfs_div, 1013 [s32cc_part_t] = enable_part, 1014 [s32cc_part_block_t] = enable_part_block, 1015 [s32cc_part_block_link_t] = enable_part_block_link, 1016 }; 1017 unsigned int ldepth = depth; 1018 uint32_t index; 1019 int ret = 0; 1020 1021 ret = update_stack_depth(&ldepth); 1022 if (ret != 0) { 1023 return ret; 1024 } 1025 1026 if (drv == NULL) { 1027 return -EINVAL; 1028 } 1029 1030 index = (uint32_t)module->type; 1031 1032 if (index >= ARRAY_SIZE(enable_clbs)) { 1033 ERROR("Undefined module type: %d\n", module->type); 1034 return -EINVAL; 1035 } 1036 1037 if (enable_clbs[index] == NULL) { 1038 ERROR("Undefined callback for the clock type: %d\n", 1039 module->type); 1040 return -EINVAL; 1041 } 1042 1043 parent = get_module_parent(module); 1044 1045 ret = exec_cb_with_refcount(enable_module, parent, drv, 1046 false, ldepth); 1047 if (ret != 0) { 1048 return ret; 1049 } 1050 1051 ret = exec_cb_with_refcount(enable_clbs[index], module, drv, 1052 true, ldepth); 1053 if (ret != 0) { 1054 return ret; 1055 } 1056 1057 return ret; 1058 } 1059 1060 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1061 const struct s32cc_clk_drv *drv, 1062 unsigned int depth) 1063 { 1064 return exec_cb_with_refcount(enable_module, module, drv, false, depth); 1065 } 1066 1067 static int s32cc_clk_enable(unsigned long id) 1068 { 1069 const struct s32cc_clk_drv *drv = get_drv(); 1070 unsigned int depth = MAX_STACK_DEPTH; 1071 struct s32cc_clk *clk; 1072 1073 clk = s32cc_get_arch_clk(id); 1074 if (clk == NULL) { 1075 return -EINVAL; 1076 } 1077 1078 return enable_module_with_refcount(&clk->desc, drv, depth); 1079 } 1080 1081 static void s32cc_clk_disable(unsigned long id) 1082 { 1083 } 1084 1085 static bool s32cc_clk_is_enabled(unsigned long id) 1086 { 1087 return false; 1088 } 1089 1090 static int set_osc_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1091 unsigned long *orate, unsigned int *depth) 1092 { 1093 struct s32cc_osc *osc = s32cc_obj2osc(module); 1094 int ret; 1095 1096 ret = update_stack_depth(depth); 1097 if (ret != 0) { 1098 return ret; 1099 } 1100 1101 if ((osc->freq != 0UL) && (rate != osc->freq)) { 1102 ERROR("Already initialized oscillator. freq = %lu\n", 1103 osc->freq); 1104 return -EINVAL; 1105 } 1106 1107 osc->freq = rate; 1108 *orate = osc->freq; 1109 1110 return 0; 1111 } 1112 1113 static int get_osc_freq(const struct s32cc_clk_obj *module, 1114 const struct s32cc_clk_drv *drv, 1115 unsigned long *rate, unsigned int depth) 1116 { 1117 const struct s32cc_osc *osc = s32cc_obj2osc(module); 1118 unsigned int ldepth = depth; 1119 int ret; 1120 1121 ret = update_stack_depth(&ldepth); 1122 if (ret != 0) { 1123 return ret; 1124 } 1125 1126 if (osc->freq == 0UL) { 1127 ERROR("Uninitialized oscillator\n"); 1128 return -EINVAL; 1129 } 1130 1131 *rate = osc->freq; 1132 1133 return 0; 1134 } 1135 1136 static int set_clk_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1137 unsigned long *orate, unsigned int *depth) 1138 { 1139 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1140 int ret; 1141 1142 ret = update_stack_depth(depth); 1143 if (ret != 0) { 1144 return ret; 1145 } 1146 1147 if ((clk->min_freq != 0UL) && (clk->max_freq != 0UL) && 1148 ((rate < clk->min_freq) || (rate > clk->max_freq))) { 1149 ERROR("%lu frequency is out of the allowed range: [%lu:%lu]\n", 1150 rate, clk->min_freq, clk->max_freq); 1151 return -EINVAL; 1152 } 1153 1154 if (clk->module != NULL) { 1155 return set_module_rate(clk->module, rate, orate, depth); 1156 } 1157 1158 if (clk->pclock != NULL) { 1159 return set_clk_freq(&clk->pclock->desc, rate, orate, depth); 1160 } 1161 1162 return -EINVAL; 1163 } 1164 1165 static int get_clk_freq(const struct s32cc_clk_obj *module, 1166 const struct s32cc_clk_drv *drv, unsigned long *rate, 1167 unsigned int depth) 1168 { 1169 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1170 unsigned int ldepth = depth; 1171 int ret; 1172 1173 ret = update_stack_depth(&ldepth); 1174 if (ret != 0) { 1175 return ret; 1176 } 1177 1178 if (clk == NULL) { 1179 ERROR("Invalid clock\n"); 1180 return -EINVAL; 1181 } 1182 1183 if (clk->module != NULL) { 1184 return get_module_rate(clk->module, drv, rate, ldepth); 1185 } 1186 1187 if (clk->pclock == NULL) { 1188 ERROR("Invalid clock parent\n"); 1189 return -EINVAL; 1190 } 1191 1192 return get_clk_freq(&clk->pclock->desc, drv, rate, ldepth); 1193 } 1194 1195 static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1196 unsigned long *orate, unsigned int *depth) 1197 { 1198 struct s32cc_pll *pll = s32cc_obj2pll(module); 1199 int ret; 1200 1201 ret = update_stack_depth(depth); 1202 if (ret != 0) { 1203 return ret; 1204 } 1205 1206 if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) { 1207 ERROR("PLL frequency was already set\n"); 1208 return -EINVAL; 1209 } 1210 1211 pll->vco_freq = rate; 1212 *orate = pll->vco_freq; 1213 1214 return 0; 1215 } 1216 1217 static int get_pll_freq(const struct s32cc_clk_obj *module, 1218 const struct s32cc_clk_drv *drv, 1219 unsigned long *rate, unsigned int depth) 1220 { 1221 const struct s32cc_pll *pll = s32cc_obj2pll(module); 1222 const struct s32cc_clk *source; 1223 uint32_t mfi, mfn, rdiv, plldv; 1224 unsigned long prate, clk_src; 1225 unsigned int ldepth = depth; 1226 uintptr_t pll_addr = 0UL; 1227 uint64_t t1, t2; 1228 uint32_t pllpd; 1229 int ret; 1230 1231 ret = update_stack_depth(&ldepth); 1232 if (ret != 0) { 1233 return ret; 1234 } 1235 1236 ret = get_base_addr(pll->instance, drv, &pll_addr); 1237 if (ret != 0) { 1238 ERROR("Failed to detect PLL instance\n"); 1239 return ret; 1240 } 1241 1242 /* Disabled PLL */ 1243 pllpd = mmio_read_32(PLLDIG_PLLCR(pll_addr)) & PLLDIG_PLLCR_PLLPD; 1244 if (pllpd != 0U) { 1245 *rate = pll->vco_freq; 1246 return 0; 1247 } 1248 1249 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 1250 switch (clk_src) { 1251 case 0: 1252 clk_src = S32CC_CLK_FIRC; 1253 break; 1254 case 1: 1255 clk_src = S32CC_CLK_FXOSC; 1256 break; 1257 default: 1258 ERROR("Failed to identify PLL source id %" PRIu64 "\n", clk_src); 1259 return -EINVAL; 1260 }; 1261 1262 source = s32cc_get_arch_clk(clk_src); 1263 if (source == NULL) { 1264 ERROR("Failed to get PLL source clock\n"); 1265 return -EINVAL; 1266 } 1267 1268 ret = get_module_rate(&source->desc, drv, &prate, ldepth); 1269 if (ret != 0) { 1270 ERROR("Failed to get PLL's parent frequency\n"); 1271 return ret; 1272 } 1273 1274 plldv = mmio_read_32(PLLDIG_PLLDV(pll_addr)); 1275 mfi = PLLDIG_PLLDV_MFI(plldv); 1276 rdiv = PLLDIG_PLLDV_RDIV(plldv); 1277 if (rdiv == 0U) { 1278 rdiv = 1; 1279 } 1280 1281 /* Frac-N mode */ 1282 mfn = PLLDIG_PLLFD_MFN_SET(mmio_read_32(PLLDIG_PLLFD(pll_addr))); 1283 1284 /* PLL VCO frequency in Fractional mode when PLLDV[RDIV] is not 0 */ 1285 t1 = prate / rdiv; 1286 t2 = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 18432U); 1287 1288 *rate = t1 * t2 / FP_PRECISION; 1289 1290 return 0; 1291 } 1292 1293 static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1294 unsigned long *orate, unsigned int *depth) 1295 { 1296 struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1297 const struct s32cc_pll *pll; 1298 unsigned long prate, dc; 1299 int ret; 1300 1301 ret = update_stack_depth(depth); 1302 if (ret != 0) { 1303 return ret; 1304 } 1305 1306 if (pdiv->parent == NULL) { 1307 ERROR("Failed to identify PLL divider's parent\n"); 1308 return -EINVAL; 1309 } 1310 1311 pll = s32cc_obj2pll(pdiv->parent); 1312 if (pll == NULL) { 1313 ERROR("The parent of the PLL DIV is invalid\n"); 1314 return -EINVAL; 1315 } 1316 1317 prate = pll->vco_freq; 1318 1319 /** 1320 * The PLL is not initialized yet, so let's take a risk 1321 * and accept the proposed rate. 1322 */ 1323 if (prate == 0UL) { 1324 pdiv->freq = rate; 1325 *orate = rate; 1326 return 0; 1327 } 1328 1329 /* Decline in case the rate cannot fit PLL's requirements. */ 1330 dc = prate / rate; 1331 if ((prate / dc) != rate) { 1332 return -EINVAL; 1333 } 1334 1335 pdiv->freq = rate; 1336 *orate = pdiv->freq; 1337 1338 return 0; 1339 } 1340 1341 static int get_pll_div_freq(const struct s32cc_clk_obj *module, 1342 const struct s32cc_clk_drv *drv, 1343 unsigned long *rate, unsigned int depth) 1344 { 1345 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1346 const struct s32cc_pll *pll; 1347 unsigned int ldepth = depth; 1348 uintptr_t pll_addr = 0UL; 1349 unsigned long pfreq; 1350 uint32_t pllodiv; 1351 uint32_t dc; 1352 int ret; 1353 1354 ret = update_stack_depth(&ldepth); 1355 if (ret != 0) { 1356 return ret; 1357 } 1358 1359 pll = get_div_pll(pdiv); 1360 if (pll == NULL) { 1361 ERROR("The parent of the PLL DIV is invalid\n"); 1362 return -EINVAL; 1363 } 1364 1365 ret = get_base_addr(pll->instance, drv, &pll_addr); 1366 if (ret != 0) { 1367 ERROR("Failed to detect PLL instance\n"); 1368 return -EINVAL; 1369 } 1370 1371 ret = get_module_rate(pdiv->parent, drv, &pfreq, ldepth); 1372 if (ret != 0) { 1373 ERROR("Failed to get the frequency of PLL %" PRIxPTR "\n", 1374 pll_addr); 1375 return ret; 1376 } 1377 1378 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index)); 1379 1380 /* Disabled module */ 1381 if ((pllodiv & PLLDIG_PLLODIV_DE) == 0U) { 1382 *rate = pdiv->freq; 1383 return 0; 1384 } 1385 1386 dc = PLLDIG_PLLODIV_DIV(pllodiv); 1387 *rate = (pfreq * FP_PRECISION) / (dc + 1U) / FP_PRECISION; 1388 1389 return 0; 1390 } 1391 1392 static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1393 unsigned long *orate, unsigned int *depth) 1394 { 1395 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1396 int ret; 1397 1398 ret = update_stack_depth(depth); 1399 if (ret != 0) { 1400 return ret; 1401 } 1402 1403 if (fdiv->parent == NULL) { 1404 ERROR("The divider doesn't have a valid parent\b"); 1405 return -EINVAL; 1406 } 1407 1408 ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth); 1409 1410 /* Update the output rate based on the parent's rate */ 1411 *orate /= fdiv->rate_div; 1412 1413 return ret; 1414 } 1415 1416 static int get_fixed_div_freq(const struct s32cc_clk_obj *module, 1417 const struct s32cc_clk_drv *drv, 1418 unsigned long *rate, unsigned int depth) 1419 { 1420 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1421 unsigned long pfreq; 1422 int ret; 1423 1424 ret = get_module_rate(fdiv->parent, drv, &pfreq, depth); 1425 if (ret != 0) { 1426 return ret; 1427 } 1428 1429 *rate = (pfreq * FP_PRECISION / fdiv->rate_div) / FP_PRECISION; 1430 return 0; 1431 } 1432 1433 static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1434 unsigned long *orate, unsigned int *depth) 1435 { 1436 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1437 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1438 int ret; 1439 1440 ret = update_stack_depth(depth); 1441 if (ret != 0) { 1442 return ret; 1443 } 1444 1445 if (clk == NULL) { 1446 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1447 mux->index, mux->source_id); 1448 return -EINVAL; 1449 } 1450 1451 return set_module_rate(&clk->desc, rate, orate, depth); 1452 } 1453 1454 static int get_mux_freq(const struct s32cc_clk_obj *module, 1455 const struct s32cc_clk_drv *drv, 1456 unsigned long *rate, unsigned int depth) 1457 { 1458 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1459 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1460 unsigned int ldepth = depth; 1461 int ret; 1462 1463 ret = update_stack_depth(&ldepth); 1464 if (ret != 0) { 1465 return ret; 1466 } 1467 1468 if (clk == NULL) { 1469 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1470 mux->index, mux->source_id); 1471 return -EINVAL; 1472 } 1473 1474 return get_clk_freq(&clk->desc, drv, rate, ldepth); 1475 } 1476 1477 static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1478 unsigned long *orate, unsigned int *depth) 1479 { 1480 struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1481 const struct s32cc_dfs *dfs; 1482 int ret; 1483 1484 ret = update_stack_depth(depth); 1485 if (ret != 0) { 1486 return ret; 1487 } 1488 1489 if (dfs_div->parent == NULL) { 1490 ERROR("Failed to identify DFS divider's parent\n"); 1491 return -EINVAL; 1492 } 1493 1494 /* Sanity check */ 1495 dfs = s32cc_obj2dfs(dfs_div->parent); 1496 if (dfs->parent == NULL) { 1497 ERROR("Failed to identify DFS's parent\n"); 1498 return -EINVAL; 1499 } 1500 1501 if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) { 1502 ERROR("DFS DIV frequency was already set to %lu\n", 1503 dfs_div->freq); 1504 return -EINVAL; 1505 } 1506 1507 dfs_div->freq = rate; 1508 *orate = rate; 1509 1510 return ret; 1511 } 1512 1513 static unsigned long compute_dfs_div_freq(unsigned long pfreq, uint32_t mfi, uint32_t mfn) 1514 { 1515 unsigned long freq; 1516 1517 /** 1518 * Formula for input and output clocks of each port divider. 1519 * See 'Digital Frequency Synthesizer' chapter from Reference Manual. 1520 * 1521 * freq = pfreq / (2 * (mfi + mfn / 36.0)); 1522 */ 1523 freq = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 36UL); 1524 freq *= 2UL; 1525 freq = pfreq * FP_PRECISION / freq; 1526 1527 return freq; 1528 } 1529 1530 static int get_dfs_div_freq(const struct s32cc_clk_obj *module, 1531 const struct s32cc_clk_drv *drv, 1532 unsigned long *rate, unsigned int depth) 1533 { 1534 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1535 unsigned int ldepth = depth; 1536 const struct s32cc_dfs *dfs; 1537 uint32_t dvport, mfi, mfn; 1538 uintptr_t dfs_addr = 0UL; 1539 unsigned long pfreq; 1540 int ret; 1541 1542 ret = update_stack_depth(&ldepth); 1543 if (ret != 0) { 1544 return ret; 1545 } 1546 1547 dfs = get_div_dfs(dfs_div); 1548 if (dfs == NULL) { 1549 return -EINVAL; 1550 } 1551 1552 ret = get_module_rate(dfs_div->parent, drv, &pfreq, ldepth); 1553 if (ret != 0) { 1554 return ret; 1555 } 1556 1557 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 1558 if (ret != 0) { 1559 ERROR("Failed to detect the DFS instance\n"); 1560 return ret; 1561 } 1562 1563 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, dfs_div->index)); 1564 1565 mfi = DFS_DVPORTn_MFI(dvport); 1566 mfn = DFS_DVPORTn_MFN(dvport); 1567 1568 /* Disabled port */ 1569 if ((mfi == 0U) && (mfn == 0U)) { 1570 *rate = dfs_div->freq; 1571 return 0; 1572 } 1573 1574 *rate = compute_dfs_div_freq(pfreq, mfi, mfn); 1575 return 0; 1576 } 1577 1578 static int set_module_rate(const struct s32cc_clk_obj *module, 1579 unsigned long rate, unsigned long *orate, 1580 unsigned int *depth) 1581 { 1582 int ret = 0; 1583 1584 ret = update_stack_depth(depth); 1585 if (ret != 0) { 1586 return ret; 1587 } 1588 1589 ret = -EINVAL; 1590 1591 switch (module->type) { 1592 case s32cc_clk_t: 1593 ret = set_clk_freq(module, rate, orate, depth); 1594 break; 1595 case s32cc_osc_t: 1596 ret = set_osc_freq(module, rate, orate, depth); 1597 break; 1598 case s32cc_pll_t: 1599 ret = set_pll_freq(module, rate, orate, depth); 1600 break; 1601 case s32cc_pll_out_div_t: 1602 ret = set_pll_div_freq(module, rate, orate, depth); 1603 break; 1604 case s32cc_fixed_div_t: 1605 ret = set_fixed_div_freq(module, rate, orate, depth); 1606 break; 1607 case s32cc_clkmux_t: 1608 ret = set_mux_freq(module, rate, orate, depth); 1609 break; 1610 case s32cc_shared_clkmux_t: 1611 ret = set_mux_freq(module, rate, orate, depth); 1612 break; 1613 case s32cc_dfs_t: 1614 ERROR("Setting the frequency of a DFS is not allowed!"); 1615 break; 1616 case s32cc_dfs_div_t: 1617 ret = set_dfs_div_freq(module, rate, orate, depth); 1618 break; 1619 default: 1620 break; 1621 } 1622 1623 return ret; 1624 } 1625 1626 static int get_module_rate(const struct s32cc_clk_obj *module, 1627 const struct s32cc_clk_drv *drv, 1628 unsigned long *rate, 1629 unsigned int depth) 1630 { 1631 unsigned int ldepth = depth; 1632 int ret = 0; 1633 1634 ret = update_stack_depth(&ldepth); 1635 if (ret != 0) { 1636 return ret; 1637 } 1638 1639 switch (module->type) { 1640 case s32cc_osc_t: 1641 ret = get_osc_freq(module, drv, rate, ldepth); 1642 break; 1643 case s32cc_clk_t: 1644 ret = get_clk_freq(module, drv, rate, ldepth); 1645 break; 1646 case s32cc_pll_t: 1647 ret = get_pll_freq(module, drv, rate, ldepth); 1648 break; 1649 case s32cc_dfs_t: 1650 ret = get_dfs_freq(module, drv, rate, ldepth); 1651 break; 1652 case s32cc_dfs_div_t: 1653 ret = get_dfs_div_freq(module, drv, rate, ldepth); 1654 break; 1655 case s32cc_fixed_div_t: 1656 ret = get_fixed_div_freq(module, drv, rate, ldepth); 1657 break; 1658 case s32cc_pll_out_div_t: 1659 ret = get_pll_div_freq(module, drv, rate, ldepth); 1660 break; 1661 case s32cc_clkmux_t: 1662 ret = get_mux_freq(module, drv, rate, ldepth); 1663 break; 1664 case s32cc_shared_clkmux_t: 1665 ret = get_mux_freq(module, drv, rate, ldepth); 1666 break; 1667 case s32cc_part_t: 1668 ERROR("s32cc_part_t cannot be used to get rate\n"); 1669 break; 1670 case s32cc_part_block_t: 1671 ERROR("s32cc_part_block_t cannot be used to get rate\n"); 1672 break; 1673 case s32cc_part_block_link_t: 1674 ret = get_part_block_link_freq(module, drv, rate, ldepth); 1675 break; 1676 default: 1677 ret = -EINVAL; 1678 break; 1679 } 1680 1681 return ret; 1682 } 1683 1684 static int s32cc_clk_set_rate(unsigned long id, unsigned long rate, 1685 unsigned long *orate) 1686 { 1687 unsigned int depth = MAX_STACK_DEPTH; 1688 const struct s32cc_clk *clk; 1689 int ret; 1690 1691 clk = s32cc_get_arch_clk(id); 1692 if (clk == NULL) { 1693 return -EINVAL; 1694 } 1695 1696 ret = set_module_rate(&clk->desc, rate, orate, &depth); 1697 if (ret != 0) { 1698 ERROR("Failed to set frequency (%lu MHz) for clock %lu\n", 1699 rate, id); 1700 } 1701 1702 return ret; 1703 } 1704 1705 static unsigned long s32cc_clk_get_rate(unsigned long id) 1706 { 1707 const struct s32cc_clk_drv *drv = get_drv(); 1708 unsigned int depth = MAX_STACK_DEPTH; 1709 const struct s32cc_clk *clk; 1710 unsigned long rate = 0UL; 1711 int ret; 1712 1713 clk = s32cc_get_arch_clk(id); 1714 if (clk == NULL) { 1715 return 0; 1716 } 1717 1718 ret = get_module_rate(&clk->desc, drv, &rate, depth); 1719 if (ret != 0) { 1720 ERROR("Failed to get frequency (%lu MHz) for clock %lu\n", 1721 rate, id); 1722 return 0; 1723 } 1724 1725 return rate; 1726 } 1727 1728 static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module) 1729 { 1730 return NULL; 1731 } 1732 1733 typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj); 1734 1735 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module) 1736 { 1737 static const get_parent_clb_t parents_clbs[12] = { 1738 [s32cc_clk_t] = get_clk_parent, 1739 [s32cc_osc_t] = get_no_parent, 1740 [s32cc_pll_t] = get_pll_parent, 1741 [s32cc_pll_out_div_t] = get_pll_div_parent, 1742 [s32cc_clkmux_t] = get_mux_parent, 1743 [s32cc_shared_clkmux_t] = get_mux_parent, 1744 [s32cc_dfs_t] = get_dfs_parent, 1745 [s32cc_dfs_div_t] = get_dfs_div_parent, 1746 [s32cc_part_t] = get_no_parent, 1747 [s32cc_part_block_t] = get_part_block_parent, 1748 [s32cc_part_block_link_t] = get_part_block_link_parent, 1749 }; 1750 uint32_t index; 1751 1752 if (module == NULL) { 1753 return NULL; 1754 } 1755 1756 index = (uint32_t)module->type; 1757 1758 if (index >= ARRAY_SIZE(parents_clbs)) { 1759 ERROR("Undefined module type: %d\n", module->type); 1760 return NULL; 1761 } 1762 1763 if (parents_clbs[index] == NULL) { 1764 ERROR("Undefined parent getter for type: %d\n", module->type); 1765 return NULL; 1766 } 1767 1768 return parents_clbs[index](module); 1769 } 1770 1771 static int s32cc_clk_get_parent(unsigned long id) 1772 { 1773 struct s32cc_clk *parent_clk; 1774 const struct s32cc_clk_obj *parent; 1775 const struct s32cc_clk *clk; 1776 unsigned long parent_id; 1777 int ret; 1778 1779 clk = s32cc_get_arch_clk(id); 1780 if (clk == NULL) { 1781 return -EINVAL; 1782 } 1783 1784 parent = get_module_parent(clk->module); 1785 if (parent == NULL) { 1786 return -EINVAL; 1787 } 1788 1789 parent_clk = s32cc_obj2clk(parent); 1790 if (parent_clk == NULL) { 1791 return -EINVAL; 1792 } 1793 1794 ret = s32cc_get_clk_id(parent_clk, &parent_id); 1795 if (ret != 0) { 1796 return ret; 1797 } 1798 1799 if (parent_id > (unsigned long)INT_MAX) { 1800 return -E2BIG; 1801 } 1802 1803 return (int)parent_id; 1804 } 1805 1806 static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id) 1807 { 1808 const struct s32cc_clk *parent; 1809 const struct s32cc_clk *clk; 1810 bool valid_source = false; 1811 struct s32cc_clkmux *mux; 1812 uint8_t i; 1813 1814 clk = s32cc_get_arch_clk(id); 1815 if (clk == NULL) { 1816 return -EINVAL; 1817 } 1818 1819 parent = s32cc_get_arch_clk(parent_id); 1820 if (parent == NULL) { 1821 return -EINVAL; 1822 } 1823 1824 if (!is_s32cc_clk_mux(clk)) { 1825 ERROR("Clock %lu is not a mux\n", id); 1826 return -EINVAL; 1827 } 1828 1829 mux = s32cc_clk2mux(clk); 1830 if (mux == NULL) { 1831 ERROR("Failed to cast clock %lu to clock mux\n", id); 1832 return -EINVAL; 1833 } 1834 1835 for (i = 0; i < mux->nclks; i++) { 1836 if (mux->clkids[i] == parent_id) { 1837 valid_source = true; 1838 break; 1839 } 1840 } 1841 1842 if (!valid_source) { 1843 ERROR("Clock %lu is not a valid clock for mux %lu\n", 1844 parent_id, id); 1845 return -EINVAL; 1846 } 1847 1848 mux->source_id = parent_id; 1849 1850 return 0; 1851 } 1852 1853 static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) 1854 { 1855 const uintptr_t base_addrs[11] = { 1856 drv->fxosc_base, 1857 drv->armpll_base, 1858 drv->periphpll_base, 1859 drv->armdfs_base, 1860 drv->cgm0_base, 1861 drv->cgm1_base, 1862 drv->cgm5_base, 1863 drv->ddrpll_base, 1864 drv->mc_me, 1865 drv->mc_rgm, 1866 drv->rdc, 1867 }; 1868 size_t i; 1869 int ret; 1870 1871 for (i = 0U; i < ARRAY_SIZE(base_addrs); i++) { 1872 ret = mmap_add_dynamic_region(base_addrs[i], base_addrs[i], 1873 PAGE_SIZE, 1874 MT_DEVICE | MT_RW | MT_SECURE); 1875 if (ret != 0) { 1876 ERROR("Failed to map clock module 0x%" PRIuPTR "\n", 1877 base_addrs[i]); 1878 return ret; 1879 } 1880 } 1881 1882 return 0; 1883 } 1884 1885 int s32cc_clk_register_drv(bool mmap_regs) 1886 { 1887 static const struct clk_ops s32cc_clk_ops = { 1888 .enable = s32cc_clk_enable, 1889 .disable = s32cc_clk_disable, 1890 .is_enabled = s32cc_clk_is_enabled, 1891 .get_rate = s32cc_clk_get_rate, 1892 .set_rate = s32cc_clk_set_rate, 1893 .get_parent = s32cc_clk_get_parent, 1894 .set_parent = s32cc_clk_set_parent, 1895 }; 1896 const struct s32cc_clk_drv *drv; 1897 1898 clk_register(&s32cc_clk_ops); 1899 1900 drv = get_drv(); 1901 if (drv == NULL) { 1902 return -EINVAL; 1903 } 1904 1905 if (mmap_regs) { 1906 return s32cc_clk_mmap_regs(drv); 1907 } 1908 1909 return 0; 1910 } 1911 1912