1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <errno.h> 7 #include <common/debug.h> 8 #include <drivers/clk.h> 9 #include <lib/mmio.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <s32cc-clk-ids.h> 12 #include <s32cc-clk-modules.h> 13 #include <s32cc-clk-regs.h> 14 #include <s32cc-clk-utils.h> 15 #include <s32cc-mc-me.h> 16 17 #define MAX_STACK_DEPTH (40U) 18 19 /* This is used for floating-point precision calculations. */ 20 #define FP_PRECISION (100000000UL) 21 22 struct s32cc_clk_drv { 23 uintptr_t fxosc_base; 24 uintptr_t armpll_base; 25 uintptr_t periphpll_base; 26 uintptr_t armdfs_base; 27 uintptr_t periphdfs_base; 28 uintptr_t cgm0_base; 29 uintptr_t cgm1_base; 30 uintptr_t cgm5_base; 31 uintptr_t ddrpll_base; 32 uintptr_t mc_me; 33 uintptr_t mc_rgm; 34 uintptr_t rdc; 35 }; 36 37 static int set_module_rate(const struct s32cc_clk_obj *module, 38 unsigned long rate, unsigned long *orate, 39 unsigned int *depth); 40 static int get_module_rate(const struct s32cc_clk_obj *module, 41 const struct s32cc_clk_drv *drv, 42 unsigned long *rate, 43 unsigned int depth); 44 45 static int update_stack_depth(unsigned int *depth) 46 { 47 if (*depth == 0U) { 48 return -ENOMEM; 49 } 50 51 (*depth)--; 52 return 0; 53 } 54 55 static struct s32cc_clk_drv *get_drv(void) 56 { 57 static struct s32cc_clk_drv driver = { 58 .fxosc_base = FXOSC_BASE_ADDR, 59 .armpll_base = ARMPLL_BASE_ADDR, 60 .periphpll_base = PERIPHPLL_BASE_ADDR, 61 .armdfs_base = ARM_DFS_BASE_ADDR, 62 .periphdfs_base = PERIPH_DFS_BASE_ADDR, 63 .cgm0_base = CGM0_BASE_ADDR, 64 .cgm1_base = CGM1_BASE_ADDR, 65 .cgm5_base = MC_CGM5_BASE_ADDR, 66 .ddrpll_base = DDRPLL_BASE_ADDR, 67 .mc_me = MC_ME_BASE_ADDR, 68 .mc_rgm = MC_RGM_BASE_ADDR, 69 .rdc = RDC_BASE_ADDR, 70 }; 71 72 return &driver; 73 } 74 75 static int enable_module(struct s32cc_clk_obj *module, 76 const struct s32cc_clk_drv *drv, 77 unsigned int depth); 78 79 static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module) 80 { 81 const struct s32cc_clk *clk = s32cc_obj2clk(module); 82 83 if (clk->module != NULL) { 84 return clk->module; 85 } 86 87 if (clk->pclock != NULL) { 88 return &clk->pclock->desc; 89 } 90 91 return NULL; 92 } 93 94 static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv, 95 uintptr_t *base) 96 { 97 int ret = 0; 98 99 switch (id) { 100 case S32CC_FXOSC: 101 *base = drv->fxosc_base; 102 break; 103 case S32CC_ARM_PLL: 104 *base = drv->armpll_base; 105 break; 106 case S32CC_PERIPH_PLL: 107 *base = drv->periphpll_base; 108 break; 109 case S32CC_DDR_PLL: 110 *base = drv->ddrpll_base; 111 break; 112 case S32CC_ARM_DFS: 113 *base = drv->armdfs_base; 114 break; 115 case S32CC_PERIPH_DFS: 116 *base = drv->periphdfs_base; 117 break; 118 case S32CC_CGM0: 119 *base = drv->cgm0_base; 120 break; 121 case S32CC_CGM1: 122 *base = drv->cgm1_base; 123 break; 124 case S32CC_CGM5: 125 *base = drv->cgm5_base; 126 break; 127 case S32CC_FIRC: 128 break; 129 case S32CC_SIRC: 130 break; 131 default: 132 ret = -EINVAL; 133 break; 134 } 135 136 if (ret != 0) { 137 ERROR("Unknown clock source id: %u\n", id); 138 } 139 140 return ret; 141 } 142 143 static void enable_fxosc(const struct s32cc_clk_drv *drv) 144 { 145 uintptr_t fxosc_base = drv->fxosc_base; 146 uint32_t ctrl; 147 148 ctrl = mmio_read_32(FXOSC_CTRL(fxosc_base)); 149 if ((ctrl & FXOSC_CTRL_OSCON) != U(0)) { 150 return; 151 } 152 153 ctrl = FXOSC_CTRL_COMP_EN; 154 ctrl &= ~FXOSC_CTRL_OSC_BYP; 155 ctrl |= FXOSC_CTRL_EOCV(0x1); 156 ctrl |= FXOSC_CTRL_GM_SEL(0x7); 157 mmio_write_32(FXOSC_CTRL(fxosc_base), ctrl); 158 159 /* Switch ON the crystal oscillator. */ 160 mmio_setbits_32(FXOSC_CTRL(fxosc_base), FXOSC_CTRL_OSCON); 161 162 /* Wait until the clock is stable. */ 163 while ((mmio_read_32(FXOSC_STAT(fxosc_base)) & FXOSC_STAT_OSC_STAT) == U(0)) { 164 } 165 } 166 167 static int enable_osc(struct s32cc_clk_obj *module, 168 const struct s32cc_clk_drv *drv, 169 unsigned int depth) 170 { 171 const struct s32cc_osc *osc = s32cc_obj2osc(module); 172 unsigned int ldepth = depth; 173 int ret = 0; 174 175 ret = update_stack_depth(&ldepth); 176 if (ret != 0) { 177 return ret; 178 } 179 180 switch (osc->source) { 181 case S32CC_FXOSC: 182 enable_fxosc(drv); 183 break; 184 /* FIRC and SIRC oscillators are enabled by default */ 185 case S32CC_FIRC: 186 break; 187 case S32CC_SIRC: 188 break; 189 default: 190 ERROR("Invalid oscillator %d\n", osc->source); 191 ret = -EINVAL; 192 break; 193 }; 194 195 return ret; 196 } 197 198 static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module) 199 { 200 const struct s32cc_pll *pll = s32cc_obj2pll(module); 201 202 if (pll->source == NULL) { 203 ERROR("Failed to identify PLL's parent\n"); 204 } 205 206 return pll->source; 207 } 208 209 static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq, 210 uint32_t *mfi, uint32_t *mfn) 211 212 { 213 unsigned long vco; 214 unsigned long mfn64; 215 216 /* FRAC-N mode */ 217 *mfi = (uint32_t)(pll_vco / ref_freq); 218 219 /* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */ 220 mfn64 = pll_vco % ref_freq; 221 mfn64 *= FP_PRECISION; 222 mfn64 /= ref_freq; 223 mfn64 *= 18432UL; 224 mfn64 /= FP_PRECISION; 225 226 if (mfn64 > UINT32_MAX) { 227 return -EINVAL; 228 } 229 230 *mfn = (uint32_t)mfn64; 231 232 vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL; 233 vco += (unsigned long)*mfi * FP_PRECISION; 234 vco *= ref_freq; 235 vco /= FP_PRECISION; 236 237 if (vco != pll_vco) { 238 ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n", 239 pll_vco, vco); 240 return -EINVAL; 241 } 242 243 return 0; 244 } 245 246 static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll) 247 { 248 const struct s32cc_clk_obj *source = pll->source; 249 const struct s32cc_clk *clk; 250 251 if (source == NULL) { 252 ERROR("Failed to identify PLL's parent\n"); 253 return NULL; 254 } 255 256 if (source->type != s32cc_clk_t) { 257 ERROR("The parent of the PLL isn't a clock\n"); 258 return NULL; 259 } 260 261 clk = s32cc_obj2clk(source); 262 263 if (clk->module == NULL) { 264 ERROR("The clock isn't connected to a module\n"); 265 return NULL; 266 } 267 268 source = clk->module; 269 270 if ((source->type != s32cc_clkmux_t) && 271 (source->type != s32cc_shared_clkmux_t)) { 272 ERROR("The parent of the PLL isn't a MUX\n"); 273 return NULL; 274 } 275 276 return s32cc_obj2clkmux(source); 277 } 278 279 static void disable_odiv(uintptr_t pll_addr, uint32_t div_index) 280 { 281 mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 282 } 283 284 static void enable_odiv(uintptr_t pll_addr, uint32_t div_index) 285 { 286 mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 287 } 288 289 static void enable_odivs(uintptr_t pll_addr, uint32_t ndivs, uint32_t mask) 290 { 291 uint32_t i; 292 293 for (i = 0; i < ndivs; i++) { 294 if ((mask & BIT_32(i)) != 0U) { 295 enable_odiv(pll_addr, i); 296 } 297 } 298 } 299 300 static int adjust_odiv_settings(const struct s32cc_pll *pll, uintptr_t pll_addr, 301 uint32_t odivs_mask, unsigned long old_vco) 302 { 303 uint64_t old_odiv_freq, odiv_freq; 304 uint32_t i, pllodiv, pdiv; 305 int ret = 0; 306 307 if (old_vco == 0UL) { 308 return 0; 309 } 310 311 for (i = 0; i < pll->ndividers; i++) { 312 if ((odivs_mask & BIT_32(i)) == 0U) { 313 continue; 314 } 315 316 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, i)); 317 318 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 319 320 old_odiv_freq = ((old_vco * FP_PRECISION) / (pdiv + 1U)) / FP_PRECISION; 321 pdiv = (uint32_t)(pll->vco_freq * FP_PRECISION / old_odiv_freq / FP_PRECISION); 322 323 odiv_freq = pll->vco_freq * FP_PRECISION / pdiv / FP_PRECISION; 324 325 if (old_odiv_freq != odiv_freq) { 326 ERROR("Failed to adjust ODIV %" PRIu32 " to match previous frequency\n", 327 i); 328 } 329 330 pllodiv = PLLDIG_PLLODIV_DIV_SET(pdiv - 1U); 331 mmio_write_32(PLLDIG_PLLODIV(pll_addr, i), pllodiv); 332 } 333 334 return ret; 335 } 336 337 static uint32_t get_enabled_odivs(uintptr_t pll_addr, uint32_t ndivs) 338 { 339 uint32_t mask = 0; 340 uint32_t pllodiv; 341 uint32_t i; 342 343 for (i = 0; i < ndivs; i++) { 344 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, i)); 345 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 346 mask |= BIT_32(i); 347 } 348 } 349 350 return mask; 351 } 352 353 static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs) 354 { 355 uint32_t i; 356 357 for (i = 0; i < ndivs; i++) { 358 disable_odiv(pll_addr, i); 359 } 360 } 361 362 static void enable_pll_hw(uintptr_t pll_addr) 363 { 364 /* Enable the PLL. */ 365 mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0); 366 367 /* Poll until PLL acquires lock. */ 368 while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) { 369 } 370 } 371 372 static void disable_pll_hw(uintptr_t pll_addr) 373 { 374 mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD); 375 } 376 377 static bool is_pll_enabled(uintptr_t pll_base) 378 { 379 uint32_t pllcr, pllsr; 380 381 pllcr = mmio_read_32(PLLDIG_PLLCR(pll_base)); 382 pllsr = mmio_read_32(PLLDIG_PLLSR(pll_base)); 383 384 /* Enabled and locked PLL */ 385 if ((pllcr & PLLDIG_PLLCR_PLLPD) != 0U) { 386 return false; 387 } 388 389 if ((pllsr & PLLDIG_PLLSR_LOCK) == 0U) { 390 return false; 391 } 392 393 return true; 394 } 395 396 static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr, 397 const struct s32cc_clk_drv *drv, uint32_t sclk_id, 398 unsigned long sclk_freq, unsigned int depth) 399 { 400 uint32_t rdiv = 1, mfi, mfn; 401 unsigned long old_vco = 0UL; 402 unsigned int ldepth = depth; 403 uint32_t odivs_mask; 404 int ret; 405 406 ret = update_stack_depth(&ldepth); 407 if (ret != 0) { 408 return ret; 409 } 410 411 ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn); 412 if (ret != 0) { 413 return -EINVAL; 414 } 415 416 odivs_mask = get_enabled_odivs(pll_addr, pll->ndividers); 417 418 if (is_pll_enabled(pll_addr)) { 419 ret = get_module_rate(&pll->desc, drv, &old_vco, ldepth); 420 if (ret != 0) { 421 return ret; 422 } 423 } 424 425 /* Disable ODIVs*/ 426 disable_odivs(pll_addr, pll->ndividers); 427 428 /* Disable PLL */ 429 disable_pll_hw(pll_addr); 430 431 /* Program PLLCLKMUX */ 432 mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id); 433 434 /* Program VCO */ 435 mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr), 436 PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK, 437 PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi)); 438 439 mmio_write_32(PLLDIG_PLLFD(pll_addr), 440 PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN); 441 442 ret = adjust_odiv_settings(pll, pll_addr, odivs_mask, old_vco); 443 if (ret != 0) { 444 return ret; 445 } 446 447 enable_pll_hw(pll_addr); 448 449 /* Enable out dividers */ 450 enable_odivs(pll_addr, pll->ndividers, odivs_mask); 451 452 return ret; 453 } 454 455 static int enable_pll(struct s32cc_clk_obj *module, 456 const struct s32cc_clk_drv *drv, 457 unsigned int depth) 458 { 459 const struct s32cc_pll *pll = s32cc_obj2pll(module); 460 unsigned int clk_src, ldepth = depth; 461 unsigned long sclk_freq, pll_vco; 462 const struct s32cc_clkmux *mux; 463 uintptr_t pll_addr = UL(0x0); 464 bool pll_enabled; 465 uint32_t sclk_id; 466 int ret; 467 468 ret = update_stack_depth(&ldepth); 469 if (ret != 0) { 470 return ret; 471 } 472 473 mux = get_pll_mux(pll); 474 if (mux == NULL) { 475 return -EINVAL; 476 } 477 478 if (pll->instance != mux->module) { 479 ERROR("MUX type is not in sync with PLL ID\n"); 480 return -EINVAL; 481 } 482 483 ret = get_base_addr(pll->instance, drv, &pll_addr); 484 if (ret != 0) { 485 ERROR("Failed to detect PLL instance\n"); 486 return ret; 487 } 488 489 switch (mux->source_id) { 490 case S32CC_CLK_FIRC: 491 sclk_freq = 48U * MHZ; 492 sclk_id = 0; 493 break; 494 case S32CC_CLK_FXOSC: 495 sclk_freq = 40U * MHZ; 496 sclk_id = 1; 497 break; 498 default: 499 ERROR("Invalid source selection for PLL 0x%lx\n", 500 pll_addr); 501 return -EINVAL; 502 }; 503 504 ret = get_module_rate(&pll->desc, drv, &pll_vco, depth); 505 if (ret != 0) { 506 return ret; 507 } 508 509 pll_enabled = is_pll_enabled(pll_addr); 510 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 511 512 if ((clk_src == sclk_id) && pll_enabled && 513 (pll_vco == pll->vco_freq)) { 514 return 0; 515 } 516 517 return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq, ldepth); 518 } 519 520 static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv) 521 { 522 const struct s32cc_clk_obj *parent; 523 524 parent = pdiv->parent; 525 if (parent == NULL) { 526 ERROR("Failed to identify PLL divider's parent\n"); 527 return NULL; 528 } 529 530 if (parent->type != s32cc_pll_t) { 531 ERROR("The parent of the divider is not a PLL instance\n"); 532 return NULL; 533 } 534 535 return s32cc_obj2pll(parent); 536 } 537 538 static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc) 539 { 540 uint32_t pllodiv; 541 uint32_t pdiv; 542 543 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index)); 544 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 545 546 if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) { 547 return; 548 } 549 550 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 551 disable_odiv(pll_addr, div_index); 552 } 553 554 pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U); 555 mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv); 556 557 enable_odiv(pll_addr, div_index); 558 } 559 560 static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module) 561 { 562 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 563 564 if (pdiv->parent == NULL) { 565 ERROR("Failed to identify PLL DIV's parent\n"); 566 } 567 568 return pdiv->parent; 569 } 570 571 static int enable_pll_div(struct s32cc_clk_obj *module, 572 const struct s32cc_clk_drv *drv, 573 unsigned int depth) 574 { 575 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 576 uintptr_t pll_addr = 0x0ULL; 577 unsigned int ldepth = depth; 578 const struct s32cc_pll *pll; 579 unsigned long pll_vco; 580 uint32_t dc; 581 int ret; 582 583 ret = update_stack_depth(&ldepth); 584 if (ret != 0) { 585 return ret; 586 } 587 588 pll = get_div_pll(pdiv); 589 if (pll == NULL) { 590 ERROR("The parent of the PLL DIV is invalid\n"); 591 return 0; 592 } 593 594 ret = get_base_addr(pll->instance, drv, &pll_addr); 595 if (ret != 0) { 596 ERROR("Failed to detect PLL instance\n"); 597 return -EINVAL; 598 } 599 600 ret = get_module_rate(&pll->desc, drv, &pll_vco, ldepth); 601 if (ret != 0) { 602 ERROR("Failed to enable the PLL due to unknown rate for 0x%" PRIxPTR "\n", 603 pll_addr); 604 return ret; 605 } 606 607 dc = (uint32_t)(pll_vco / pdiv->freq); 608 609 config_pll_out_div(pll_addr, pdiv->index, dc); 610 611 return 0; 612 } 613 614 static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source, 615 bool safe_clk) 616 { 617 uint32_t css, csc; 618 619 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 620 621 /* Already configured */ 622 if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) && 623 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 624 ((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) { 625 return 0; 626 } 627 628 /* Ongoing clock switch? */ 629 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 630 MC_CGM_MUXn_CSS_SWIP) != 0U) { 631 } 632 633 csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)); 634 635 /* Clear previous source. */ 636 csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK); 637 638 if (!safe_clk) { 639 /* Select the clock source and trigger the clock switch. */ 640 csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW; 641 } else { 642 /* Switch to safe clock */ 643 csc |= MC_CGM_MUXn_CSC_SAFE_SW; 644 } 645 646 mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc); 647 648 /* Wait for configuration bit to auto-clear. */ 649 while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) & 650 MC_CGM_MUXn_CSC_CLK_SW) != 0U) { 651 } 652 653 /* Is the clock switch completed? */ 654 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 655 MC_CGM_MUXn_CSS_SWIP) != 0U) { 656 } 657 658 /* 659 * Check if the switch succeeded. 660 * Check switch trigger cause and the source. 661 */ 662 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 663 if (!safe_clk) { 664 if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 665 (MC_CGM_MUXn_CSS_SELSTAT(css) == source)) { 666 return 0; 667 } 668 669 ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n", 670 mux, source, cgm_addr); 671 } else { 672 if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) || 673 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) && 674 ((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) { 675 return 0; 676 } 677 678 ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n", 679 mux, cgm_addr); 680 } 681 682 return -EINVAL; 683 } 684 685 static int enable_cgm_mux(const struct s32cc_clkmux *mux, 686 const struct s32cc_clk_drv *drv) 687 { 688 uintptr_t cgm_addr = UL(0x0); 689 uint32_t mux_hw_clk; 690 int ret; 691 692 ret = get_base_addr(mux->module, drv, &cgm_addr); 693 if (ret != 0) { 694 return ret; 695 } 696 697 mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id); 698 699 return cgm_mux_clk_config(cgm_addr, mux->index, 700 mux_hw_clk, false); 701 } 702 703 static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module) 704 { 705 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 706 struct s32cc_clk *clk; 707 708 if (mux == NULL) { 709 return NULL; 710 } 711 712 clk = s32cc_get_arch_clk(mux->source_id); 713 if (clk == NULL) { 714 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 715 mux->source_id, mux->index); 716 return NULL; 717 } 718 719 return &clk->desc; 720 } 721 722 static int enable_mux(struct s32cc_clk_obj *module, 723 const struct s32cc_clk_drv *drv, 724 unsigned int depth) 725 { 726 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 727 unsigned int ldepth = depth; 728 const struct s32cc_clk *clk; 729 int ret = 0; 730 731 ret = update_stack_depth(&ldepth); 732 if (ret != 0) { 733 return ret; 734 } 735 736 if (mux == NULL) { 737 return -EINVAL; 738 } 739 740 clk = s32cc_get_arch_clk(mux->source_id); 741 if (clk == NULL) { 742 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 743 mux->source_id, mux->index); 744 return -EINVAL; 745 } 746 747 switch (mux->module) { 748 /* PLL mux will be enabled by PLL setup */ 749 case S32CC_ARM_PLL: 750 case S32CC_PERIPH_PLL: 751 case S32CC_DDR_PLL: 752 break; 753 case S32CC_CGM1: 754 ret = enable_cgm_mux(mux, drv); 755 break; 756 case S32CC_CGM0: 757 ret = enable_cgm_mux(mux, drv); 758 break; 759 case S32CC_CGM5: 760 ret = enable_cgm_mux(mux, drv); 761 break; 762 default: 763 ERROR("Unknown mux parent type: %d\n", mux->module); 764 ret = -EINVAL; 765 break; 766 }; 767 768 return ret; 769 } 770 771 static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module) 772 { 773 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 774 775 if (dfs->parent == NULL) { 776 ERROR("Failed to identify DFS's parent\n"); 777 } 778 779 return dfs->parent; 780 } 781 782 static int enable_dfs(struct s32cc_clk_obj *module, 783 const struct s32cc_clk_drv *drv, 784 unsigned int depth) 785 { 786 unsigned int ldepth = depth; 787 int ret = 0; 788 789 ret = update_stack_depth(&ldepth); 790 if (ret != 0) { 791 return ret; 792 } 793 794 return 0; 795 } 796 797 static int get_dfs_freq(const struct s32cc_clk_obj *module, 798 const struct s32cc_clk_drv *drv, 799 unsigned long *rate, unsigned int depth) 800 { 801 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 802 unsigned int ldepth = depth; 803 uintptr_t dfs_addr; 804 int ret; 805 806 ret = update_stack_depth(&ldepth); 807 if (ret != 0) { 808 return ret; 809 } 810 811 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 812 if (ret != 0) { 813 ERROR("Failed to detect the DFS instance\n"); 814 return ret; 815 } 816 817 return get_module_rate(dfs->parent, drv, rate, ldepth); 818 } 819 820 static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div) 821 { 822 const struct s32cc_clk_obj *parent = dfs_div->parent; 823 824 if (parent->type != s32cc_dfs_t) { 825 ERROR("DFS DIV doesn't have a DFS as parent\n"); 826 return NULL; 827 } 828 829 return s32cc_obj2dfs(parent); 830 } 831 832 static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div, 833 uint32_t *mfi, uint32_t *mfn) 834 { 835 uint64_t factor64, tmp64, ofreq; 836 uint32_t factor32; 837 838 unsigned long in = dfs_freq; 839 unsigned long out = dfs_div->freq; 840 841 /** 842 * factor = (IN / OUT) / 2 843 * MFI = integer(factor) 844 * MFN = (factor - MFI) * 36 845 */ 846 factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL; 847 tmp64 = factor64 / FP_PRECISION; 848 if (tmp64 > UINT32_MAX) { 849 return -EINVAL; 850 } 851 852 factor32 = (uint32_t)tmp64; 853 *mfi = factor32; 854 855 tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION; 856 if (tmp64 > UINT32_MAX) { 857 return -EINVAL; 858 } 859 860 *mfn = (uint32_t)tmp64; 861 862 /* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */ 863 factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL; 864 factor64 += ((uint64_t)*mfi) * FP_PRECISION; 865 factor64 *= 2ULL; 866 ofreq = (((uint64_t)in) * FP_PRECISION) / factor64; 867 868 if (ofreq != dfs_div->freq) { 869 ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n", 870 dfs_div->freq); 871 ERROR("Nearest freq = %" PRIx64 "\n", ofreq); 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static int init_dfs_port(uintptr_t dfs_addr, uint32_t port, 879 uint32_t mfi, uint32_t mfn) 880 { 881 uint32_t portsr, portolsr; 882 uint32_t mask, old_mfi, old_mfn; 883 uint32_t dvport; 884 bool init_dfs; 885 886 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port)); 887 888 old_mfi = DFS_DVPORTn_MFI(dvport); 889 old_mfn = DFS_DVPORTn_MFN(dvport); 890 891 portsr = mmio_read_32(DFS_PORTSR(dfs_addr)); 892 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 893 894 /* Skip configuration if it's not needed */ 895 if (((portsr & BIT_32(port)) != 0U) && 896 ((portolsr & BIT_32(port)) == 0U) && 897 (mfi == old_mfi) && (mfn == old_mfn)) { 898 return 0; 899 } 900 901 init_dfs = (portsr == 0U); 902 903 if (init_dfs) { 904 mask = DFS_PORTRESET_MASK; 905 } else { 906 mask = DFS_PORTRESET_SET(BIT_32(port)); 907 } 908 909 mmio_write_32(DFS_PORTOLSR(dfs_addr), mask); 910 mmio_write_32(DFS_PORTRESET(dfs_addr), mask); 911 912 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) { 913 } 914 915 if (init_dfs) { 916 mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 917 } 918 919 mmio_write_32(DFS_DVPORTn(dfs_addr, port), 920 DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn)); 921 922 if (init_dfs) { 923 /* DFS clk enable programming */ 924 mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 925 } 926 927 mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port)); 928 929 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) { 930 } 931 932 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 933 if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) { 934 ERROR("Failed to lock DFS divider\n"); 935 return -EINVAL; 936 } 937 938 return 0; 939 } 940 941 static struct s32cc_clk_obj * 942 get_dfs_div_parent(const struct s32cc_clk_obj *module) 943 { 944 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 945 946 if (dfs_div->parent == NULL) { 947 ERROR("Failed to identify DFS divider's parent\n"); 948 } 949 950 return dfs_div->parent; 951 } 952 953 static int enable_dfs_div(struct s32cc_clk_obj *module, 954 const struct s32cc_clk_drv *drv, 955 unsigned int depth) 956 { 957 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 958 unsigned int ldepth = depth; 959 const struct s32cc_dfs *dfs; 960 uintptr_t dfs_addr = 0UL; 961 unsigned long dfs_freq; 962 uint32_t mfi, mfn; 963 int ret = 0; 964 965 ret = update_stack_depth(&ldepth); 966 if (ret != 0) { 967 return ret; 968 } 969 970 dfs = get_div_dfs(dfs_div); 971 if (dfs == NULL) { 972 return -EINVAL; 973 } 974 975 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 976 if ((ret != 0) || (dfs_addr == 0UL)) { 977 return -EINVAL; 978 } 979 980 ret = get_module_rate(&dfs->desc, drv, &dfs_freq, depth); 981 if (ret != 0) { 982 return ret; 983 } 984 985 ret = get_dfs_mfi_mfn(dfs_freq, dfs_div, &mfi, &mfn); 986 if (ret != 0) { 987 return -EINVAL; 988 } 989 990 return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn); 991 } 992 993 typedef int (*enable_clk_t)(struct s32cc_clk_obj *module, 994 const struct s32cc_clk_drv *drv, 995 unsigned int depth); 996 997 static int enable_part(struct s32cc_clk_obj *module, 998 const struct s32cc_clk_drv *drv, 999 unsigned int depth) 1000 { 1001 const struct s32cc_part *part = s32cc_obj2part(module); 1002 uint32_t part_no = part->partition_id; 1003 1004 if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) { 1005 return -EINVAL; 1006 } 1007 1008 return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no); 1009 } 1010 1011 static int enable_part_block(struct s32cc_clk_obj *module, 1012 const struct s32cc_clk_drv *drv, 1013 unsigned int depth) 1014 { 1015 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 1016 const struct s32cc_part *part = block->part; 1017 uint32_t part_no = part->partition_id; 1018 unsigned int ldepth = depth; 1019 uint32_t cofb; 1020 int ret; 1021 1022 ret = update_stack_depth(&ldepth); 1023 if (ret != 0) { 1024 return ret; 1025 } 1026 1027 if ((block->block >= s32cc_part_block0) && 1028 (block->block <= s32cc_part_block15)) { 1029 cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0; 1030 mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status); 1031 } else { 1032 ERROR("Unknown partition block type: %d\n", block->block); 1033 return -EINVAL; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static struct s32cc_clk_obj * 1040 get_part_block_parent(const struct s32cc_clk_obj *module) 1041 { 1042 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 1043 1044 return &block->part->desc; 1045 } 1046 1047 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1048 const struct s32cc_clk_drv *drv, 1049 unsigned int depth); 1050 1051 static int enable_part_block_link(struct s32cc_clk_obj *module, 1052 const struct s32cc_clk_drv *drv, 1053 unsigned int depth) 1054 { 1055 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 1056 struct s32cc_part_block *block = link->block; 1057 unsigned int ldepth = depth; 1058 int ret; 1059 1060 ret = update_stack_depth(&ldepth); 1061 if (ret != 0) { 1062 return ret; 1063 } 1064 1065 /* Move the enablement algorithm to partition tree */ 1066 return enable_module_with_refcount(&block->desc, drv, ldepth); 1067 } 1068 1069 static struct s32cc_clk_obj * 1070 get_part_block_link_parent(const struct s32cc_clk_obj *module) 1071 { 1072 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 1073 1074 return link->parent; 1075 } 1076 1077 static int get_part_block_link_freq(const struct s32cc_clk_obj *module, 1078 const struct s32cc_clk_drv *drv, 1079 unsigned long *rate, unsigned int depth) 1080 { 1081 const struct s32cc_part_block_link *block = s32cc_obj2partblocklink(module); 1082 unsigned int ldepth = depth; 1083 int ret; 1084 1085 ret = update_stack_depth(&ldepth); 1086 if (ret != 0) { 1087 return ret; 1088 } 1089 1090 return get_module_rate(block->parent, drv, rate, ldepth); 1091 } 1092 1093 static void cgm_mux_div_config(uintptr_t cgm_addr, uint32_t mux, 1094 uint32_t dc, uint32_t div_index) 1095 { 1096 uint32_t updstat; 1097 uint32_t dc_val = mmio_read_32(MC_CGM_MUXn_DCm(cgm_addr, mux, div_index)); 1098 1099 dc_val &= (MC_CGM_MUXn_DCm_DIV_MASK | MC_CGM_MUXn_DCm_DE); 1100 1101 if (dc_val == (MC_CGM_MUXn_DCm_DE | MC_CGM_MUXn_DCm_DIV_SET(dc))) { 1102 return; 1103 } 1104 1105 /* Set the divider */ 1106 mmio_write_32(MC_CGM_MUXn_DCm(cgm_addr, mux, div_index), 1107 MC_CGM_MUXn_DCm_DE | MC_CGM_MUXn_DCm_DIV_SET(dc)); 1108 1109 /* Wait for divider to get updated */ 1110 do { 1111 updstat = mmio_read_32(MC_CGM_MUXn_DIV_UPD_STAT(cgm_addr, mux)); 1112 } while (MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT(updstat) != 0U); 1113 } 1114 1115 static inline struct s32cc_clkmux *get_cgm_div_mux(const struct s32cc_cgm_div *cgm_div) 1116 { 1117 const struct s32cc_clk_obj *parent = cgm_div->parent; 1118 const struct s32cc_clk_obj *mux_obj; 1119 const struct s32cc_clk *clk; 1120 1121 if (parent == NULL) { 1122 ERROR("Failed to identify CGM DIV's parent\n"); 1123 return NULL; 1124 } 1125 1126 if (parent->type != s32cc_clk_t) { 1127 ERROR("The parent of the CGM DIV isn't a clock\n"); 1128 return NULL; 1129 } 1130 1131 clk = s32cc_obj2clk(parent); 1132 1133 if (clk->module == NULL) { 1134 ERROR("The clock isn't connected to a module\n"); 1135 return NULL; 1136 } 1137 1138 mux_obj = clk->module; 1139 1140 if ((mux_obj->type != s32cc_clkmux_t) && 1141 (mux_obj->type != s32cc_shared_clkmux_t)) { 1142 ERROR("The parent of the CGM DIV isn't a MUX\n"); 1143 return NULL; 1144 } 1145 1146 return s32cc_obj2clkmux(mux_obj); 1147 } 1148 1149 static int enable_cgm_div(struct s32cc_clk_obj *module, 1150 const struct s32cc_clk_drv *drv, unsigned int depth) 1151 { 1152 const struct s32cc_cgm_div *cgm_div = s32cc_obj2cgmdiv(module); 1153 const struct s32cc_clkmux *mux; 1154 unsigned int ldepth = depth; 1155 uintptr_t cgm_addr = 0ULL; 1156 uint64_t pfreq, dc64; 1157 uint32_t dc; 1158 int ret; 1159 1160 ret = update_stack_depth(&ldepth); 1161 if (ret != 0) { 1162 return ret; 1163 } 1164 1165 if (cgm_div->parent == NULL) { 1166 ERROR("Failed to identify CGM divider's parent\n"); 1167 return -EINVAL; 1168 } 1169 1170 if (cgm_div->freq == 0U) { 1171 ERROR("The frequency of the divider %" PRIu32 " is not set\n", 1172 cgm_div->index); 1173 return -EINVAL; 1174 } 1175 1176 mux = get_cgm_div_mux(cgm_div); 1177 if (mux == NULL) { 1178 return -EINVAL; 1179 } 1180 1181 ret = get_base_addr(mux->module, drv, &cgm_addr); 1182 if (ret != 0) { 1183 ERROR("Failed to get CGM base address of the MUX module %d\n", 1184 mux->module); 1185 return ret; 1186 } 1187 1188 ret = get_module_rate(cgm_div->parent, drv, &pfreq, ldepth); 1189 if (ret != 0) { 1190 ERROR("Failed to enable the div due to unknown frequency of " 1191 "the CGM MUX %" PRIu8 "(CGM=%" PRIxPTR ")\n", 1192 mux->index, cgm_addr); 1193 return -EINVAL; 1194 } 1195 1196 dc64 = ((pfreq * FP_PRECISION) / cgm_div->freq) / FP_PRECISION; 1197 dc = (uint32_t)dc64; 1198 1199 if ((pfreq / dc64) != cgm_div->freq) { 1200 ERROR("Cannot set CGM divider (mux:%" PRIu8 ", div:%" PRIu32 1201 ") for input = %lu & output = %lu, Nearest freq = %lu\n", 1202 mux->index, cgm_div->index, (unsigned long)pfreq, 1203 cgm_div->freq, (unsigned long)(pfreq / dc)); 1204 return -EINVAL; 1205 } 1206 1207 cgm_mux_div_config(cgm_addr, mux->index, dc - 1U, cgm_div->index); 1208 return 0; 1209 } 1210 1211 static int set_cgm_div_freq(const struct s32cc_clk_obj *module, 1212 unsigned long rate, unsigned long *orate, 1213 unsigned int *depth) 1214 { 1215 struct s32cc_cgm_div *cgm_div = s32cc_obj2cgmdiv(module); 1216 int ret; 1217 1218 ret = update_stack_depth(depth); 1219 if (ret != 0) { 1220 return ret; 1221 } 1222 1223 if (cgm_div->parent == NULL) { 1224 ERROR("Failed to identify the CGM divider's parent\n"); 1225 return -EINVAL; 1226 } 1227 1228 cgm_div->freq = rate; 1229 *orate = rate; 1230 1231 return 0; 1232 } 1233 1234 static int no_enable(struct s32cc_clk_obj *module, 1235 const struct s32cc_clk_drv *drv, 1236 unsigned int depth) 1237 { 1238 return 0; 1239 } 1240 1241 static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod, 1242 const struct s32cc_clk_drv *drv, bool leaf_node, 1243 unsigned int depth) 1244 { 1245 unsigned int ldepth = depth; 1246 int ret = 0; 1247 1248 if (mod == NULL) { 1249 return 0; 1250 } 1251 1252 ret = update_stack_depth(&ldepth); 1253 if (ret != 0) { 1254 return ret; 1255 } 1256 1257 /* Refcount will be updated as part of the recursivity */ 1258 if (leaf_node) { 1259 return en_cb(mod, drv, ldepth); 1260 } 1261 1262 if (mod->refcount == 0U) { 1263 ret = en_cb(mod, drv, ldepth); 1264 } 1265 1266 if (ret == 0) { 1267 mod->refcount++; 1268 } 1269 1270 return ret; 1271 } 1272 1273 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module); 1274 1275 static int enable_module(struct s32cc_clk_obj *module, 1276 const struct s32cc_clk_drv *drv, 1277 unsigned int depth) 1278 { 1279 struct s32cc_clk_obj *parent = get_module_parent(module); 1280 static const enable_clk_t enable_clbs[13] = { 1281 [s32cc_clk_t] = no_enable, 1282 [s32cc_osc_t] = enable_osc, 1283 [s32cc_pll_t] = enable_pll, 1284 [s32cc_pll_out_div_t] = enable_pll_div, 1285 [s32cc_clkmux_t] = enable_mux, 1286 [s32cc_shared_clkmux_t] = enable_mux, 1287 [s32cc_dfs_t] = enable_dfs, 1288 [s32cc_dfs_div_t] = enable_dfs_div, 1289 [s32cc_part_t] = enable_part, 1290 [s32cc_part_block_t] = enable_part_block, 1291 [s32cc_part_block_link_t] = enable_part_block_link, 1292 [s32cc_cgm_div_t] = enable_cgm_div, 1293 }; 1294 unsigned int ldepth = depth; 1295 uint32_t index; 1296 int ret = 0; 1297 1298 ret = update_stack_depth(&ldepth); 1299 if (ret != 0) { 1300 return ret; 1301 } 1302 1303 if (drv == NULL) { 1304 return -EINVAL; 1305 } 1306 1307 index = (uint32_t)module->type; 1308 1309 if (index >= ARRAY_SIZE(enable_clbs)) { 1310 ERROR("Undefined module type: %d\n", module->type); 1311 return -EINVAL; 1312 } 1313 1314 if (enable_clbs[index] == NULL) { 1315 ERROR("Undefined callback for the clock type: %d\n", 1316 module->type); 1317 return -EINVAL; 1318 } 1319 1320 parent = get_module_parent(module); 1321 1322 ret = exec_cb_with_refcount(enable_module, parent, drv, 1323 false, ldepth); 1324 if (ret != 0) { 1325 return ret; 1326 } 1327 1328 ret = exec_cb_with_refcount(enable_clbs[index], module, drv, 1329 true, ldepth); 1330 if (ret != 0) { 1331 return ret; 1332 } 1333 1334 return ret; 1335 } 1336 1337 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1338 const struct s32cc_clk_drv *drv, 1339 unsigned int depth) 1340 { 1341 return exec_cb_with_refcount(enable_module, module, drv, false, depth); 1342 } 1343 1344 static int s32cc_clk_enable(unsigned long id) 1345 { 1346 const struct s32cc_clk_drv *drv = get_drv(); 1347 unsigned int depth = MAX_STACK_DEPTH; 1348 struct s32cc_clk *clk; 1349 1350 clk = s32cc_get_arch_clk(id); 1351 if (clk == NULL) { 1352 return -EINVAL; 1353 } 1354 1355 return enable_module_with_refcount(&clk->desc, drv, depth); 1356 } 1357 1358 static void s32cc_clk_disable(unsigned long id) 1359 { 1360 } 1361 1362 static bool s32cc_clk_is_enabled(unsigned long id) 1363 { 1364 return false; 1365 } 1366 1367 static int set_osc_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1368 unsigned long *orate, unsigned int *depth) 1369 { 1370 struct s32cc_osc *osc = s32cc_obj2osc(module); 1371 int ret; 1372 1373 ret = update_stack_depth(depth); 1374 if (ret != 0) { 1375 return ret; 1376 } 1377 1378 if ((osc->freq != 0UL) && (rate != osc->freq)) { 1379 ERROR("Already initialized oscillator. freq = %lu\n", 1380 osc->freq); 1381 return -EINVAL; 1382 } 1383 1384 osc->freq = rate; 1385 *orate = osc->freq; 1386 1387 return 0; 1388 } 1389 1390 static int get_osc_freq(const struct s32cc_clk_obj *module, 1391 const struct s32cc_clk_drv *drv, 1392 unsigned long *rate, unsigned int depth) 1393 { 1394 const struct s32cc_osc *osc = s32cc_obj2osc(module); 1395 unsigned int ldepth = depth; 1396 int ret; 1397 1398 ret = update_stack_depth(&ldepth); 1399 if (ret != 0) { 1400 return ret; 1401 } 1402 1403 if (osc->freq == 0UL) { 1404 ERROR("Uninitialized oscillator\n"); 1405 return -EINVAL; 1406 } 1407 1408 *rate = osc->freq; 1409 1410 return 0; 1411 } 1412 1413 static int set_clk_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1414 unsigned long *orate, unsigned int *depth) 1415 { 1416 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1417 int ret; 1418 1419 ret = update_stack_depth(depth); 1420 if (ret != 0) { 1421 return ret; 1422 } 1423 1424 if ((clk->min_freq != 0UL) && (clk->max_freq != 0UL) && 1425 ((rate < clk->min_freq) || (rate > clk->max_freq))) { 1426 ERROR("%lu frequency is out of the allowed range: [%lu:%lu]\n", 1427 rate, clk->min_freq, clk->max_freq); 1428 return -EINVAL; 1429 } 1430 1431 if (clk->module != NULL) { 1432 return set_module_rate(clk->module, rate, orate, depth); 1433 } 1434 1435 if (clk->pclock != NULL) { 1436 return set_clk_freq(&clk->pclock->desc, rate, orate, depth); 1437 } 1438 1439 return -EINVAL; 1440 } 1441 1442 static int get_clk_freq(const struct s32cc_clk_obj *module, 1443 const struct s32cc_clk_drv *drv, unsigned long *rate, 1444 unsigned int depth) 1445 { 1446 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1447 unsigned int ldepth = depth; 1448 int ret; 1449 1450 ret = update_stack_depth(&ldepth); 1451 if (ret != 0) { 1452 return ret; 1453 } 1454 1455 if (clk == NULL) { 1456 ERROR("Invalid clock\n"); 1457 return -EINVAL; 1458 } 1459 1460 if (clk->module != NULL) { 1461 return get_module_rate(clk->module, drv, rate, ldepth); 1462 } 1463 1464 if (clk->pclock == NULL) { 1465 ERROR("Invalid clock parent\n"); 1466 return -EINVAL; 1467 } 1468 1469 return get_clk_freq(&clk->pclock->desc, drv, rate, ldepth); 1470 } 1471 1472 static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1473 unsigned long *orate, unsigned int *depth) 1474 { 1475 struct s32cc_pll *pll = s32cc_obj2pll(module); 1476 int ret; 1477 1478 ret = update_stack_depth(depth); 1479 if (ret != 0) { 1480 return ret; 1481 } 1482 1483 if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) { 1484 ERROR("PLL frequency was already set\n"); 1485 return -EINVAL; 1486 } 1487 1488 pll->vco_freq = rate; 1489 *orate = pll->vco_freq; 1490 1491 return 0; 1492 } 1493 1494 static int get_pll_freq(const struct s32cc_clk_obj *module, 1495 const struct s32cc_clk_drv *drv, 1496 unsigned long *rate, unsigned int depth) 1497 { 1498 const struct s32cc_pll *pll = s32cc_obj2pll(module); 1499 const struct s32cc_clk *source; 1500 uint32_t mfi, mfn, rdiv, plldv; 1501 unsigned long prate, clk_src; 1502 unsigned int ldepth = depth; 1503 uintptr_t pll_addr = 0UL; 1504 uint64_t t1, t2; 1505 int ret; 1506 1507 ret = update_stack_depth(&ldepth); 1508 if (ret != 0) { 1509 return ret; 1510 } 1511 1512 ret = get_base_addr(pll->instance, drv, &pll_addr); 1513 if (ret != 0) { 1514 ERROR("Failed to detect PLL instance\n"); 1515 return ret; 1516 } 1517 1518 /* Disabled PLL */ 1519 if (!is_pll_enabled(pll_addr)) { 1520 *rate = pll->vco_freq; 1521 return 0; 1522 } 1523 1524 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 1525 switch (clk_src) { 1526 case 0: 1527 clk_src = S32CC_CLK_FIRC; 1528 break; 1529 case 1: 1530 clk_src = S32CC_CLK_FXOSC; 1531 break; 1532 default: 1533 ERROR("Failed to identify PLL source id %" PRIu64 "\n", clk_src); 1534 return -EINVAL; 1535 }; 1536 1537 source = s32cc_get_arch_clk(clk_src); 1538 if (source == NULL) { 1539 ERROR("Failed to get PLL source clock\n"); 1540 return -EINVAL; 1541 } 1542 1543 ret = get_module_rate(&source->desc, drv, &prate, ldepth); 1544 if (ret != 0) { 1545 ERROR("Failed to get PLL's parent frequency\n"); 1546 return ret; 1547 } 1548 1549 plldv = mmio_read_32(PLLDIG_PLLDV(pll_addr)); 1550 mfi = PLLDIG_PLLDV_MFI(plldv); 1551 rdiv = PLLDIG_PLLDV_RDIV(plldv); 1552 if (rdiv == 0U) { 1553 rdiv = 1; 1554 } 1555 1556 /* Frac-N mode */ 1557 mfn = PLLDIG_PLLFD_MFN_SET(mmio_read_32(PLLDIG_PLLFD(pll_addr))); 1558 1559 /* PLL VCO frequency in Fractional mode when PLLDV[RDIV] is not 0 */ 1560 t1 = prate / rdiv; 1561 t2 = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 18432U); 1562 1563 *rate = t1 * t2 / FP_PRECISION; 1564 1565 return 0; 1566 } 1567 1568 static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1569 unsigned long *orate, unsigned int *depth) 1570 { 1571 struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1572 const struct s32cc_pll *pll; 1573 unsigned long prate, dc; 1574 int ret; 1575 1576 ret = update_stack_depth(depth); 1577 if (ret != 0) { 1578 return ret; 1579 } 1580 1581 if (pdiv->parent == NULL) { 1582 ERROR("Failed to identify PLL divider's parent\n"); 1583 return -EINVAL; 1584 } 1585 1586 pll = s32cc_obj2pll(pdiv->parent); 1587 if (pll == NULL) { 1588 ERROR("The parent of the PLL DIV is invalid\n"); 1589 return -EINVAL; 1590 } 1591 1592 prate = pll->vco_freq; 1593 1594 /** 1595 * The PLL is not initialized yet, so let's take a risk 1596 * and accept the proposed rate. 1597 */ 1598 if (prate == 0UL) { 1599 pdiv->freq = rate; 1600 *orate = rate; 1601 return 0; 1602 } 1603 1604 /* Decline in case the rate cannot fit PLL's requirements. */ 1605 dc = prate / rate; 1606 if ((prate / dc) != rate) { 1607 return -EINVAL; 1608 } 1609 1610 pdiv->freq = rate; 1611 *orate = pdiv->freq; 1612 1613 return 0; 1614 } 1615 1616 static int get_pll_div_freq(const struct s32cc_clk_obj *module, 1617 const struct s32cc_clk_drv *drv, 1618 unsigned long *rate, unsigned int depth) 1619 { 1620 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1621 const struct s32cc_pll *pll; 1622 unsigned int ldepth = depth; 1623 uintptr_t pll_addr = 0UL; 1624 unsigned long pfreq; 1625 uint32_t pllodiv; 1626 uint32_t dc; 1627 int ret; 1628 1629 ret = update_stack_depth(&ldepth); 1630 if (ret != 0) { 1631 return ret; 1632 } 1633 1634 pll = get_div_pll(pdiv); 1635 if (pll == NULL) { 1636 ERROR("The parent of the PLL DIV is invalid\n"); 1637 return -EINVAL; 1638 } 1639 1640 ret = get_base_addr(pll->instance, drv, &pll_addr); 1641 if (ret != 0) { 1642 ERROR("Failed to detect PLL instance\n"); 1643 return -EINVAL; 1644 } 1645 1646 ret = get_module_rate(pdiv->parent, drv, &pfreq, ldepth); 1647 if (ret != 0) { 1648 ERROR("Failed to get the frequency of PLL %" PRIxPTR "\n", 1649 pll_addr); 1650 return ret; 1651 } 1652 1653 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index)); 1654 1655 /* Disabled module */ 1656 if ((pllodiv & PLLDIG_PLLODIV_DE) == 0U) { 1657 *rate = pdiv->freq; 1658 return 0; 1659 } 1660 1661 dc = PLLDIG_PLLODIV_DIV(pllodiv); 1662 *rate = (pfreq * FP_PRECISION) / (dc + 1U) / FP_PRECISION; 1663 1664 return 0; 1665 } 1666 1667 static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1668 unsigned long *orate, unsigned int *depth) 1669 { 1670 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1671 int ret; 1672 1673 ret = update_stack_depth(depth); 1674 if (ret != 0) { 1675 return ret; 1676 } 1677 1678 if (fdiv->parent == NULL) { 1679 ERROR("The divider doesn't have a valid parent\b"); 1680 return -EINVAL; 1681 } 1682 1683 ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth); 1684 1685 /* Update the output rate based on the parent's rate */ 1686 *orate /= fdiv->rate_div; 1687 1688 return ret; 1689 } 1690 1691 static int get_fixed_div_freq(const struct s32cc_clk_obj *module, 1692 const struct s32cc_clk_drv *drv, 1693 unsigned long *rate, unsigned int depth) 1694 { 1695 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1696 unsigned long pfreq; 1697 int ret; 1698 1699 ret = get_module_rate(fdiv->parent, drv, &pfreq, depth); 1700 if (ret != 0) { 1701 return ret; 1702 } 1703 1704 *rate = (pfreq * FP_PRECISION / fdiv->rate_div) / FP_PRECISION; 1705 return 0; 1706 } 1707 1708 static inline struct s32cc_clk_obj *get_fixed_div_parent(const struct s32cc_clk_obj *module) 1709 { 1710 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1711 1712 return fdiv->parent; 1713 } 1714 1715 static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1716 unsigned long *orate, unsigned int *depth) 1717 { 1718 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1719 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1720 int ret; 1721 1722 ret = update_stack_depth(depth); 1723 if (ret != 0) { 1724 return ret; 1725 } 1726 1727 if (clk == NULL) { 1728 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1729 mux->index, mux->source_id); 1730 return -EINVAL; 1731 } 1732 1733 return set_module_rate(&clk->desc, rate, orate, depth); 1734 } 1735 1736 static int get_mux_freq(const struct s32cc_clk_obj *module, 1737 const struct s32cc_clk_drv *drv, 1738 unsigned long *rate, unsigned int depth) 1739 { 1740 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1741 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1742 unsigned int ldepth = depth; 1743 int ret; 1744 1745 ret = update_stack_depth(&ldepth); 1746 if (ret != 0) { 1747 return ret; 1748 } 1749 1750 if (clk == NULL) { 1751 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1752 mux->index, mux->source_id); 1753 return -EINVAL; 1754 } 1755 1756 return get_clk_freq(&clk->desc, drv, rate, ldepth); 1757 } 1758 1759 static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1760 unsigned long *orate, unsigned int *depth) 1761 { 1762 struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1763 const struct s32cc_dfs *dfs; 1764 int ret; 1765 1766 ret = update_stack_depth(depth); 1767 if (ret != 0) { 1768 return ret; 1769 } 1770 1771 if (dfs_div->parent == NULL) { 1772 ERROR("Failed to identify DFS divider's parent\n"); 1773 return -EINVAL; 1774 } 1775 1776 /* Sanity check */ 1777 dfs = s32cc_obj2dfs(dfs_div->parent); 1778 if (dfs->parent == NULL) { 1779 ERROR("Failed to identify DFS's parent\n"); 1780 return -EINVAL; 1781 } 1782 1783 if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) { 1784 ERROR("DFS DIV frequency was already set to %lu\n", 1785 dfs_div->freq); 1786 return -EINVAL; 1787 } 1788 1789 dfs_div->freq = rate; 1790 *orate = rate; 1791 1792 return ret; 1793 } 1794 1795 static unsigned long compute_dfs_div_freq(unsigned long pfreq, uint32_t mfi, uint32_t mfn) 1796 { 1797 unsigned long freq; 1798 1799 /** 1800 * Formula for input and output clocks of each port divider. 1801 * See 'Digital Frequency Synthesizer' chapter from Reference Manual. 1802 * 1803 * freq = pfreq / (2 * (mfi + mfn / 36.0)); 1804 */ 1805 freq = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 36UL); 1806 freq *= 2UL; 1807 freq = pfreq * FP_PRECISION / freq; 1808 1809 return freq; 1810 } 1811 1812 static int get_dfs_div_freq(const struct s32cc_clk_obj *module, 1813 const struct s32cc_clk_drv *drv, 1814 unsigned long *rate, unsigned int depth) 1815 { 1816 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1817 unsigned int ldepth = depth; 1818 const struct s32cc_dfs *dfs; 1819 uint32_t dvport, mfi, mfn; 1820 uintptr_t dfs_addr = 0UL; 1821 unsigned long pfreq; 1822 int ret; 1823 1824 ret = update_stack_depth(&ldepth); 1825 if (ret != 0) { 1826 return ret; 1827 } 1828 1829 dfs = get_div_dfs(dfs_div); 1830 if (dfs == NULL) { 1831 return -EINVAL; 1832 } 1833 1834 ret = get_module_rate(dfs_div->parent, drv, &pfreq, ldepth); 1835 if (ret != 0) { 1836 return ret; 1837 } 1838 1839 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 1840 if (ret != 0) { 1841 ERROR("Failed to detect the DFS instance\n"); 1842 return ret; 1843 } 1844 1845 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, dfs_div->index)); 1846 1847 mfi = DFS_DVPORTn_MFI(dvport); 1848 mfn = DFS_DVPORTn_MFN(dvport); 1849 1850 /* Disabled port */ 1851 if ((mfi == 0U) && (mfn == 0U)) { 1852 *rate = dfs_div->freq; 1853 return 0; 1854 } 1855 1856 *rate = compute_dfs_div_freq(pfreq, mfi, mfn); 1857 return 0; 1858 } 1859 1860 static int set_part_block_link_freq(const struct s32cc_clk_obj *module, 1861 unsigned long rate, unsigned long *orate, 1862 const unsigned int *depth) 1863 { 1864 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 1865 const struct s32cc_clk_obj *parent = link->parent; 1866 unsigned int ldepth = *depth; 1867 int ret; 1868 1869 ret = update_stack_depth(&ldepth); 1870 if (ret != 0) { 1871 return ret; 1872 } 1873 1874 if (parent == NULL) { 1875 ERROR("Partition block link with no parent\n"); 1876 return -EINVAL; 1877 } 1878 1879 return set_module_rate(parent, rate, orate, &ldepth); 1880 } 1881 1882 static int set_module_rate(const struct s32cc_clk_obj *module, 1883 unsigned long rate, unsigned long *orate, 1884 unsigned int *depth) 1885 { 1886 int ret = 0; 1887 1888 ret = update_stack_depth(depth); 1889 if (ret != 0) { 1890 return ret; 1891 } 1892 1893 ret = -EINVAL; 1894 1895 switch (module->type) { 1896 case s32cc_clk_t: 1897 ret = set_clk_freq(module, rate, orate, depth); 1898 break; 1899 case s32cc_osc_t: 1900 ret = set_osc_freq(module, rate, orate, depth); 1901 break; 1902 case s32cc_pll_t: 1903 ret = set_pll_freq(module, rate, orate, depth); 1904 break; 1905 case s32cc_pll_out_div_t: 1906 ret = set_pll_div_freq(module, rate, orate, depth); 1907 break; 1908 case s32cc_fixed_div_t: 1909 ret = set_fixed_div_freq(module, rate, orate, depth); 1910 break; 1911 case s32cc_clkmux_t: 1912 ret = set_mux_freq(module, rate, orate, depth); 1913 break; 1914 case s32cc_shared_clkmux_t: 1915 ret = set_mux_freq(module, rate, orate, depth); 1916 break; 1917 case s32cc_cgm_div_t: 1918 ret = set_cgm_div_freq(module, rate, orate, depth); 1919 break; 1920 case s32cc_dfs_t: 1921 ERROR("Setting the frequency of a DFS is not allowed!"); 1922 break; 1923 case s32cc_dfs_div_t: 1924 ret = set_dfs_div_freq(module, rate, orate, depth); 1925 break; 1926 case s32cc_part_block_link_t: 1927 ret = set_part_block_link_freq(module, rate, orate, depth); 1928 break; 1929 case s32cc_part_t: 1930 ERROR("It's not allowed to set the frequency of a partition !"); 1931 break; 1932 case s32cc_part_block_t: 1933 ERROR("It's not allowed to set the frequency of a partition block !"); 1934 break; 1935 default: 1936 break; 1937 } 1938 1939 return ret; 1940 } 1941 1942 static int get_module_rate(const struct s32cc_clk_obj *module, 1943 const struct s32cc_clk_drv *drv, 1944 unsigned long *rate, 1945 unsigned int depth) 1946 { 1947 unsigned int ldepth = depth; 1948 int ret = 0; 1949 1950 ret = update_stack_depth(&ldepth); 1951 if (ret != 0) { 1952 return ret; 1953 } 1954 1955 switch (module->type) { 1956 case s32cc_osc_t: 1957 ret = get_osc_freq(module, drv, rate, ldepth); 1958 break; 1959 case s32cc_clk_t: 1960 ret = get_clk_freq(module, drv, rate, ldepth); 1961 break; 1962 case s32cc_pll_t: 1963 ret = get_pll_freq(module, drv, rate, ldepth); 1964 break; 1965 case s32cc_dfs_t: 1966 ret = get_dfs_freq(module, drv, rate, ldepth); 1967 break; 1968 case s32cc_dfs_div_t: 1969 ret = get_dfs_div_freq(module, drv, rate, ldepth); 1970 break; 1971 case s32cc_fixed_div_t: 1972 ret = get_fixed_div_freq(module, drv, rate, ldepth); 1973 break; 1974 case s32cc_pll_out_div_t: 1975 ret = get_pll_div_freq(module, drv, rate, ldepth); 1976 break; 1977 case s32cc_clkmux_t: 1978 ret = get_mux_freq(module, drv, rate, ldepth); 1979 break; 1980 case s32cc_shared_clkmux_t: 1981 ret = get_mux_freq(module, drv, rate, ldepth); 1982 break; 1983 case s32cc_part_t: 1984 ERROR("s32cc_part_t cannot be used to get rate\n"); 1985 break; 1986 case s32cc_part_block_t: 1987 ERROR("s32cc_part_block_t cannot be used to get rate\n"); 1988 break; 1989 case s32cc_part_block_link_t: 1990 ret = get_part_block_link_freq(module, drv, rate, ldepth); 1991 break; 1992 default: 1993 ret = -EINVAL; 1994 break; 1995 } 1996 1997 return ret; 1998 } 1999 2000 static int s32cc_clk_set_rate(unsigned long id, unsigned long rate, 2001 unsigned long *orate) 2002 { 2003 unsigned int depth = MAX_STACK_DEPTH; 2004 const struct s32cc_clk *clk; 2005 int ret; 2006 2007 clk = s32cc_get_arch_clk(id); 2008 if (clk == NULL) { 2009 return -EINVAL; 2010 } 2011 2012 ret = set_module_rate(&clk->desc, rate, orate, &depth); 2013 if (ret != 0) { 2014 ERROR("Failed to set frequency (%lu MHz) for clock %lu\n", 2015 rate, id); 2016 } 2017 2018 return ret; 2019 } 2020 2021 static unsigned long s32cc_clk_get_rate(unsigned long id) 2022 { 2023 const struct s32cc_clk_drv *drv = get_drv(); 2024 unsigned int depth = MAX_STACK_DEPTH; 2025 const struct s32cc_clk *clk; 2026 unsigned long rate = 0UL; 2027 int ret; 2028 2029 clk = s32cc_get_arch_clk(id); 2030 if (clk == NULL) { 2031 return 0; 2032 } 2033 2034 ret = get_module_rate(&clk->desc, drv, &rate, depth); 2035 if (ret != 0) { 2036 ERROR("Failed to get frequency (%lu MHz) for clock %lu\n", 2037 rate, id); 2038 return 0; 2039 } 2040 2041 return rate; 2042 } 2043 2044 static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module) 2045 { 2046 return NULL; 2047 } 2048 2049 typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj); 2050 2051 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module) 2052 { 2053 static const get_parent_clb_t parents_clbs[13] = { 2054 [s32cc_clk_t] = get_clk_parent, 2055 [s32cc_osc_t] = get_no_parent, 2056 [s32cc_pll_t] = get_pll_parent, 2057 [s32cc_pll_out_div_t] = get_pll_div_parent, 2058 [s32cc_clkmux_t] = get_mux_parent, 2059 [s32cc_shared_clkmux_t] = get_mux_parent, 2060 [s32cc_dfs_t] = get_dfs_parent, 2061 [s32cc_dfs_div_t] = get_dfs_div_parent, 2062 [s32cc_part_t] = get_no_parent, 2063 [s32cc_fixed_div_t] = get_fixed_div_parent, 2064 [s32cc_part_block_t] = get_part_block_parent, 2065 [s32cc_part_block_link_t] = get_part_block_link_parent, 2066 }; 2067 uint32_t index; 2068 2069 if (module == NULL) { 2070 return NULL; 2071 } 2072 2073 index = (uint32_t)module->type; 2074 2075 if (index >= ARRAY_SIZE(parents_clbs)) { 2076 ERROR("Undefined module type: %d\n", module->type); 2077 return NULL; 2078 } 2079 2080 if (parents_clbs[index] == NULL) { 2081 ERROR("Undefined parent getter for type: %d\n", module->type); 2082 return NULL; 2083 } 2084 2085 return parents_clbs[index](module); 2086 } 2087 2088 static int s32cc_clk_get_parent(unsigned long id) 2089 { 2090 struct s32cc_clk *parent_clk; 2091 const struct s32cc_clk_obj *parent; 2092 const struct s32cc_clk *clk; 2093 unsigned long parent_id; 2094 int ret; 2095 2096 clk = s32cc_get_arch_clk(id); 2097 if (clk == NULL) { 2098 return -EINVAL; 2099 } 2100 2101 parent = get_module_parent(clk->module); 2102 if (parent == NULL) { 2103 return -EINVAL; 2104 } 2105 2106 parent_clk = s32cc_obj2clk(parent); 2107 if (parent_clk == NULL) { 2108 return -EINVAL; 2109 } 2110 2111 ret = s32cc_get_clk_id(parent_clk, &parent_id); 2112 if (ret != 0) { 2113 return ret; 2114 } 2115 2116 if (parent_id > (unsigned long)INT_MAX) { 2117 return -E2BIG; 2118 } 2119 2120 return (int)parent_id; 2121 } 2122 2123 static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id) 2124 { 2125 const struct s32cc_clk *parent; 2126 const struct s32cc_clk *clk; 2127 bool valid_source = false; 2128 struct s32cc_clkmux *mux; 2129 uint8_t i; 2130 2131 clk = s32cc_get_arch_clk(id); 2132 if (clk == NULL) { 2133 return -EINVAL; 2134 } 2135 2136 parent = s32cc_get_arch_clk(parent_id); 2137 if (parent == NULL) { 2138 return -EINVAL; 2139 } 2140 2141 if (!is_s32cc_clk_mux(clk)) { 2142 ERROR("Clock %lu is not a mux\n", id); 2143 return -EINVAL; 2144 } 2145 2146 mux = s32cc_clk2mux(clk); 2147 if (mux == NULL) { 2148 ERROR("Failed to cast clock %lu to clock mux\n", id); 2149 return -EINVAL; 2150 } 2151 2152 for (i = 0; i < mux->nclks; i++) { 2153 if (mux->clkids[i] == parent_id) { 2154 valid_source = true; 2155 break; 2156 } 2157 } 2158 2159 if (!valid_source) { 2160 ERROR("Clock %lu is not a valid clock for mux %lu\n", 2161 parent_id, id); 2162 return -EINVAL; 2163 } 2164 2165 mux->source_id = parent_id; 2166 2167 return 0; 2168 } 2169 2170 static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) 2171 { 2172 const uintptr_t base_addrs[12] = { 2173 drv->fxosc_base, 2174 drv->armpll_base, 2175 drv->periphpll_base, 2176 drv->armdfs_base, 2177 drv->periphdfs_base, 2178 drv->cgm0_base, 2179 drv->cgm1_base, 2180 drv->cgm5_base, 2181 drv->ddrpll_base, 2182 drv->mc_me, 2183 drv->mc_rgm, 2184 drv->rdc, 2185 }; 2186 size_t i; 2187 int ret; 2188 2189 for (i = 0U; i < ARRAY_SIZE(base_addrs); i++) { 2190 ret = mmap_add_dynamic_region(base_addrs[i], base_addrs[i], 2191 PAGE_SIZE, 2192 MT_DEVICE | MT_RW | MT_SECURE); 2193 if (ret != 0) { 2194 ERROR("Failed to map clock module 0x%" PRIuPTR "\n", 2195 base_addrs[i]); 2196 return ret; 2197 } 2198 } 2199 2200 return 0; 2201 } 2202 2203 int s32cc_clk_register_drv(bool mmap_regs) 2204 { 2205 static const struct clk_ops s32cc_clk_ops = { 2206 .enable = s32cc_clk_enable, 2207 .disable = s32cc_clk_disable, 2208 .is_enabled = s32cc_clk_is_enabled, 2209 .get_rate = s32cc_clk_get_rate, 2210 .set_rate = s32cc_clk_set_rate, 2211 .get_parent = s32cc_clk_get_parent, 2212 .set_parent = s32cc_clk_set_parent, 2213 }; 2214 const struct s32cc_clk_drv *drv; 2215 2216 clk_register(&s32cc_clk_ops); 2217 2218 drv = get_drv(); 2219 if (drv == NULL) { 2220 return -EINVAL; 2221 } 2222 2223 if (mmap_regs) { 2224 return s32cc_clk_mmap_regs(drv); 2225 } 2226 2227 return 0; 2228 } 2229 2230