Merge "feat(rcar): rewrite console_renesas_register() in C" into integration

Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto ext

Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto extension
feat(crypto): enable access to SIMD crypto in BL1 and BL2
feat(crypto): enable floating point register traps in EL3
feat(crypto): build flag for SIMD crypto extensions for v8+ platform
refactor(build): add a default filter list for lib cflags

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Merge "feat(s32g274ardb): use DDR reset deassertion" into integration

Merge "feat(rcar): test only for SCIF TX FIFO empty before writing the FIFO" into integration

feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_

feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_FEAT_CRYPTO_SHA3
to enable SIMD crypto extension for sha384 and sha512 in bootflow authentication
process for Arm platform greater than v8.0.

Change-Id: I6e52feb318136910d34cafd89319bf94f90e16fc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes I6deddab4,I432b05b2,I4af7371d,I2318ea4b into integration

* changes:
feat(rdv3): use SFCP PSA call instead of RSE comms
feat(tc): use SFCP PSA call instead of RSE comms
feat(tc):

Merge changes I6deddab4,I432b05b2,I4af7371d,I2318ea4b into integration

* changes:
feat(rdv3): use SFCP PSA call instead of RSE comms
feat(tc): use SFCP PSA call instead of RSE comms
feat(tc): add tc_sfcp.c
feat(sfcp): add SFCP stack and PSA call

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feat(rcar): test only for SCIF TX FIFO empty before writing the FIFO

Currently, the code tests both whether the SCIF TX FIFO is empty using
TDFE bit and whether the current byte transfer ended using

feat(rcar): test only for SCIF TX FIFO empty before writing the FIFO

Currently, the code tests both whether the SCIF TX FIFO is empty using
TDFE bit and whether the current byte transfer ended using TEND bit,
both before and after writing the TX FIFO. Starting with Renesas RZ/A2
platform, the TEND bit is not set after the SCIF IP is reset, it is set
only after the TX FIFO was written for the first time.

Relax the first test before TX FIFO is written such, that it only uses
the TDFE bit to verify that the TX FIFO is empty and safe to be written,
but keep both TDFE and TEND check in the second test to assure that the
character was properly transmitted after it was written into the TX FIFO.
This allows both current platforms and RZ/A2 and newer to share the same
code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I313703bd61b51b52e689fb2bb895b96096d30f22

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feat(rcar): rewrite console_renesas_register() in C

Replace assembler implementation of console_renesas_register() with
matching C implementation. Since it is now easily possible to pass
flags into

feat(rcar): rewrite console_renesas_register() in C

Replace assembler implementation of console_renesas_register() with
matching C implementation. Since it is now easily possible to pass
flags into console_renesas_register() and then onward to the console
initialization, adjust the signature of console_renesas_register()
and include the flags in it. Adjust both rcar_console_boot_init()
and rcar_console_runtime_init() to call console_renesas_register()
with its new combined set of parameters and drop console_set_scope()
invocation which is no longer needed, because the flags are passed
directly into console_renesas_register().

Drop console_renesas_flush() which is always a noop. Drop return
value from console_renesas_init() which is always 1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I1c7d1a81b6922138b6e2e80f2635fcc8558685c7

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Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add

Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add DDR training stubs

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feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now integrated into
the DDR initialization flow.

Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(sfcp): add SFCP stack and PSA call

Add SFCP stack from trusted-firmware-m commit 8eb72a3bc5cc. SFCP is the
Simple Firmware Communication Protocol, which is a more substantial
software stack des

feat(sfcp): add SFCP stack and PSA call

Add SFCP stack from trusted-firmware-m commit 8eb72a3bc5cc. SFCP is the
Simple Firmware Communication Protocol, which is a more substantial
software stack designed to replace the existing RSE comms (and indeed
wider communication between firmware components in the system). It has
support for both polling mode and interrupt driver communication
handling, and is able to support any underlying transport (this patch
adds MHU only). It requires a static routing layout between system
components.

This patch adds the link layer (with support for the MHU transport),
top-level SFCP API implementation and the implementation of PSA
call making use of the SFCP API.

Note that encryption support is not implemented and only the stub
encryption implementation is added in this patch. This can be
implemented when TF-A needs it.

The sfcp_link_hal.c implementation is the same as that in
trusted-firmware-m, and it makes use of the MHU V2 and V3 drivers
directly. This is possible as the underlying MHU driver APIs is the same
in trusted-firmware-m and trusted-firmware-a.

Change-Id: I2318ea4bdb4e533b8a4a5000040aec0635a83857
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by

feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR contr

feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR controller and prepare for PHY training.
It includes controller setup and the training
orchestration function.

Change-Id: Icd8649516d9bad1a6d72616a774b8b60c6bae067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068f

refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068fb4f523b37a9db3a4a9ce8be836a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-Id: I80b8df9a7f0058941083893d4e7bb728768ae236
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge "feat(rse): fix iovec parameter check in rse comms" into integration

feat(rse): fix iovec parameter check in rse comms

Allow NULL pointers as in/outvec pointer, but only if the
corresponding length is 0, in which case it is not used.
Introduce check for outvec as wel

feat(rse): fix iovec parameter check in rse comms

Allow NULL pointers as in/outvec pointer, but only if the
corresponding length is 0, in which case it is not used.
Introduce check for outvec as well, where NULL pointer
would cause illegal dereferencing on evaluation of
out_vec[0].base

Signed-off-by: Martin Fonai <martin.fonai@arm.com>
Change-Id: Ie5ea11ed63d942a063a9cfed8333b553b96e9924

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Merge changes from topic "upstream_ddr_reg_accesories" into integration

* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support

Merge "refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform" into integration

refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesa

refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesas platforms.

Due to the above renaming, function console_renesas_register is duplicated
in both scif.h and console.h, so it should be removed from scif.h

Change-Id: I42b44d1786578f7ed8db34e7da421836ea60b5e2
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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fix(rcar3): disable stack protector for functions in SRAM

Disable the BL31 stack protector for all functions placed in SRAM,
because the canary value in __stack_chk_guard in DRAM can not be
read whe

fix(rcar3): disable stack protector for functions in SRAM

Disable the BL31 stack protector for all functions placed in SRAM,
because the canary value in __stack_chk_guard in DRAM can not be
read when running Suspend To RAM code from SRAM. The SSP functions
in DRAM can also not be called from that code. Make sure the code
in SRAM is self-contained by marking rcar_pwrc_go_suspend_to_ram()
as noinline. To assure the stack protector is active otherwise,
use no_stack_protector function attribute for the select functions
which are placed in SRAM.

Change-Id: Idc43e70fd5217ea130a48c46f227a37c568dc8bd
Fixes: cfa466ab733f ("feat(rcar3): enable the stack protection")
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

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feat(rcar): fold console_rcar_* functions into rcar_printf.c

The three console_rcar_{init,putc,flush}() no-op functions can
easily be C functions, they do not need assembler wrappers. Move
the funct

feat(rcar): fold console_rcar_* functions into rcar_printf.c

The three console_rcar_{init,putc,flush}() no-op functions can
easily be C functions, they do not need assembler wrappers. Move
the functions into rcar_printf.c which is part of the custom
R-Car Gen3 memory logging console. Remove rcar_printf.c from
BL2 builds, as it is not useful there. Rename rcar_set_log_data()
to console_rcar_putc() and update its signature, it is no longer
necessary to have such a wrapper around C function.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ia7a1c37b2151f6217cde70ffd2b367643d3184e4

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feat(rcar): rewrite SCIF driver from assembler to C

Rewrite the SCIF driver from difficult to read assembler to plain C.
Use scif-common.c which contains putc() and flush() helper functions
to avoid

feat(rcar): rewrite SCIF driver from assembler to C

Rewrite the SCIF driver from difficult to read assembler to plain C.
Use scif-common.c which contains putc() and flush() helper functions
to avoid duplication, so only fill in the initialization code. Drop
support for external clock, which is unused. Clean up macros and drop
ones which are not referenced.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ia933c505c33e133e45448c82776a17629f3df1eb

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fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change-Id: Ia4f71c5e79fa318a81a291080494f25e76fd987f
Signed-off-by: Roman Meier <romameie@outlook.com>

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feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algor

feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algorithm metadata at runtime. Add mboot_find_event_log_metadata() as a
common helper for resolving image metadata. Update the Event Log build
logic to use MAX_DIGEST_SIZE and MAX_HASH_COUNT, deprecate legacy
MBOOT_EL_HASH_ALG, and warn when it is used. Adjust MbedTLS
configuration to enable hash algorithms automatically when Measured Boot
is enabled.

Change-Id: I704e1a5005f6caad3d51d868bacc53699b6dd64f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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