fix(scmi): fix coverity issue INTEGER_OVERFLOW

Use round_up_overflow to avoid any integer overflow from
protocol count.

Thsi fixes below coverity issue -

CID 457880: (#1 of 1): Overflowed constant

fix(scmi): fix coverity issue INTEGER_OVERFLOW

Use round_up_overflow to avoid any integer overflow from
protocol count.

Thsi fixes below coverity issue -

CID 457880: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
4. overflow_const: Expression count - 1U, where count is known
to be equal to 0, underflows the type of count - 1U, which is
type unsigned int.

Change-Id: Ib55599fcb2a522e57271a6a07fb9bfd07e6953b9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-I

fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-Id: I376809fc110ff45dd0682b4bcf8dab43cf03d300
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is k

fix(scmi): fix coverity issue INTEGER_OVERFLOW

Fixes the following coverity issue -

CID 457917: (#1 of 1): Overflowed constant (INTEGER_OVERFLOW)
overflow_const: Expression lvl - 1U, where lvl is known to be equal
to 0, underflows the type of lvl - 1U, which is type unsigned int.

Change-Id: Id965c4b95159793944b3ef4658fd92e881d53c59
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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Merge changes from topic "st-usb-coverity" into integration

* changes:
fix(st-usb): init endpoint with fixed value if only one is used
fix(st-usb): correct phy_epnum type for error trace
fix(s

Merge changes from topic "st-usb-coverity" into integration

* changes:
fix(st-usb): init endpoint with fixed value if only one is used
fix(st-usb): correct phy_epnum type for error trace
fix(st-usb): stub dead code

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Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols un

Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols until all are resolved
fix(build): add include directory dependencies

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Merge "fix(rcar4): assure SCIF and HSCIF clock are always enabled" into integration

fix(build): don't rely on Event Log build tree

Follow proper CMake usage by installing libeventlog and referring to
the installed artifacts rather than the build directory. The previous
approach rel

fix(build): don't rely on Event Log build tree

Follow proper CMake usage by installing libeventlog and referring to
the installed artifacts rather than the build directory. The previous
approach relied on build-tree paths, which is considered an anti-
pattern and may break across CMake versions since the build layout is
not stable or part of the public interface.

This change installs libeventlog into a staging directory and updates
the TF-A build to use the installed include and library paths. This
improves portability, stability, and compliance with CMake idioms.

Change-Id: I740a558fd6f3163a6af3b122e9e1df558a045872
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(st-usb): init endpoint with fixed value if only one is used

Use a fixed value when initializing PHY endpoint, in case only one is
used.

This silences the Coverity issue CID 491154:
Integer hand

fix(st-usb): init endpoint with fixed value if only one is used

Use a fixed value when initializing PHY endpoint, in case only one is
used.

This silences the Coverity issue CID 491154:
Integer handling issues (CONSTANT_EXPRESSION_RESULT).

Change-Id: I082ba1a608439e0bdc15ddd8a514704e616d53b8
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st-usb): correct phy_epnum type for error trace

The variable phy_epnum is an uint8_t, we should use %u to display it,
and not %lu.

This corrects Coverity issue CID 491155:
API usage errors (PW.

fix(st-usb): correct phy_epnum type for error trace

The variable phy_epnum is an uint8_t, we should use %u to display it,
and not %lu.

This corrects Coverity issue CID 491155:
API usage errors (PW.PRINTF_ARG_MISMATCH).

Change-Id: I6be371277f641b08921f070d0a7dfeee9324a3fb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st-usb): stub dead code

In case USB_DWC3_NUM_OUT_EP or USB_DWC3_NUM_IN_EP are set to 1, some
loops become dead code. Put them under a pre-processor check.

This corrects an issue reported by Cov

fix(st-usb): stub dead code

In case USB_DWC3_NUM_OUT_EP or USB_DWC3_NUM_IN_EP are set to 1, some
loops become dead code. Put them under a pre-processor check.

This corrects an issue reported by Coverity: CID 491156 (DEADCODE).

Change-Id: I90e92af4468b05dc256ea744265baec582427611
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(build): link Event Log library directly

The `libraries` target is a `.PHONY` target to which various real
library targets, including the Event Log library, have been added over
the years. This t

fix(build): link Event Log library directly

The `libraries` target is a `.PHONY` target to which various real
library targets, including the Event Log library, have been added over
the years. This target is added as a dependency to any target created
with the `MAKE_BL` function. While this might look convenient on the
surface, it also dictates that a library must be linked even to images
it is totally irrelevant for.

The Event Log library is a good example of this; the library is not
typically used by all images, but by attaching itself to the `libraries`
target it becomes mandatory for all of them.

This change returns some of the control over when and where the Event
Log goes to platform maintainers via the introduction of two new
variables:

- `LIBEVLOG_LIBS`: the path to the Event Log static library.
- `LIBEVLOG_INCLUDE_DIRS`: include directories for the public API.

These can be appended to `BLx_LIBS` and `BLx_INCLUDE_DIRS` to include
the Event Log library in the relevant bootloaders.

Change-Id: I3e1a48cd45493334590b34b2ade0c6e29cbfd47a
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "upstream_deassert_ddr_reset" into integration

* changes:
feat(s32g274ardb): add DDR clock source support
feat(s32g274ardb): add mc_rgm_release_periph func

fix(st-clock): prevent panic when external oscillator is absent

To deactivate the external oscillator, the frequency must be set to 0
in the device tree.
The frequency check for 0 was implemented in

fix(st-clock): prevent panic when external oscillator is absent

To deactivate the external oscillator, the frequency must be set to 0
in the device tree.
The frequency check for 0 was implemented in clk_stm32_osc_gate_enable()
and clk_stm32_osc_gate_disable(), but missing in
clk_stm32_osc_gate_is_enabled().
Since clk_stm32_osc_gate_is_enabled() is called by clk_enable()
to verify if the clock is actually enabled, this fix prevents a panic
when the oscillator is not present.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I90dc671f39bd46d0db19d7532aee9ec7b449ba9d

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feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change

feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ia10c287bf4068742a7add9016c1a87e300eebff0

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fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manue

fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manuel,
chapter 3.3 Cortex-A35 clocking:

The clock for the Cortex-A35 subsystem can be selected among:
a clock from the device clock generator (aka ck_cpu1_ext2f). The maximum
frequency on this clock is 400 MHz with a divider by two, enabled thanks
to the CA35SS_SSC_CHGCLKREQ SSC register.

In OpenSTLinux clock tree you assume flexgen63 = 400MHz,
so we force divider by 2 for ck_cpu1_ext2f clock, the CA35 bypass clock
with ARM_DIVSEL = 0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9d11f9316ce3a2c7280a9bb7652d241b164ce5a1

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feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave periph

feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This doesn't support semaphore acquisition.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2

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feat(st-usb): add USB DWC3 driver

Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode

Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st

feat(st-usb): add USB DWC3 driver

Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode

Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>

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feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
i

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
initializing the DDR subsystem.

Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc

feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc_rgm_release_part`
to make use of `mc_rgm_release_periph` function.

Change-Id: Ia2e049ac461f823379ddce34b1406eea0a0a86e9
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(scmi): add support for discovering and changing parent clocks

Add base support for discovering and changing parent clocks

This is the part of SCMI platform design document version 3.2,
which i

feat(scmi): add support for discovering and changing parent clocks

Add base support for discovering and changing parent clocks

This is the part of SCMI platform design document version 3.2,
which introduces SCMI clock protocol version 3.0

Add mandatory support for CLOCK_CONFIG_GET which is needed
for SCMI clock protocol version 3.0

Also, add support for clock_enable_delay parameter which got
introduced as new parameter in return values for command
CLOCK_ATTRIBUTES in same SCMI Platform design document v3.2

Change-Id: Ie5cba83dad27bf1e3b51c11c0218259a44c1af59
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c

feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c57b0112302d3568e0e0bcf2116d3e259
Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I

refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I4c1f23b7ea2f17fdb71792319b4c403db542b757
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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fix(rcar4): assure SCIF and HSCIF clock are always enabled

Prior stages before TFA BL31 may shut down the SCIF or HSCIF clock.
Enable the SCIF or HSCIF clock again during console initialization,
to

fix(rcar4): assure SCIF and HSCIF clock are always enabled

Prior stages before TFA BL31 may shut down the SCIF or HSCIF clock.
Enable the SCIF or HSCIF clock again during console initialization,
to make sure those clock are running and prints can be produced on
serial console if necessary.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I9461e72888a939c0bbe5795087a76f1a71c7151d

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