drivers: marvell: thermal: use dedicated function for thermal SiPs

Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name

drivers: marvell: thermal: use dedicated function for thermal SiPs

Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.

Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: marvell: add thermal sensor driver and expose it via SIP service

Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), acce

drivers: marvell: add thermal sensor driver and expose it via SIP service

Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.

The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.

Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>

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Merge changes from topic "dcc_console" into integration

* changes:
plat:xilinx:versal: Add JTAG DCC support
plat:xilinx:zynqmp: Add JTAG DCC support
drivers: dcc: Support JTAG DCC console

Merge "driver: brcm: add mdio driver" into integration

mmc: remove useless extra semicolons

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If1d6b2040e482577292890e3554449096648c2ae

Revert "mmc:prevent accessing to the released space in case of wrong usage"

This reverts commit 13f3c5166f126b021e5f6e09e4a7c97f12495a35.
The STM32MP1 platform can no more boot qwith this change.
Th

Revert "mmc:prevent accessing to the released space in case of wrong usage"

This reverts commit 13f3c5166f126b021e5f6e09e4a7c97f12495a35.
The STM32MP1 platform can no more boot qwith this change.
The driver will not be aware when the static struct in framework is updated.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Icc544e243136ee3b0067f316b71dff7dfd6526d6

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Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask

Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

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drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit need

drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7

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drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register valu

drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
new_val = (old_val & ~mask) | (data & mask);
it does
new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65

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drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should

drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b

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drivers: dcc: Support JTAG DCC console

The legacy console is gone. Re-add DCC console support based
on the multi-console framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilin

drivers: dcc: Support JTAG DCC console

The legacy console is gone. Re-add DCC console support based
on the multi-console framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e

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Merge changes from topic "tzc400_stm32mp" into integration

* changes:
stm32mp1: add TZC400 interrupt management
stm32mp1: use TZC400 macro to describe filters
tzc400: add support for interrupts

driver: brcm: add i2c driver

Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2

driver: brcm: add i2c driver

Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13

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Merge "plat/allwinner: do not setup 'disabled' regulators" into integration

nxp: adding the driver.mk file

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic6c3a173f9f1f7b85244fc4484e247fdbb438b9c

nxp: cot using nxp internal and mbedtls

Chain of trust(CoT) is enabled on NXP SoC in two ways:
- Using MbedTLS, parsing X509 Certificates.
- Using NXP internal method parsing CSF header

Signed-off-

nxp: cot using nxp internal and mbedtls

Chain of trust(CoT) is enabled on NXP SoC in two ways:
- Using MbedTLS, parsing X509 Certificates.
- Using NXP internal method parsing CSF header

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I78fb28516dfcfa667bebf8a1951ffb24bcab8de4

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nxp:driver for crypto h/w accelerator caam

NXP has hardware crypto accelerator called CAAM.
- Work with Job ring
- Jobs are submitted to CAAM in the form of 64 word
descriptor.

Signed-off-by: Ruc

nxp:driver for crypto h/w accelerator caam

NXP has hardware crypto accelerator called CAAM.
- Work with Job ring
- Jobs are submitted to CAAM in the form of 64 word
descriptor.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I02bcfce68143b8630e1833a74c4b126972f4323d

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nxp:add driver support for sd and emmc

SD & eMMC driver support for NXP SoC.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I245f

nxp:add driver support for sd and emmc

SD & eMMC driver support for NXP SoC.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I245fecd2c791697238b5667c46bf5466379695ce

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nxp:add qspi driver

NXP QuadSPI driver support NXP SoC.
- Supporting QSPI flash

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I928cbec8ea31f4d8f9e320ac9c5105f7ab0ecb73

nxp: add flexspi driver support

Flexspi driver now introduces read/write/erase APIs for complete flash
size, FAST-READ are by default used and IP bus is used for erase, read
and write using flexspi

nxp: add flexspi driver support

Flexspi driver now introduces read/write/erase APIs for complete flash
size, FAST-READ are by default used and IP bus is used for erase, read
and write using flexspi APIs.

Framework layer is currently embedded in driver itself using flash_info
defines.

Test cases are also added to confirm flash functionality currently under
DEBUG flag.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0

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nxp: adding gic apis for nxp soc

GIC api used by NXP SoC is based on:
- arm provided drivers: /drivers/arm/gic

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If3d470256e5bd078614f191

nxp: adding gic apis for nxp soc

GIC api used by NXP SoC is based on:
- arm provided drivers: /drivers/arm/gic

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd

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nxp: gpio driver support

NXP General Purpose Input/Output driver support for
NXP platforms.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a3574f1d5d12e4a65ff60f640d4e77e2defd6d4

nxp: added csu driver

NXP Central Security Unit(CSU) for NXP SoC.
CSU is used for:
- Access permissions for peripheral that donot have their own
access control.
- Locking of individual CSU setting

nxp: added csu driver

NXP Central Security Unit(CSU) for NXP SoC.
CSU is used for:
- Access permissions for peripheral that donot have their own
access control.
- Locking of individual CSU settings until the next POR
- General purpose security related control bits

Refer NXP SoC manuals fro more details.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I07a4729c79c5e2597f8b2a782e87e09f7f30c2ca

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nxp: driver pmu for nxp soc

Driver for NXP IP for Power Management Unit.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I855657eddab357cb182419b188ed8861c46a1b19

nxp: ddr driver enablement for nxp layerscape soc

DDR driver for NXP layerscape SoC(s):
- lx2160aqds
- lx2162aqds
- lx2160ardb
- Other Board with SoC(s) like ls1046a, ls1043a etc;
-- These othe

nxp: ddr driver enablement for nxp layerscape soc

DDR driver for NXP layerscape SoC(s):
- lx2160aqds
- lx2162aqds
- lx2160ardb
- Other Board with SoC(s) like ls1046a, ls1043a etc;
-- These other boards are not verified yet.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf

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