1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <common/debug.h> 9 #include <drivers/marvell/mci.h> 10 #include <drivers/marvell/mochi/ap_setup.h> 11 #include <drivers/marvell/mochi/cp110_setup.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <marvell_plat_priv.h> 16 #include <marvell_pm.h> 17 #include <mc_trustzone/mc_trustzone.h> 18 #include <plat_marvell.h> 19 #if MSS_SUPPORT 20 #include <mss_ipc_drv.h> 21 #include <mss_mem.h> 22 #endif 23 24 /* In Armada-8k family AP806/AP807, CP0 connected to PIDI 25 * and CP1 connected to IHB via MCI #0 26 */ 27 #define MVEBU_MCI0 0 28 29 static _Bool pm_fw_running; 30 31 /* Set a weak stub for platforms that don't need to configure GPIO */ 32 #pragma weak marvell_gpio_config 33 int marvell_gpio_config(void) 34 { 35 return 0; 36 } 37 38 static void marvell_bl31_mpp_init(int cp) 39 { 40 uint32_t reg; 41 42 /* need to do for CP#0 only */ 43 if (cp) 44 return; 45 46 47 /* 48 * Enable CP0 I2C MPPs (MPP: 37-38) 49 * U-Boot rely on proper MPP settings for I2C EEPROM usage 50 * (only for CP0) 51 */ 52 reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4)); 53 mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000); 54 } 55 56 #if MSS_SUPPORT 57 void marvell_bl31_mss_init(void) 58 { 59 struct mss_pm_ctrl_block *mss_pm_crtl = 60 (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; 61 62 /* Check that the image was loaded successfully */ 63 if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { 64 NOTICE("MSS PM is not supported in this build\n"); 65 return; 66 } 67 68 /* If we got here it means that the PM firmware is running */ 69 pm_fw_running = 1; 70 71 INFO("MSS IPC init\n"); 72 73 if (mss_pm_crtl->ipc_state == IPC_INITIALIZED) 74 mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); 75 } 76 #endif 77 78 _Bool is_pm_fw_running(void) 79 { 80 return pm_fw_running; 81 } 82 83 /* For TrusTzone we treat the "target" field of addr_map_win 84 * struct as attribute 85 */ 86 static const struct addr_map_win tz_map[] = { 87 {PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT} 88 }; 89 90 /* Configure MC TrustZone regions */ 91 static void marvell_bl31_security_setup(void) 92 { 93 int tz_nr, win_id; 94 95 tz_nr = ARRAY_SIZE(tz_map); 96 97 for (win_id = 0; win_id < tz_nr; win_id++) 98 tz_enable_win(MVEBU_AP0, tz_map, win_id); 99 } 100 101 /* This function overruns the same function in marvell_bl31_setup.c */ 102 void bl31_plat_arch_setup(void) 103 { 104 int cp; 105 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; 106 107 /* initialize the timer for mdelay/udelay functionality */ 108 plat_delay_timer_init(); 109 110 /* configure apn806 */ 111 ap_init(); 112 113 /* In marvell_bl31_plat_arch_setup, el3 mmu is configured. 114 * el3 mmu configuration MUST be called after apn806_init, if not, 115 * this will cause an hang in init_io_win 116 * (after setting the IO windows GCR values). 117 */ 118 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || 119 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) 120 marvell_bl31_plat_arch_setup(); 121 122 for (cp = 0; cp < CP_COUNT; cp++) { 123 cp110_init(MVEBU_CP_REGS_BASE(cp), 124 STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP)); 125 126 marvell_bl31_mpp_init(cp); 127 } 128 129 for (cp = 1; cp < CP_COUNT; cp++) 130 mci_link_tune(cp - 1); 131 132 #if MSS_SUPPORT 133 /* initialize IPC between MSS and ATF */ 134 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || 135 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) 136 marvell_bl31_mss_init(); 137 #endif 138 /* Configure GPIO */ 139 marvell_gpio_config(); 140 141 marvell_bl31_security_setup(); 142 } 143