1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 #include <lib/mmio.h> 11 12 #if RCAR_LSI == RCAR_AUTO 13 #include "G2H/qos_init_g2h_v30.h" 14 #include "G2M/qos_init_g2m_v10.h" 15 #include "G2M/qos_init_g2m_v11.h" 16 #include "G2M/qos_init_g2m_v30.h" 17 #endif /* RCAR_LSI == RCAR_AUTO */ 18 #if (RCAR_LSI == RZ_G2M) 19 #include "G2M/qos_init_g2m_v10.h" 20 #include "G2M/qos_init_g2m_v11.h" 21 #include "G2M/qos_init_g2m_v30.h" 22 #endif /* RCAR_LSI == RZ_G2M */ 23 #if RCAR_LSI == RZ_G2H 24 #include "G2H/qos_init_g2h_v30.h" 25 #endif /* RCAR_LSI == RZ_G2H */ 26 #include "qos_common.h" 27 #include "qos_init.h" 28 #include "qos_reg.h" 29 #include "rcar_def.h" 30 31 #define DRAM_CH_CNT 0x04U 32 uint32_t qos_init_ddr_ch; 33 uint8_t qos_init_ddr_phyvalid; 34 35 #define PRR_PRODUCT_ERR(reg) \ 36 { \ 37 ERROR("LSI Product ID(PRR=0x%x) QoS " \ 38 "initialize not supported.\n", reg); \ 39 panic(); \ 40 } 41 42 #define PRR_CUT_ERR(reg) \ 43 { \ 44 ERROR("LSI Cut ID(PRR=0x%x) QoS " \ 45 "initialize not supported.\n", reg); \ 46 panic(); \ 47 } 48 49 void rzg_qos_init(void) 50 { 51 uint32_t reg; 52 uint32_t i; 53 54 qos_init_ddr_ch = 0U; 55 qos_init_ddr_phyvalid = get_boardcnf_phyvalid(); 56 for (i = 0U; i < DRAM_CH_CNT; i++) { 57 if ((qos_init_ddr_phyvalid & (1U << i))) { 58 qos_init_ddr_ch++; 59 } 60 } 61 62 reg = mmio_read_32(PRR); 63 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT 64 switch (reg & PRR_PRODUCT_MASK) { 65 case PRR_PRODUCT_M3: 66 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) 67 switch (reg & PRR_CUT_MASK) { 68 case PRR_PRODUCT_10: 69 qos_init_g2m_v10(); 70 break; 71 case PRR_PRODUCT_21: /* G2M Cut 13 */ 72 qos_init_g2m_v11(); 73 break; 74 case PRR_PRODUCT_30: /* G2M Cut 30 */ 75 default: 76 qos_init_g2m_v30(); 77 break; 78 } 79 #else /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */ 80 PRR_PRODUCT_ERR(reg); 81 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */ 82 break; 83 case PRR_PRODUCT_H3: 84 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) 85 switch (reg & PRR_CUT_MASK) { 86 case PRR_PRODUCT_30: 87 default: 88 qos_init_g2h_v30(); 89 break; 90 } 91 #else 92 PRR_PRODUCT_ERR(reg); 93 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */ 94 break; 95 default: 96 PRR_PRODUCT_ERR(reg); 97 break; 98 } 99 #else /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */ 100 #if (RCAR_LSI == RZ_G2M) 101 #if RCAR_LSI_CUT == RCAR_CUT_10 102 /* G2M Cut 10 */ 103 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10) 104 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 105 PRR_PRODUCT_ERR(reg); 106 } 107 qos_init_g2m_v10(); 108 #elif RCAR_LSI_CUT == RCAR_CUT_11 109 /* G2M Cut 11 */ 110 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20) 111 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 112 PRR_PRODUCT_ERR(reg); 113 } 114 qos_init_g2m_v11(); 115 #elif RCAR_LSI_CUT == RCAR_CUT_13 116 /* G2M Cut 13 */ 117 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21) 118 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 119 PRR_PRODUCT_ERR(reg); 120 } 121 qos_init_g2m_v11(); 122 #else 123 /* G2M Cut 30 or later */ 124 if ((PRR_PRODUCT_M3) 125 != (reg & (PRR_PRODUCT_MASK))) { 126 PRR_PRODUCT_ERR(reg); 127 } 128 qos_init_g2m_v30(); 129 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */ 130 #elif (RCAR_LSI == RZ_G2H) 131 /* G2H Cut 30 or later */ 132 if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) { 133 PRR_PRODUCT_ERR(reg); 134 } 135 qos_init_g2h_v30(); 136 #else /* (RCAR_LSI == RZ_G2M) */ 137 #error "Don't have QoS initialize routine(Unknown chip)." 138 #endif /* (RCAR_LSI == RZ_G2M) */ 139 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */ 140 } 141 142 uint32_t get_refperiod(void) 143 { 144 uint32_t refperiod = QOSWT_WTSET0_CYCLE; 145 146 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT 147 uint32_t reg; 148 149 reg = mmio_read_32(PRR); 150 switch (reg & PRR_PRODUCT_MASK) { 151 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) 152 case PRR_PRODUCT_M3: 153 switch (reg & PRR_CUT_MASK) { 154 case PRR_PRODUCT_10: 155 break; 156 case PRR_PRODUCT_20: /* G2M Cut 11 */ 157 case PRR_PRODUCT_21: /* G2M Cut 13 */ 158 case PRR_PRODUCT_30: /* G2M Cut 30 */ 159 default: 160 refperiod = REFPERIOD_CYCLE; 161 break; 162 } 163 break; 164 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */ 165 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) 166 case PRR_PRODUCT_H3: 167 switch (reg & PRR_CUT_MASK) { 168 case PRR_PRODUCT_30: 169 default: 170 refperiod = REFPERIOD_CYCLE; 171 break; 172 } 173 break; 174 #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */ 175 default: 176 break; 177 } 178 #elif RCAR_LSI == RZ_G2M 179 #if RCAR_LSI_CUT == RCAR_CUT_10 180 /* G2M Cut 10 */ 181 #else /* RCAR_LSI_CUT == RCAR_CUT_10 */ 182 /* G2M Cut 11|13|30 or later */ 183 refperiod = REFPERIOD_CYCLE; 184 #endif /* RCAR_LSI_CUT == RCAR_CUT_10 */ 185 #elif RCAR_LSI == RZ_G2H 186 /* G2H Cut 30 or later */ 187 refperiod = REFPERIOD_CYCLE; 188 #endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */ 189 return refperiod; 190 } 191 192 void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos, 193 unsigned int qos_size, bool dbsc_wren) 194 { 195 unsigned int i; 196 197 /* Register write enable */ 198 if (dbsc_wren) { 199 mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U); 200 } 201 202 for (i = 0; i < qos_size; i++) { 203 mmio_write_32(qos[i].reg, qos[i].val); 204 } 205 206 /* Register write protect */ 207 if (dbsc_wren) { 208 mmio_write_32(DBSC_DBSYSCNT0, 0x00000000U); 209 } 210 } 211