| 7417cda6 | 05-Apr-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(st-clock): correct stm32_clk_parse_fdt_by_name
The fdt_getprop() function sets the length to -1 if the property is not found. We should then not use it later in stm32_clk_parse_fdt_by_name() in
fix(st-clock): correct stm32_clk_parse_fdt_by_name
The fdt_getprop() function sets the length to -1 if the property is not found. We should then not use it later in stm32_clk_parse_fdt_by_name() in that case. Directly set *nb to 0U and return 0 if the property is not found.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I19c5c953f392cdc768e0b1f3f240fc99a73a049c
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| b8eab512 | 29-Mar-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-clock): check _clk_stm32_get_parent return
This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent() return shouldn't be negative. Return the error in this case.
Signed-off-
fix(st-clock): check _clk_stm32_get_parent return
This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent() return shouldn't be negative. Return the error in this case.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I91eff7e99fcdac9a258100b163fd9b040a9bd2c0
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| 6481a8f1 | 20-Jan-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(st-sdmmc2): allow compatible to be defined in platform code
Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not defined in platform code.
Change-Id: I611baaf1fc622d33e655ee
feat(st-sdmmc2): allow compatible to be defined in platform code
Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not defined in platform code.
Change-Id: I611baaf1fc622d33e655ee2c78d9c287baaa6a67 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 5278ec3f | 18-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(st-pmic): add pmic_voltages_init() function
This new function pmic_voltages_init() is used to set the minimum value for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved from dev
feat(st-pmic): add pmic_voltages_init() function
This new function pmic_voltages_init() is used to set the minimum value for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ibbe237cb5dccc1fddf92e07ffd3955048ff82075
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| 9be88e75 | 11-Mar-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
feat(st-clock): add clock driver for STM32MP13
Add new clock driver for STM32MP13. Split the include file to manage either STM32MP13 or STM32MP15.
Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e9
feat(st-clock): add clock driver for STM32MP13
Add new clock driver for STM32MP13. Split the include file to manage either STM32MP13 or STM32MP15.
Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 111a384c | 12-Feb-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): remove unsupported features on STM32MP13
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ. * STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1 and reset fr
feat(stm32mp1): remove unsupported features on STM32MP13
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ. * STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1 and reset from MCU traces * There is no MCU on STM32MP13. Put MCU security management under STM32MP15 flag. * The authentication feature is not supported yet on STM32MP13, put the code under SPM32MP15 flag. * On STM32MP13, the monotonic counter is managed in ROM code, keep the monotonic counter update just for STM32MP15. * SYSCFG: put registers not present on STM32MP13 under STM32MP15 flag, as the code that manages them. * PMIC: use ldo3 during DDR configuration only for STM32MP15 * Reset UART pins on USB boot is no more required.
Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 57e60183 | 09-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-pmic): add static const to pmic_ops
The static was found by sparse tool: drivers/st/pmic/stm32mp_pmic.c:456:18: warning: symbol 'pmic_ops' was not declared. Should it be static? The const wa
fix(st-pmic): add static const to pmic_ops
The static was found by sparse tool: drivers/st/pmic/stm32mp_pmic.c:456:18: warning: symbol 'pmic_ops' was not declared. Should it be static? The const was also missing.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ibb5cfaf67ac980bf0af27712a95dbef05b617c25
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| c507b060 | 06-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(st-clock): initialize pllcfg table" into integration |
| 1f60d1bd | 28-Feb-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st-uart): manage oversampling by 8
UART oversampling by 8 allows higher baud rates for UART. This is required when (UART freq / baudrate) <= 16. In this case the OVER8 bit needs to be enabled i
feat(st-uart): manage oversampling by 8
UART oversampling by 8 allows higher baud rates for UART. This is required when (UART freq / baudrate) <= 16. In this case the OVER8 bit needs to be enabled in CR1 register. And the BRR register management is different: USARTDIV = (2 * UART freq / baudrate) (with div round nearest) BRR[15:4] = USARTDIV[15:4] BRR[3] = 0 BRR[2:0] = USARTDIV[3:0] >> 1
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ia3fbeeb73a36a4dc485c7ba428c531e65b6f6c09
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| af7775ab | 28-Feb-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(st-uart): correctly fill BRR register
To get the nearest divisor for BRR register, we use: Divisor = (Uart clock + (baudrate / 2)) / baudrate But lsl was wrongly used instead of lsr to have the
fix(st-uart): correctly fill BRR register
To get the nearest divisor for BRR register, we use: Divisor = (Uart clock + (baudrate / 2)) / baudrate But lsl was wrongly used instead of lsr to have the division by 2.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Iedcc3ccdb4cf8268012e82a66df2a9ec48fc1d79
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| 175758b2 | 04-Mar-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-clock): initialize pllcfg table
The issue was found by Coverity: CID 376582: (UNINIT) Using uninitialized value "*pllcfg[_PLL4]" when calling "stm32mp1_check_pll_conf". CID 376582:
fix(st-clock): initialize pllcfg table
The issue was found by Coverity: CID 376582: (UNINIT) Using uninitialized value "*pllcfg[_PLL4]" when calling "stm32mp1_check_pll_conf". CID 376582: (UNINIT) Using uninitialized value "*pllcfg[_PLL3]" when calling "stm32mp1_check_pll_conf".
Check PLL configs are valid before using pllcfg.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I49de849eaf451d0c165a8eb8555112a0a4140bbc
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| 9fa9a0c5 | 28-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-clock): print enums as unsigned
With gcc-11, the -Wformat-signedness warning complains about enum values that should be printed as unsigned values. Change %d to %u for several lines in the cl
fix(st-clock): print enums as unsigned
With gcc-11, the -Wformat-signedness warning complains about enum values that should be printed as unsigned values. Change %d to %u for several lines in the clock driver.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ia2d24e6feef5e852e0a6bfaa1286fe605f9a16b7
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| 47065ffe | 06-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-pmic): correct verbose message
Replace %d with %u in log, to avoid warning when -Wformat-signedness is enabled.
Change-Id: Ied5823520181f225ae09bd164e2e52e9a7692c60 Signed-off-by: Yann Gauti
fix(st-pmic): correct verbose message
Replace %d with %u in log, to avoid warning when -Wformat-signedness is enabled.
Change-Id: Ied5823520181f225ae09bd164e2e52e9a7692c60 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| bc1c98a8 | 14-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-sdmmc2): correct cmd_idx type in messages
As cmd_idx is unsigned, we have to use %u and not %d. This avoids warning when -Wformat-signedness is enabled.
Change-Id: I6954a8c939f3fb47dbb2c6db5
fix(st-sdmmc2): correct cmd_idx type in messages
As cmd_idx is unsigned, we have to use %u and not %d. This avoids warning when -Wformat-signedness is enabled.
Change-Id: I6954a8c939f3fb47dbb2c6db56a1909565af078b Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| afcdc9d8 | 14-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-fmc): fix type in message
As page is unsigned, we should use %u and not %d. Find with -Wformat-signedness.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I7205971ee5e83163e4fe4
fix(st-fmc): fix type in message
As page is unsigned, we should use %u and not %d. Find with -Wformat-signedness.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I7205971ee5e83163e4fe47d33bb9e90832b59ae0
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| 812daf91 | 15-Dec-2020 |
Lionel Debieve <lionel.debieve@st.com> |
feat(st): update the security based on new compatible
From the new binding, the RCC become secured based on the new compatible. This must be done only from the secure OS initialisation.
Signed-off-
feat(st): update the security based on new compatible
From the new binding, the RCC become secured based on the new compatible. This must be done only from the secure OS initialisation.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I7f0a62f22bfcca638ddaefc9563df00f89f01653
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| fc0aa10a | 11-Aug-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(st-gpio): do not apply secure config in BL2
At boot, the devices under ETZPC control are secured, so should be their GPIOs. As securable GPIOs are secured by default, keep the reset values in B
feat(st-gpio): do not apply secure config in BL2
At boot, the devices under ETZPC control are secured, so should be their GPIOs. As securable GPIOs are secured by default, keep the reset values in BL2.
Change-Id: I9e560d936f8e8fda0f96f6299bb0c3b35ba9b71f Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 53584e1d | 21-Sep-2021 |
Fabien Dessenne <fabien.dessenne@foss.st.com> |
feat(st-gpio): allow to set a gpio in output mode
Allow to set a gpio in output mode from the device tree.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: Ic483324bc5fe916a6
feat(st-gpio): allow to set a gpio in output mode
Allow to set a gpio in output mode from the device tree.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: Ic483324bc5fe916a60df05f74706bd1da4d08aa5
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| 417196fa | 21-Sep-2021 |
Fabien Dessenne <fabien.dessenne@foss.st.com> |
refactor(st-gpio): code improvements
No functional, change, but some improvements: - Declare set_gpio() as static (only called locally) - Handle the type ('open-drain') property independently from t
refactor(st-gpio): code improvements
No functional, change, but some improvements: - Declare set_gpio() as static (only called locally) - Handle the type ('open-drain') property independently from the mode one. - Replace mmio_clrbits_32() + mmio_setbits_32() with mmio_clrsetbits_32(). - Add a missing log - Add missing U() in macro definitions
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa
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| 072d7532 | 20-May-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements.
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements. Probe the driver earlier, especially to check debug features.
Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 9b4ca70d | 28-Jan-2022 |
Pascal Paillet <p.paillet@st.com> |
feat(st-regulator): add support for regulator-always-on
Add support for regulator-always-on at BL2 level as it was supported before using the regulator framework.
Signed-off-by: Pascal Paillet <p.p
feat(st-regulator): add support for regulator-always-on
Add support for regulator-always-on at BL2 level as it was supported before using the regulator framework.
Signed-off-by: Pascal Paillet <p.paillet@st.com> Change-Id: Idb2f4ddc2fdd4e0d31fb33da87c84618aa2e5135
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| 591d80c8 | 04-Dec-2019 |
Lionel Debieve <lionel.debieve@st.com> |
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by: Lionel Debieve <
refactor(st-clock): update STGEN management
Rework STGEN config function, and move it to stm32mp_clkfunc.c file.
Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 7418cf39 | 17-Jan-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(st-clock): assign clocks to the correct BL
Some clocks are only required in BL2, like boot devices clocks: FMC, QSPI. Some clocks are only used in BL32: Timers, devices that need special care f
feat(st-clock): assign clocks to the correct BL
Some clocks are only required in BL2, like boot devices clocks: FMC, QSPI. Some clocks are only used in BL32: Timers, devices that need special care for independent reset.
Change-Id: Id4ba99afeea5095f419a86f7dc6423192c628d82 Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 3d69149a | 27-Oct-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(st-clock): do not refcount on non-secure clocks in bl32
This change removes reference counting support in clock gating implementation for clocks that rely on non-secure only RCC resources. As R
feat(st-clock): do not refcount on non-secure clocks in bl32
This change removes reference counting support in clock gating implementation for clocks that rely on non-secure only RCC resources. As RCC registers are accessed straight by non-secure world for these clocks, secure world cannot safely store the clock state and even disabling such clock from secure world can jeopardize the non-secure world clock management framework and drivers.
As a consequence, for such clocks, stm32_clock_enable() forces the clock ON without any increment of a refcount and stm32_clock_disable() does not disable the clock.
Change-Id: I0cc159b36a25dbc8676f05edf2668ae63c640537 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| aaa09b71 | 27-Oct-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(st-clock): define secure and non-secure gate clocks
Array stm32mp1_clk_gate[] defines the clock resources. This change add a secure attribute to the clock: secure upon RCC[TZEN] (SEC), secure u
feat(st-clock): define secure and non-secure gate clocks
Array stm32mp1_clk_gate[] defines the clock resources. This change add a secure attribute to the clock: secure upon RCC[TZEN] (SEC), secure upon RCC[TZEN] and RCC[MCKPROT] (MKP) or always accessible from non-secure (N_S).
At init, lookup clock tree to check if any of the secure clocks is derived from PLL3 in which case PLL3 shall be secure.
Note that this change does not grow byte size of stm32mp1_clk_gate[].
Change-Id: I933d8a30007f3c72f755aa1ef6d7e6bcfabbfa9e Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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