fix(st-usb): init endpoint with fixed value if only one is used

Use a fixed value when initializing PHY endpoint, in case only one is
used.

This silences the Coverity issue CID 491154:
Integer hand

fix(st-usb): init endpoint with fixed value if only one is used

Use a fixed value when initializing PHY endpoint, in case only one is
used.

This silences the Coverity issue CID 491154:
Integer handling issues (CONSTANT_EXPRESSION_RESULT).

Change-Id: I082ba1a608439e0bdc15ddd8a514704e616d53b8
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st-usb): correct phy_epnum type for error trace

The variable phy_epnum is an uint8_t, we should use %u to display it,
and not %lu.

This corrects Coverity issue CID 491155:
API usage errors (PW.

fix(st-usb): correct phy_epnum type for error trace

The variable phy_epnum is an uint8_t, we should use %u to display it,
and not %lu.

This corrects Coverity issue CID 491155:
API usage errors (PW.PRINTF_ARG_MISMATCH).

Change-Id: I6be371277f641b08921f070d0a7dfeee9324a3fb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st-usb): stub dead code

In case USB_DWC3_NUM_OUT_EP or USB_DWC3_NUM_IN_EP are set to 1, some
loops become dead code. Put them under a pre-processor check.

This corrects an issue reported by Cov

fix(st-usb): stub dead code

In case USB_DWC3_NUM_OUT_EP or USB_DWC3_NUM_IN_EP are set to 1, some
loops become dead code. Put them under a pre-processor check.

This corrects an issue reported by Coverity: CID 491156 (DEADCODE).

Change-Id: I90e92af4468b05dc256ea744265baec582427611
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st-clock): prevent panic when external oscillator is absent

To deactivate the external oscillator, the frequency must be set to 0
in the device tree.
The frequency check for 0 was implemented in

fix(st-clock): prevent panic when external oscillator is absent

To deactivate the external oscillator, the frequency must be set to 0
in the device tree.
The frequency check for 0 was implemented in clk_stm32_osc_gate_enable()
and clk_stm32_osc_gate_disable(), but missing in
clk_stm32_osc_gate_is_enabled().
Since clk_stm32_osc_gate_is_enabled() is called by clk_enable()
to verify if the clock is actually enabled, this fix prevents a panic
when the oscillator is not present.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I90dc671f39bd46d0db19d7532aee9ec7b449ba9d

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feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change

feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ia10c287bf4068742a7add9016c1a87e300eebff0

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fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manue

fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manuel,
chapter 3.3 Cortex-A35 clocking:

The clock for the Cortex-A35 subsystem can be selected among:
a clock from the device clock generator (aka ck_cpu1_ext2f). The maximum
frequency on this clock is 400 MHz with a divider by two, enabled thanks
to the CA35SS_SSC_CHGCLKREQ SSC register.

In OpenSTLinux clock tree you assume flexgen63 = 400MHz,
so we force divider by 2 for ck_cpu1_ext2f clock, the CA35 bypass clock
with ARM_DIVSEL = 0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9d11f9316ce3a2c7280a9bb7652d241b164ce5a1

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feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave periph

feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This doesn't support semaphore acquisition.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2

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feat(st-usb): add USB DWC3 driver

Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode

Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st

feat(st-usb): add USB DWC3 driver

Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode

Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>

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fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I

fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I94b6238e3f8a94bc4a1fabaf8d45d3b66d42e834
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
compl

fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
complete is enough.

Change-Id: I5e254df89f2652e300ea5bedf9269d420895bdbf
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the retur

fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the return value that should be void in flush related functions
description.

Change-Id: Idbeecc3ca36b6ce506c9489b4f611bbe345121a3
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character w

fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character written in TDR was
outputed.
This behavior is no more needed. Once a character is in the FIFO the
UART will empty it when it is clocked.

Change-Id: I914c7f75a451bedbcc9287d8ed9178db47b4eab4
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as it is mandatory to keep the DDR
clock active.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6ac2aff07484bfc22210ee9d3e46a97d1735f34b

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region definition through DT.

Change-Id: I1bca9c0a89af88a72651e1a71e3f8950807eec40
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve

fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve the IP behavior.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I7e05e52466be68fdbf5439931a9f01dcfa57a24d

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feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instanc

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instance for the TF-A
purpose as it needs only one to work. The others are activated because
needed by specific IPs.

Seed errors are now also checked after null data read. The Reference
Manual recommends to always verify that RNG_DR is different from zero.
Because when it is the case a seed error can occur between RNG_SR
polling and RND_DR output reading (rare event).

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Ie4d7f01f4ffe5a9e2d0e5e7317b008edd3b80a17

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fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

S

fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

Signed-off-by: Thomas BOURGOIN <thomas.bourgoin@foss.st.com>
Change-Id: Ia37b5b0f706701ca2827d47c9360dfcf83a48fc0

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Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1

feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.

This will avoid to forget to modify all these files when a new SoC is
introduced.

Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(st-iwdg): remove num_irq

Remove the unused field num_irq in stm32_iwdg_instance struct.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11

fix(st-iwdg): remove num_irq

Remove the unused field num_irq in stm32_iwdg_instance struct.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11d812430fa4

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fix(st-drivers): remove useless field in fixed regul

Cleanup useless structure fields in order to
reduce code size.

Change-Id: Ifb1df2d347c3d892d6633b339fa0bae648c87537
Signed-off-by: Pascal Paille

fix(st-drivers): remove useless field in fixed regul

Cleanup useless structure fields in order to
reduce code size.

Change-Id: Ifb1df2d347c3d892d6633b339fa0bae648c87537
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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fix(st-bsec): remove useless defines in BSEC3

Remove some useles defines and structure in BSEC3 driver.

Change-Id: Ieef147948e9beba776a4d10746ffc730e6faff25
Signed-off-by: Yann Gautier <yann.gautie

fix(st-bsec): remove useless defines in BSEC3

Remove some useles defines and structure in BSEC3 driver.

Change-Id: Ieef147948e9beba776a4d10746ffc730e6faff25
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d224

fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d2242bdf368d98d419d798

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