1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/stm32mp_clkfunc.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_rcc.h> 22 #include <dt-bindings/clock/stm32mp1-clksrc.h> 23 #include <lib/mmio.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils_def.h> 26 #include <libfdt.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_def.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _HSE_RTC, 60 _CSI_KER, 61 _PLL1_P, 62 _PLL1_Q, 63 _PLL1_R, 64 _PLL2_P, 65 _PLL2_Q, 66 _PLL2_R, 67 _PLL3_P, 68 _PLL3_Q, 69 _PLL3_R, 70 _PLL4_P, 71 _PLL4_Q, 72 _PLL4_R, 73 _ACLK, 74 _PCLK1, 75 _PCLK2, 76 _PCLK3, 77 _PCLK4, 78 _PCLK5, 79 _HCLK6, 80 _HCLK2, 81 _CK_PER, 82 _CK_MPU, 83 _CK_MCU, 84 _USB_PHY_48, 85 _PARENT_NB, 86 _UNKNOWN_ID = 0xff, 87 }; 88 89 /* Lists only the parent clock we are interested in */ 90 enum stm32mp1_parent_sel { 91 _I2C12_SEL, 92 _I2C35_SEL, 93 _STGEN_SEL, 94 _I2C46_SEL, 95 _SPI6_SEL, 96 _UART1_SEL, 97 _RNG1_SEL, 98 _UART6_SEL, 99 _UART24_SEL, 100 _UART35_SEL, 101 _UART78_SEL, 102 _SDMMC12_SEL, 103 _SDMMC3_SEL, 104 _QSPI_SEL, 105 _FMC_SEL, 106 _AXIS_SEL, 107 _MCUS_SEL, 108 _USBPHY_SEL, 109 _USBO_SEL, 110 _MPU_SEL, 111 _CKPER_SEL, 112 _RTC_SEL, 113 _PARENT_SEL_NB, 114 _UNKNOWN_SEL = 0xff, 115 }; 116 117 /* State the parent clock ID straight related to a clock */ 118 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 119 [_HSE] = CK_HSE, 120 [_HSI] = CK_HSI, 121 [_CSI] = CK_CSI, 122 [_LSE] = CK_LSE, 123 [_LSI] = CK_LSI, 124 [_I2S_CKIN] = _UNKNOWN_ID, 125 [_USB_PHY_48] = _UNKNOWN_ID, 126 [_HSI_KER] = CK_HSI, 127 [_HSE_KER] = CK_HSE, 128 [_HSE_KER_DIV2] = CK_HSE_DIV2, 129 [_HSE_RTC] = _UNKNOWN_ID, 130 [_CSI_KER] = CK_CSI, 131 [_PLL1_P] = PLL1_P, 132 [_PLL1_Q] = PLL1_Q, 133 [_PLL1_R] = PLL1_R, 134 [_PLL2_P] = PLL2_P, 135 [_PLL2_Q] = PLL2_Q, 136 [_PLL2_R] = PLL2_R, 137 [_PLL3_P] = PLL3_P, 138 [_PLL3_Q] = PLL3_Q, 139 [_PLL3_R] = PLL3_R, 140 [_PLL4_P] = PLL4_P, 141 [_PLL4_Q] = PLL4_Q, 142 [_PLL4_R] = PLL4_R, 143 [_ACLK] = CK_AXI, 144 [_PCLK1] = CK_AXI, 145 [_PCLK2] = CK_AXI, 146 [_PCLK3] = CK_AXI, 147 [_PCLK4] = CK_AXI, 148 [_PCLK5] = CK_AXI, 149 [_CK_PER] = CK_PER, 150 [_CK_MPU] = CK_MPU, 151 [_CK_MCU] = CK_MCU, 152 }; 153 154 static unsigned int clock_id2parent_id(unsigned long id) 155 { 156 unsigned int n; 157 158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 159 if (parent_id_clock_id[n] == id) { 160 return n; 161 } 162 } 163 164 return _UNKNOWN_ID; 165 } 166 167 enum stm32mp1_pll_id { 168 _PLL1, 169 _PLL2, 170 _PLL3, 171 _PLL4, 172 _PLL_NB 173 }; 174 175 enum stm32mp1_div_id { 176 _DIV_P, 177 _DIV_Q, 178 _DIV_R, 179 _DIV_NB, 180 }; 181 182 enum stm32mp1_clksrc_id { 183 CLKSRC_MPU, 184 CLKSRC_AXI, 185 CLKSRC_MCU, 186 CLKSRC_PLL12, 187 CLKSRC_PLL3, 188 CLKSRC_PLL4, 189 CLKSRC_RTC, 190 CLKSRC_MCO1, 191 CLKSRC_MCO2, 192 CLKSRC_NB 193 }; 194 195 enum stm32mp1_clkdiv_id { 196 CLKDIV_MPU, 197 CLKDIV_AXI, 198 CLKDIV_MCU, 199 CLKDIV_APB1, 200 CLKDIV_APB2, 201 CLKDIV_APB3, 202 CLKDIV_APB4, 203 CLKDIV_APB5, 204 CLKDIV_RTC, 205 CLKDIV_MCO1, 206 CLKDIV_MCO2, 207 CLKDIV_NB 208 }; 209 210 enum stm32mp1_pllcfg { 211 PLLCFG_M, 212 PLLCFG_N, 213 PLLCFG_P, 214 PLLCFG_Q, 215 PLLCFG_R, 216 PLLCFG_O, 217 PLLCFG_NB 218 }; 219 220 enum stm32mp1_pllcsg { 221 PLLCSG_MOD_PER, 222 PLLCSG_INC_STEP, 223 PLLCSG_SSCG_MODE, 224 PLLCSG_NB 225 }; 226 227 enum stm32mp1_plltype { 228 PLL_800, 229 PLL_1600, 230 PLL_TYPE_NB 231 }; 232 233 struct stm32mp1_pll { 234 uint8_t refclk_min; 235 uint8_t refclk_max; 236 uint8_t divn_max; 237 }; 238 239 struct stm32mp1_clk_gate { 240 uint16_t offset; 241 uint8_t bit; 242 uint8_t index; 243 uint8_t set_clr; 244 uint8_t secure; 245 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 246 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 247 }; 248 249 struct stm32mp1_clk_sel { 250 uint16_t offset; 251 uint8_t src; 252 uint8_t msk; 253 uint8_t nb_parent; 254 const uint8_t *parent; 255 }; 256 257 #define REFCLK_SIZE 4 258 struct stm32mp1_clk_pll { 259 enum stm32mp1_plltype plltype; 260 uint16_t rckxselr; 261 uint16_t pllxcfgr1; 262 uint16_t pllxcfgr2; 263 uint16_t pllxfracr; 264 uint16_t pllxcr; 265 uint16_t pllxcsgr; 266 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 267 }; 268 269 /* Clocks with selectable source and non set/clr register access */ 270 #define _CLK_SELEC(sec, off, b, idx, s) \ 271 { \ 272 .offset = (off), \ 273 .bit = (b), \ 274 .index = (idx), \ 275 .set_clr = 0, \ 276 .secure = (sec), \ 277 .sel = (s), \ 278 .fixed = _UNKNOWN_ID, \ 279 } 280 281 /* Clocks with fixed source and non set/clr register access */ 282 #define _CLK_FIXED(sec, off, b, idx, f) \ 283 { \ 284 .offset = (off), \ 285 .bit = (b), \ 286 .index = (idx), \ 287 .set_clr = 0, \ 288 .secure = (sec), \ 289 .sel = _UNKNOWN_SEL, \ 290 .fixed = (f), \ 291 } 292 293 /* Clocks with selectable source and set/clr register access */ 294 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 295 { \ 296 .offset = (off), \ 297 .bit = (b), \ 298 .index = (idx), \ 299 .set_clr = 1, \ 300 .secure = (sec), \ 301 .sel = (s), \ 302 .fixed = _UNKNOWN_ID, \ 303 } 304 305 /* Clocks with fixed source and set/clr register access */ 306 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 307 { \ 308 .offset = (off), \ 309 .bit = (b), \ 310 .index = (idx), \ 311 .set_clr = 1, \ 312 .secure = (sec), \ 313 .sel = _UNKNOWN_SEL, \ 314 .fixed = (f), \ 315 } 316 317 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 318 [_ ## _label ## _SEL] = { \ 319 .offset = _rcc_selr, \ 320 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 321 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 322 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 323 .parent = (_parents), \ 324 .nb_parent = ARRAY_SIZE(_parents) \ 325 } 326 327 #define _CLK_PLL(idx, type, off1, off2, off3, \ 328 off4, off5, off6, \ 329 p1, p2, p3, p4) \ 330 [(idx)] = { \ 331 .plltype = (type), \ 332 .rckxselr = (off1), \ 333 .pllxcfgr1 = (off2), \ 334 .pllxcfgr2 = (off3), \ 335 .pllxfracr = (off4), \ 336 .pllxcr = (off5), \ 337 .pllxcsgr = (off6), \ 338 .refclk[0] = (p1), \ 339 .refclk[1] = (p2), \ 340 .refclk[2] = (p3), \ 341 .refclk[3] = (p4), \ 342 } 343 344 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 345 346 #define SEC 1 347 #define N_S 0 348 349 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 359 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 360 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 361 362 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 363 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 373 374 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 375 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 376 377 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 378 379 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 380 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 381 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 382 383 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 384 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 385 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 387 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 388 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 389 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 393 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 394 395 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 396 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 397 398 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 399 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 400 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 401 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 402 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 409 410 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 411 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 412 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 413 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 414 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 415 416 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 417 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 418 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 419 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 420 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 421 422 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 423 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 424 }; 425 426 static const uint8_t i2c12_parents[] = { 427 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 428 }; 429 430 static const uint8_t i2c35_parents[] = { 431 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 432 }; 433 434 static const uint8_t stgen_parents[] = { 435 _HSI_KER, _HSE_KER 436 }; 437 438 static const uint8_t i2c46_parents[] = { 439 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 440 }; 441 442 static const uint8_t spi6_parents[] = { 443 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 444 }; 445 446 static const uint8_t usart1_parents[] = { 447 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 448 }; 449 450 static const uint8_t rng1_parents[] = { 451 _CSI, _PLL4_R, _LSE, _LSI 452 }; 453 454 static const uint8_t uart6_parents[] = { 455 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 456 }; 457 458 static const uint8_t uart234578_parents[] = { 459 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 460 }; 461 462 static const uint8_t sdmmc12_parents[] = { 463 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 464 }; 465 466 static const uint8_t sdmmc3_parents[] = { 467 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 468 }; 469 470 static const uint8_t qspi_parents[] = { 471 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 472 }; 473 474 static const uint8_t fmc_parents[] = { 475 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 476 }; 477 478 static const uint8_t axiss_parents[] = { 479 _HSI, _HSE, _PLL2_P 480 }; 481 482 static const uint8_t mcuss_parents[] = { 483 _HSI, _HSE, _CSI, _PLL3_P 484 }; 485 486 static const uint8_t usbphy_parents[] = { 487 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 488 }; 489 490 static const uint8_t usbo_parents[] = { 491 _PLL4_R, _USB_PHY_48 492 }; 493 494 static const uint8_t mpu_parents[] = { 495 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 496 }; 497 498 static const uint8_t per_parents[] = { 499 _HSI, _HSE, _CSI, 500 }; 501 502 static const uint8_t rtc_parents[] = { 503 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 504 }; 505 506 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 507 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 508 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 509 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 510 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 511 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 512 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 513 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 514 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 515 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 516 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 517 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 518 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 519 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 520 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 521 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 522 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 523 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 524 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 525 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 526 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 527 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 528 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 529 }; 530 531 /* Define characteristic of PLL according type */ 532 #define DIVN_MIN 24 533 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 534 [PLL_800] = { 535 .refclk_min = 4, 536 .refclk_max = 16, 537 .divn_max = 99, 538 }, 539 [PLL_1600] = { 540 .refclk_min = 8, 541 .refclk_max = 16, 542 .divn_max = 199, 543 }, 544 }; 545 546 /* PLLNCFGR2 register divider by output */ 547 static const uint8_t pllncfgr2[_DIV_NB] = { 548 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 549 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 550 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 551 }; 552 553 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 554 _CLK_PLL(_PLL1, PLL_1600, 555 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 556 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 557 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 558 _CLK_PLL(_PLL2, PLL_1600, 559 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 560 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 561 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 562 _CLK_PLL(_PLL3, PLL_800, 563 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 564 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 565 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 566 _CLK_PLL(_PLL4, PLL_800, 567 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 568 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 569 _HSI, _HSE, _CSI, _I2S_CKIN), 570 }; 571 572 /* Prescaler table lookups for clock computation */ 573 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 574 static const uint8_t stm32mp1_mcu_div[16] = { 575 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 576 }; 577 578 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 579 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 580 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 581 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 582 0, 1, 2, 3, 4, 4, 4, 4 583 }; 584 585 /* div = /1 /2 /3 /4 */ 586 static const uint8_t stm32mp1_axi_div[8] = { 587 1, 2, 3, 4, 4, 4, 4, 4 588 }; 589 590 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 591 [_HSI] = "HSI", 592 [_HSE] = "HSE", 593 [_CSI] = "CSI", 594 [_LSI] = "LSI", 595 [_LSE] = "LSE", 596 [_I2S_CKIN] = "I2S_CKIN", 597 [_HSI_KER] = "HSI_KER", 598 [_HSE_KER] = "HSE_KER", 599 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 600 [_HSE_RTC] = "HSE_RTC", 601 [_CSI_KER] = "CSI_KER", 602 [_PLL1_P] = "PLL1_P", 603 [_PLL1_Q] = "PLL1_Q", 604 [_PLL1_R] = "PLL1_R", 605 [_PLL2_P] = "PLL2_P", 606 [_PLL2_Q] = "PLL2_Q", 607 [_PLL2_R] = "PLL2_R", 608 [_PLL3_P] = "PLL3_P", 609 [_PLL3_Q] = "PLL3_Q", 610 [_PLL3_R] = "PLL3_R", 611 [_PLL4_P] = "PLL4_P", 612 [_PLL4_Q] = "PLL4_Q", 613 [_PLL4_R] = "PLL4_R", 614 [_ACLK] = "ACLK", 615 [_PCLK1] = "PCLK1", 616 [_PCLK2] = "PCLK2", 617 [_PCLK3] = "PCLK3", 618 [_PCLK4] = "PCLK4", 619 [_PCLK5] = "PCLK5", 620 [_HCLK6] = "KCLK6", 621 [_HCLK2] = "HCLK2", 622 [_CK_PER] = "CK_PER", 623 [_CK_MPU] = "CK_MPU", 624 [_CK_MCU] = "CK_MCU", 625 [_USB_PHY_48] = "USB_PHY_48", 626 }; 627 628 /* RCC clock device driver private */ 629 static unsigned long stm32mp1_osc[NB_OSC]; 630 static struct spinlock reg_lock; 631 static unsigned int gate_refcounts[NB_GATES]; 632 static struct spinlock refcount_lock; 633 634 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 635 { 636 return &stm32mp1_clk_gate[idx]; 637 } 638 639 #if defined(IMAGE_BL32) 640 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 641 { 642 return gate->secure == N_S; 643 } 644 #endif 645 646 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 647 { 648 return &stm32mp1_clk_sel[idx]; 649 } 650 651 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 652 { 653 return &stm32mp1_clk_pll[idx]; 654 } 655 656 static void stm32mp1_clk_lock(struct spinlock *lock) 657 { 658 if (stm32mp_lock_available()) { 659 /* Assume interrupts are masked */ 660 spin_lock(lock); 661 } 662 } 663 664 static void stm32mp1_clk_unlock(struct spinlock *lock) 665 { 666 if (stm32mp_lock_available()) { 667 spin_unlock(lock); 668 } 669 } 670 671 bool stm32mp1_rcc_is_secure(void) 672 { 673 uintptr_t rcc_base = stm32mp_rcc_base(); 674 uint32_t mask = RCC_TZCR_TZEN; 675 676 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 677 } 678 679 bool stm32mp1_rcc_is_mckprot(void) 680 { 681 uintptr_t rcc_base = stm32mp_rcc_base(); 682 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 683 684 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 685 } 686 687 void stm32mp1_clk_rcc_regs_lock(void) 688 { 689 stm32mp1_clk_lock(®_lock); 690 } 691 692 void stm32mp1_clk_rcc_regs_unlock(void) 693 { 694 stm32mp1_clk_unlock(®_lock); 695 } 696 697 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 698 { 699 if (idx >= NB_OSC) { 700 return 0; 701 } 702 703 return stm32mp1_osc[idx]; 704 } 705 706 static int stm32mp1_clk_get_gated_id(unsigned long id) 707 { 708 unsigned int i; 709 710 for (i = 0U; i < NB_GATES; i++) { 711 if (gate_ref(i)->index == id) { 712 return i; 713 } 714 } 715 716 ERROR("%s: clk id %lu not found\n", __func__, id); 717 718 return -EINVAL; 719 } 720 721 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 722 { 723 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 724 } 725 726 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 727 { 728 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 729 } 730 731 static int stm32mp1_clk_get_parent(unsigned long id) 732 { 733 const struct stm32mp1_clk_sel *sel; 734 uint32_t p_sel; 735 int i; 736 enum stm32mp1_parent_id p; 737 enum stm32mp1_parent_sel s; 738 uintptr_t rcc_base = stm32mp_rcc_base(); 739 740 /* Few non gateable clock have a static parent ID, find them */ 741 i = (int)clock_id2parent_id(id); 742 if (i != _UNKNOWN_ID) { 743 return i; 744 } 745 746 i = stm32mp1_clk_get_gated_id(id); 747 if (i < 0) { 748 panic(); 749 } 750 751 p = stm32mp1_clk_get_fixed_parent(i); 752 if (p < _PARENT_NB) { 753 return (int)p; 754 } 755 756 s = stm32mp1_clk_get_sel(i); 757 if (s == _UNKNOWN_SEL) { 758 return -EINVAL; 759 } 760 if (s >= _PARENT_SEL_NB) { 761 panic(); 762 } 763 764 sel = clk_sel_ref(s); 765 p_sel = (mmio_read_32(rcc_base + sel->offset) & 766 (sel->msk << sel->src)) >> sel->src; 767 if (p_sel < sel->nb_parent) { 768 return (int)sel->parent[p_sel]; 769 } 770 771 return -EINVAL; 772 } 773 774 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 775 { 776 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 777 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 778 779 return stm32mp1_clk_get_fixed(pll->refclk[src]); 780 } 781 782 /* 783 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 784 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 785 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 786 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 787 */ 788 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 789 { 790 unsigned long refclk, fvco; 791 uint32_t cfgr1, fracr, divm, divn; 792 uintptr_t rcc_base = stm32mp_rcc_base(); 793 794 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 795 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 796 797 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 798 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 799 800 refclk = stm32mp1_pll_get_fref(pll); 801 802 /* 803 * With FRACV : 804 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 805 * Without FRACV 806 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 807 */ 808 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 809 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 810 RCC_PLLNFRACR_FRACV_SHIFT; 811 unsigned long long numerator, denominator; 812 813 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 814 numerator = refclk * numerator; 815 denominator = ((unsigned long long)divm + 1U) << 13; 816 fvco = (unsigned long)(numerator / denominator); 817 } else { 818 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 819 } 820 821 return fvco; 822 } 823 824 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 825 enum stm32mp1_div_id div_id) 826 { 827 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 828 unsigned long dfout; 829 uint32_t cfgr2, divy; 830 831 if (div_id >= _DIV_NB) { 832 return 0; 833 } 834 835 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 836 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 837 838 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 839 840 return dfout; 841 } 842 843 static unsigned long get_clock_rate(int p) 844 { 845 uint32_t reg, clkdiv; 846 unsigned long clock = 0; 847 uintptr_t rcc_base = stm32mp_rcc_base(); 848 849 switch (p) { 850 case _CK_MPU: 851 /* MPU sub system */ 852 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 853 switch (reg & RCC_SELR_SRC_MASK) { 854 case RCC_MPCKSELR_HSI: 855 clock = stm32mp1_clk_get_fixed(_HSI); 856 break; 857 case RCC_MPCKSELR_HSE: 858 clock = stm32mp1_clk_get_fixed(_HSE); 859 break; 860 case RCC_MPCKSELR_PLL: 861 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 862 break; 863 case RCC_MPCKSELR_PLL_MPUDIV: 864 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 865 866 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 867 clkdiv = reg & RCC_MPUDIV_MASK; 868 clock >>= stm32mp1_mpu_div[clkdiv]; 869 break; 870 default: 871 break; 872 } 873 break; 874 /* AXI sub system */ 875 case _ACLK: 876 case _HCLK2: 877 case _HCLK6: 878 case _PCLK4: 879 case _PCLK5: 880 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 881 switch (reg & RCC_SELR_SRC_MASK) { 882 case RCC_ASSCKSELR_HSI: 883 clock = stm32mp1_clk_get_fixed(_HSI); 884 break; 885 case RCC_ASSCKSELR_HSE: 886 clock = stm32mp1_clk_get_fixed(_HSE); 887 break; 888 case RCC_ASSCKSELR_PLL: 889 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 890 break; 891 default: 892 break; 893 } 894 895 /* System clock divider */ 896 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 897 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 898 899 switch (p) { 900 case _PCLK4: 901 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 902 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 903 break; 904 case _PCLK5: 905 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 906 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 907 break; 908 default: 909 break; 910 } 911 break; 912 /* MCU sub system */ 913 case _CK_MCU: 914 case _PCLK1: 915 case _PCLK2: 916 case _PCLK3: 917 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 918 switch (reg & RCC_SELR_SRC_MASK) { 919 case RCC_MSSCKSELR_HSI: 920 clock = stm32mp1_clk_get_fixed(_HSI); 921 break; 922 case RCC_MSSCKSELR_HSE: 923 clock = stm32mp1_clk_get_fixed(_HSE); 924 break; 925 case RCC_MSSCKSELR_CSI: 926 clock = stm32mp1_clk_get_fixed(_CSI); 927 break; 928 case RCC_MSSCKSELR_PLL: 929 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 930 break; 931 default: 932 break; 933 } 934 935 /* MCU clock divider */ 936 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 937 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 938 939 switch (p) { 940 case _PCLK1: 941 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 942 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 943 break; 944 case _PCLK2: 945 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 946 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 947 break; 948 case _PCLK3: 949 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 950 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 951 break; 952 case _CK_MCU: 953 default: 954 break; 955 } 956 break; 957 case _CK_PER: 958 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 959 switch (reg & RCC_SELR_SRC_MASK) { 960 case RCC_CPERCKSELR_HSI: 961 clock = stm32mp1_clk_get_fixed(_HSI); 962 break; 963 case RCC_CPERCKSELR_HSE: 964 clock = stm32mp1_clk_get_fixed(_HSE); 965 break; 966 case RCC_CPERCKSELR_CSI: 967 clock = stm32mp1_clk_get_fixed(_CSI); 968 break; 969 default: 970 break; 971 } 972 break; 973 case _HSI: 974 case _HSI_KER: 975 clock = stm32mp1_clk_get_fixed(_HSI); 976 break; 977 case _CSI: 978 case _CSI_KER: 979 clock = stm32mp1_clk_get_fixed(_CSI); 980 break; 981 case _HSE: 982 case _HSE_KER: 983 clock = stm32mp1_clk_get_fixed(_HSE); 984 break; 985 case _HSE_KER_DIV2: 986 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 987 break; 988 case _HSE_RTC: 989 clock = stm32mp1_clk_get_fixed(_HSE); 990 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 991 break; 992 case _LSI: 993 clock = stm32mp1_clk_get_fixed(_LSI); 994 break; 995 case _LSE: 996 clock = stm32mp1_clk_get_fixed(_LSE); 997 break; 998 /* PLL */ 999 case _PLL1_P: 1000 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1001 break; 1002 case _PLL1_Q: 1003 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1004 break; 1005 case _PLL1_R: 1006 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1007 break; 1008 case _PLL2_P: 1009 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1010 break; 1011 case _PLL2_Q: 1012 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1013 break; 1014 case _PLL2_R: 1015 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1016 break; 1017 case _PLL3_P: 1018 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1019 break; 1020 case _PLL3_Q: 1021 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1022 break; 1023 case _PLL3_R: 1024 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1025 break; 1026 case _PLL4_P: 1027 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1028 break; 1029 case _PLL4_Q: 1030 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1031 break; 1032 case _PLL4_R: 1033 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1034 break; 1035 /* Other */ 1036 case _USB_PHY_48: 1037 clock = USB_PHY_48_MHZ; 1038 break; 1039 default: 1040 break; 1041 } 1042 1043 return clock; 1044 } 1045 1046 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1047 { 1048 uintptr_t rcc_base = stm32mp_rcc_base(); 1049 1050 VERBOSE("Enable clock %u\n", gate->index); 1051 1052 if (gate->set_clr != 0U) { 1053 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1054 } else { 1055 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1056 } 1057 } 1058 1059 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1060 { 1061 uintptr_t rcc_base = stm32mp_rcc_base(); 1062 1063 VERBOSE("Disable clock %u\n", gate->index); 1064 1065 if (gate->set_clr != 0U) { 1066 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1067 BIT(gate->bit)); 1068 } else { 1069 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1070 } 1071 } 1072 1073 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1074 { 1075 uintptr_t rcc_base = stm32mp_rcc_base(); 1076 1077 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1078 } 1079 1080 /* Oscillators and PLLs are not gated at runtime */ 1081 static bool clock_is_always_on(unsigned long id) 1082 { 1083 switch (id) { 1084 case CK_HSE: 1085 case CK_CSI: 1086 case CK_LSI: 1087 case CK_LSE: 1088 case CK_HSI: 1089 case CK_HSE_DIV2: 1090 case PLL1_Q: 1091 case PLL1_R: 1092 case PLL2_P: 1093 case PLL2_Q: 1094 case PLL2_R: 1095 case PLL3_P: 1096 case PLL3_Q: 1097 case PLL3_R: 1098 case CK_AXI: 1099 case CK_MPU: 1100 case CK_MCU: 1101 case RTC: 1102 return true; 1103 default: 1104 return false; 1105 } 1106 } 1107 1108 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1109 { 1110 const struct stm32mp1_clk_gate *gate; 1111 int i; 1112 1113 if (clock_is_always_on(id)) { 1114 return; 1115 } 1116 1117 i = stm32mp1_clk_get_gated_id(id); 1118 if (i < 0) { 1119 ERROR("Clock %lu can't be enabled\n", id); 1120 panic(); 1121 } 1122 1123 gate = gate_ref(i); 1124 1125 if (!with_refcnt) { 1126 __clk_enable(gate); 1127 return; 1128 } 1129 1130 #if defined(IMAGE_BL32) 1131 if (gate_is_non_secure(gate)) { 1132 /* Enable non-secure clock w/o any refcounting */ 1133 __clk_enable(gate); 1134 return; 1135 } 1136 #endif 1137 1138 stm32mp1_clk_lock(&refcount_lock); 1139 1140 if (gate_refcounts[i] == 0U) { 1141 __clk_enable(gate); 1142 } 1143 1144 gate_refcounts[i]++; 1145 if (gate_refcounts[i] == UINT_MAX) { 1146 ERROR("Clock %lu refcount reached max value\n", id); 1147 panic(); 1148 } 1149 1150 stm32mp1_clk_unlock(&refcount_lock); 1151 } 1152 1153 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1154 { 1155 const struct stm32mp1_clk_gate *gate; 1156 int i; 1157 1158 if (clock_is_always_on(id)) { 1159 return; 1160 } 1161 1162 i = stm32mp1_clk_get_gated_id(id); 1163 if (i < 0) { 1164 ERROR("Clock %lu can't be disabled\n", id); 1165 panic(); 1166 } 1167 1168 gate = gate_ref(i); 1169 1170 if (!with_refcnt) { 1171 __clk_disable(gate); 1172 return; 1173 } 1174 1175 #if defined(IMAGE_BL32) 1176 if (gate_is_non_secure(gate)) { 1177 /* Don't disable non-secure clocks */ 1178 return; 1179 } 1180 #endif 1181 1182 stm32mp1_clk_lock(&refcount_lock); 1183 1184 if (gate_refcounts[i] == 0U) { 1185 ERROR("Clock %lu refcount reached 0\n", id); 1186 panic(); 1187 } 1188 gate_refcounts[i]--; 1189 1190 if (gate_refcounts[i] == 0U) { 1191 __clk_disable(gate); 1192 } 1193 1194 stm32mp1_clk_unlock(&refcount_lock); 1195 } 1196 1197 static int stm32mp_clk_enable(unsigned long id) 1198 { 1199 __stm32mp1_clk_enable(id, true); 1200 1201 return 0; 1202 } 1203 1204 static void stm32mp_clk_disable(unsigned long id) 1205 { 1206 __stm32mp1_clk_disable(id, true); 1207 } 1208 1209 static bool stm32mp_clk_is_enabled(unsigned long id) 1210 { 1211 int i; 1212 1213 if (clock_is_always_on(id)) { 1214 return true; 1215 } 1216 1217 i = stm32mp1_clk_get_gated_id(id); 1218 if (i < 0) { 1219 panic(); 1220 } 1221 1222 return __clk_is_enabled(gate_ref(i)); 1223 } 1224 1225 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1226 { 1227 uintptr_t rcc_base = stm32mp_rcc_base(); 1228 int p = stm32mp1_clk_get_parent(id); 1229 uint32_t prescaler, timpre; 1230 unsigned long parent_rate; 1231 1232 if (p < 0) { 1233 return 0; 1234 } 1235 1236 parent_rate = get_clock_rate(p); 1237 1238 switch (id) { 1239 case TIM2_K: 1240 case TIM3_K: 1241 case TIM4_K: 1242 case TIM5_K: 1243 case TIM6_K: 1244 case TIM7_K: 1245 case TIM12_K: 1246 case TIM13_K: 1247 case TIM14_K: 1248 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1249 RCC_APBXDIV_MASK; 1250 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1251 RCC_TIMGXPRER_TIMGXPRE; 1252 break; 1253 1254 case TIM1_K: 1255 case TIM8_K: 1256 case TIM15_K: 1257 case TIM16_K: 1258 case TIM17_K: 1259 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1260 RCC_APBXDIV_MASK; 1261 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1262 RCC_TIMGXPRER_TIMGXPRE; 1263 break; 1264 1265 default: 1266 return parent_rate; 1267 } 1268 1269 if (prescaler == 0U) { 1270 return parent_rate; 1271 } 1272 1273 return parent_rate * (timpre + 1U) * 2U; 1274 } 1275 1276 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1277 { 1278 uintptr_t address = stm32mp_rcc_base() + offset; 1279 1280 if (enable) { 1281 mmio_setbits_32(address, mask_on); 1282 } else { 1283 mmio_clrbits_32(address, mask_on); 1284 } 1285 } 1286 1287 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1288 { 1289 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1290 uintptr_t address = stm32mp_rcc_base() + offset; 1291 1292 mmio_write_32(address, mask_on); 1293 } 1294 1295 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1296 { 1297 uint64_t timeout; 1298 uint32_t mask_test; 1299 uintptr_t address = stm32mp_rcc_base() + offset; 1300 1301 if (enable) { 1302 mask_test = mask_rdy; 1303 } else { 1304 mask_test = 0; 1305 } 1306 1307 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1308 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1309 if (timeout_elapsed(timeout)) { 1310 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1311 mask_rdy, address, enable, mmio_read_32(address)); 1312 return -ETIMEDOUT; 1313 } 1314 } 1315 1316 return 0; 1317 } 1318 1319 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1320 { 1321 uint32_t value; 1322 uintptr_t rcc_base = stm32mp_rcc_base(); 1323 1324 if (digbyp) { 1325 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1326 } 1327 1328 if (bypass || digbyp) { 1329 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1330 } 1331 1332 /* 1333 * Warning: not recommended to switch directly from "high drive" 1334 * to "medium low drive", and vice-versa. 1335 */ 1336 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1337 RCC_BDCR_LSEDRV_SHIFT; 1338 1339 while (value != lsedrv) { 1340 if (value > lsedrv) { 1341 value--; 1342 } else { 1343 value++; 1344 } 1345 1346 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1347 RCC_BDCR_LSEDRV_MASK, 1348 value << RCC_BDCR_LSEDRV_SHIFT); 1349 } 1350 1351 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1352 } 1353 1354 static void stm32mp1_lse_wait(void) 1355 { 1356 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1357 VERBOSE("%s: failed\n", __func__); 1358 } 1359 } 1360 1361 static void stm32mp1_lsi_set(bool enable) 1362 { 1363 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1364 1365 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1366 VERBOSE("%s: failed\n", __func__); 1367 } 1368 } 1369 1370 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1371 { 1372 uintptr_t rcc_base = stm32mp_rcc_base(); 1373 1374 if (digbyp) { 1375 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1376 } 1377 1378 if (bypass || digbyp) { 1379 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1380 } 1381 1382 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1383 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1384 VERBOSE("%s: failed\n", __func__); 1385 } 1386 1387 if (css) { 1388 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1389 } 1390 1391 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1392 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1393 (!(digbyp || bypass))) { 1394 panic(); 1395 } 1396 #endif 1397 } 1398 1399 static void stm32mp1_csi_set(bool enable) 1400 { 1401 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1402 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1403 VERBOSE("%s: failed\n", __func__); 1404 } 1405 } 1406 1407 static void stm32mp1_hsi_set(bool enable) 1408 { 1409 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1410 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1411 VERBOSE("%s: failed\n", __func__); 1412 } 1413 } 1414 1415 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1416 { 1417 uint64_t timeout; 1418 uintptr_t rcc_base = stm32mp_rcc_base(); 1419 uintptr_t address = rcc_base + RCC_OCRDYR; 1420 1421 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1422 RCC_HSICFGR_HSIDIV_MASK, 1423 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1424 1425 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1426 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1427 if (timeout_elapsed(timeout)) { 1428 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1429 address, mmio_read_32(address)); 1430 return -ETIMEDOUT; 1431 } 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int stm32mp1_hsidiv(unsigned long hsifreq) 1438 { 1439 uint8_t hsidiv; 1440 uint32_t hsidivfreq = MAX_HSI_HZ; 1441 1442 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1443 if (hsidivfreq == hsifreq) { 1444 break; 1445 } 1446 1447 hsidivfreq /= 2U; 1448 } 1449 1450 if (hsidiv == 4U) { 1451 ERROR("Invalid clk-hsi frequency\n"); 1452 return -1; 1453 } 1454 1455 if (hsidiv != 0U) { 1456 return stm32mp1_set_hsidiv(hsidiv); 1457 } 1458 1459 return 0; 1460 } 1461 1462 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1463 unsigned int clksrc, 1464 uint32_t *pllcfg, int plloff) 1465 { 1466 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1467 uintptr_t rcc_base = stm32mp_rcc_base(); 1468 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1469 enum stm32mp1_plltype type = pll->plltype; 1470 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1471 unsigned long refclk; 1472 uint32_t ifrge = 0U; 1473 uint32_t src, value, fracv = 0; 1474 void *fdt; 1475 1476 /* Check PLL output */ 1477 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1478 return false; 1479 } 1480 1481 /* Check current clksrc */ 1482 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1483 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1484 return false; 1485 } 1486 1487 /* Check Div */ 1488 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1489 1490 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1491 (pllcfg[PLLCFG_M] + 1U); 1492 1493 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1494 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1495 return false; 1496 } 1497 1498 if ((type == PLL_800) && (refclk >= 8000000U)) { 1499 ifrge = 1U; 1500 } 1501 1502 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1503 RCC_PLLNCFGR1_DIVN_MASK; 1504 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1505 RCC_PLLNCFGR1_DIVM_MASK; 1506 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1507 RCC_PLLNCFGR1_IFRGE_MASK; 1508 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1509 return false; 1510 } 1511 1512 /* Fractional configuration */ 1513 if (fdt_get_address(&fdt) == 1) { 1514 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1515 } 1516 1517 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1518 value |= RCC_PLLNFRACR_FRACLE; 1519 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1520 return false; 1521 } 1522 1523 /* Output config */ 1524 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1525 RCC_PLLNCFGR2_DIVP_MASK; 1526 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1527 RCC_PLLNCFGR2_DIVQ_MASK; 1528 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1529 RCC_PLLNCFGR2_DIVR_MASK; 1530 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1531 return false; 1532 } 1533 1534 return true; 1535 } 1536 1537 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1538 { 1539 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1540 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1541 1542 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1543 mmio_clrsetbits_32(pllxcr, 1544 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1545 RCC_PLLNCR_DIVREN, 1546 RCC_PLLNCR_PLLON); 1547 } 1548 1549 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1550 { 1551 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1552 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1553 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1554 1555 /* Wait PLL lock */ 1556 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1557 if (timeout_elapsed(timeout)) { 1558 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1559 pll_id, pllxcr, mmio_read_32(pllxcr)); 1560 return -ETIMEDOUT; 1561 } 1562 } 1563 1564 /* Start the requested output */ 1565 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1566 1567 return 0; 1568 } 1569 1570 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1571 { 1572 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1573 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1574 uint64_t timeout; 1575 1576 /* Stop all output */ 1577 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1578 RCC_PLLNCR_DIVREN); 1579 1580 /* Stop PLL */ 1581 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1582 1583 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1584 /* Wait PLL stopped */ 1585 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1586 if (timeout_elapsed(timeout)) { 1587 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1588 pll_id, pllxcr, mmio_read_32(pllxcr)); 1589 return -ETIMEDOUT; 1590 } 1591 } 1592 1593 return 0; 1594 } 1595 1596 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1597 uint32_t *pllcfg) 1598 { 1599 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1600 uintptr_t rcc_base = stm32mp_rcc_base(); 1601 uint32_t value; 1602 1603 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1604 RCC_PLLNCFGR2_DIVP_MASK; 1605 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1606 RCC_PLLNCFGR2_DIVQ_MASK; 1607 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1608 RCC_PLLNCFGR2_DIVR_MASK; 1609 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1610 } 1611 1612 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1613 uint32_t *pllcfg, uint32_t fracv) 1614 { 1615 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1616 uintptr_t rcc_base = stm32mp_rcc_base(); 1617 enum stm32mp1_plltype type = pll->plltype; 1618 unsigned long refclk; 1619 uint32_t ifrge = 0; 1620 uint32_t src, value; 1621 1622 src = mmio_read_32(rcc_base + pll->rckxselr) & 1623 RCC_SELR_REFCLK_SRC_MASK; 1624 1625 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1626 (pllcfg[PLLCFG_M] + 1U); 1627 1628 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1629 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1630 return -EINVAL; 1631 } 1632 1633 if ((type == PLL_800) && (refclk >= 8000000U)) { 1634 ifrge = 1U; 1635 } 1636 1637 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1638 RCC_PLLNCFGR1_DIVN_MASK; 1639 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1640 RCC_PLLNCFGR1_DIVM_MASK; 1641 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1642 RCC_PLLNCFGR1_IFRGE_MASK; 1643 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1644 1645 /* Fractional configuration */ 1646 value = 0; 1647 mmio_write_32(rcc_base + pll->pllxfracr, value); 1648 1649 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1650 mmio_write_32(rcc_base + pll->pllxfracr, value); 1651 1652 value |= RCC_PLLNFRACR_FRACLE; 1653 mmio_write_32(rcc_base + pll->pllxfracr, value); 1654 1655 stm32mp1_pll_config_output(pll_id, pllcfg); 1656 1657 return 0; 1658 } 1659 1660 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1661 { 1662 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1663 uint32_t pllxcsg = 0; 1664 1665 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1666 RCC_PLLNCSGR_MOD_PER_MASK; 1667 1668 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1669 RCC_PLLNCSGR_INC_STEP_MASK; 1670 1671 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1672 RCC_PLLNCSGR_SSCG_MODE_MASK; 1673 1674 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1675 1676 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1677 RCC_PLLNCR_SSCG_CTRL); 1678 } 1679 1680 static int stm32mp1_set_clksrc(unsigned int clksrc) 1681 { 1682 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1683 uint64_t timeout; 1684 1685 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1686 clksrc & RCC_SELR_SRC_MASK); 1687 1688 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1689 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1690 if (timeout_elapsed(timeout)) { 1691 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1692 clksrc_address, mmio_read_32(clksrc_address)); 1693 return -ETIMEDOUT; 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1701 { 1702 uint64_t timeout; 1703 1704 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1705 clkdiv & RCC_DIVR_DIV_MASK); 1706 1707 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1708 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1709 if (timeout_elapsed(timeout)) { 1710 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1711 clkdiv, address, mmio_read_32(address)); 1712 return -ETIMEDOUT; 1713 } 1714 } 1715 1716 return 0; 1717 } 1718 1719 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1720 { 1721 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1722 1723 /* 1724 * Binding clksrc : 1725 * bit15-4 offset 1726 * bit3: disable 1727 * bit2-0: MCOSEL[2:0] 1728 */ 1729 if ((clksrc & 0x8U) != 0U) { 1730 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1731 } else { 1732 mmio_clrsetbits_32(clksrc_address, 1733 RCC_MCOCFG_MCOSRC_MASK, 1734 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1735 mmio_clrsetbits_32(clksrc_address, 1736 RCC_MCOCFG_MCODIV_MASK, 1737 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1738 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1739 } 1740 } 1741 1742 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1743 { 1744 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1745 1746 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1747 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1748 mmio_clrsetbits_32(address, 1749 RCC_BDCR_RTCSRC_MASK, 1750 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1751 1752 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1753 } 1754 1755 if (lse_css) { 1756 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1757 } 1758 } 1759 1760 static void stm32mp1_stgen_config(void) 1761 { 1762 uint32_t cntfid0; 1763 unsigned long rate; 1764 unsigned long long counter; 1765 1766 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1767 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1768 1769 if (cntfid0 == rate) { 1770 return; 1771 } 1772 1773 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1774 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1775 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1776 counter = (counter * rate / cntfid0); 1777 1778 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1779 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1780 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1781 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1782 1783 write_cntfrq((u_register_t)rate); 1784 1785 /* Need to update timer with new frequency */ 1786 generic_delay_timer_init(); 1787 } 1788 1789 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1790 { 1791 unsigned long long cnt; 1792 1793 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1794 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1795 1796 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1797 1798 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1799 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1800 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1801 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1802 } 1803 1804 static void stm32mp1_pkcs_config(uint32_t pkcs) 1805 { 1806 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1807 uint32_t value = pkcs & 0xFU; 1808 uint32_t mask = 0xFU; 1809 1810 if ((pkcs & BIT(31)) != 0U) { 1811 mask <<= 4; 1812 value <<= 4; 1813 } 1814 1815 mmio_clrsetbits_32(address, mask, value); 1816 } 1817 1818 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1819 uint32_t *fracv, uint32_t *csg, 1820 bool *csg_set) 1821 { 1822 void *fdt; 1823 int ret; 1824 1825 if (fdt_get_address(&fdt) == 0) { 1826 return -FDT_ERR_NOTFOUND; 1827 } 1828 1829 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1830 pllcfg); 1831 if (ret < 0) { 1832 return -FDT_ERR_NOTFOUND; 1833 } 1834 1835 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1836 1837 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1838 csg); 1839 1840 *csg_set = (ret == 0); 1841 1842 if (ret == -FDT_ERR_NOTFOUND) { 1843 ret = 0; 1844 } 1845 1846 return ret; 1847 } 1848 1849 int stm32mp1_clk_init(void) 1850 { 1851 uintptr_t rcc_base = stm32mp_rcc_base(); 1852 uint32_t pllfracv[_PLL_NB]; 1853 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1854 unsigned int clksrc[CLKSRC_NB]; 1855 unsigned int clkdiv[CLKDIV_NB]; 1856 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1857 int plloff[_PLL_NB]; 1858 int ret, len; 1859 enum stm32mp1_pll_id i; 1860 bool pllcsg_set[_PLL_NB]; 1861 bool pllcfg_valid[_PLL_NB]; 1862 bool lse_css = false; 1863 bool pll3_preserve = false; 1864 bool pll4_preserve = false; 1865 bool pll4_bootrom = false; 1866 const fdt32_t *pkcs_cell; 1867 void *fdt; 1868 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1869 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1870 1871 if (fdt_get_address(&fdt) == 0) { 1872 return -FDT_ERR_NOTFOUND; 1873 } 1874 1875 /* Check status field to disable security */ 1876 if (!fdt_get_rcc_secure_status()) { 1877 mmio_write_32(rcc_base + RCC_TZCR, 0); 1878 } 1879 1880 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1881 clksrc); 1882 if (ret < 0) { 1883 return -FDT_ERR_NOTFOUND; 1884 } 1885 1886 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1887 clkdiv); 1888 if (ret < 0) { 1889 return -FDT_ERR_NOTFOUND; 1890 } 1891 1892 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1893 char name[12]; 1894 1895 snprintf(name, sizeof(name), "st,pll@%d", i); 1896 plloff[i] = fdt_rcc_subnode_offset(name); 1897 1898 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1899 if (!pllcfg_valid[i]) { 1900 continue; 1901 } 1902 1903 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1904 &pllfracv[i], pllcsg[i], 1905 &pllcsg_set[i]); 1906 if (ret != 0) { 1907 return ret; 1908 } 1909 } 1910 1911 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1912 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1913 1914 /* 1915 * Switch ON oscillator found in device-tree. 1916 * Note: HSI already ON after BootROM stage. 1917 */ 1918 if (stm32mp1_osc[_LSI] != 0U) { 1919 stm32mp1_lsi_set(true); 1920 } 1921 if (stm32mp1_osc[_LSE] != 0U) { 1922 const char *name = stm32mp_osc_node_label[_LSE]; 1923 bool bypass, digbyp; 1924 uint32_t lsedrv; 1925 1926 bypass = fdt_clk_read_bool(name, "st,bypass"); 1927 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1928 lse_css = fdt_clk_read_bool(name, "st,css"); 1929 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1930 LSEDRV_MEDIUM_HIGH); 1931 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1932 } 1933 if (stm32mp1_osc[_HSE] != 0U) { 1934 const char *name = stm32mp_osc_node_label[_HSE]; 1935 bool bypass, digbyp, css; 1936 1937 bypass = fdt_clk_read_bool(name, "st,bypass"); 1938 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1939 css = fdt_clk_read_bool(name, "st,css"); 1940 stm32mp1_hse_enable(bypass, digbyp, css); 1941 } 1942 /* 1943 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1944 * => switch on CSI even if node is not present in device tree 1945 */ 1946 stm32mp1_csi_set(true); 1947 1948 /* Come back to HSI */ 1949 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1950 if (ret != 0) { 1951 return ret; 1952 } 1953 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1954 if (ret != 0) { 1955 return ret; 1956 } 1957 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1958 if (ret != 0) { 1959 return ret; 1960 } 1961 1962 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1963 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1964 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1965 clksrc[CLKSRC_PLL3], 1966 pllcfg[_PLL3], 1967 plloff[_PLL3]); 1968 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1969 clksrc[CLKSRC_PLL4], 1970 pllcfg[_PLL4], 1971 plloff[_PLL4]); 1972 } 1973 /* Don't initialize PLL4, when used by BOOTROM */ 1974 if ((stm32mp_get_boot_itf_selected() == 1975 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1976 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1977 pll4_bootrom = true; 1978 pll4_preserve = true; 1979 } 1980 1981 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1982 if (((i == _PLL3) && pll3_preserve) || 1983 ((i == _PLL4) && pll4_preserve)) { 1984 continue; 1985 } 1986 1987 ret = stm32mp1_pll_stop(i); 1988 if (ret != 0) { 1989 return ret; 1990 } 1991 } 1992 1993 /* Configure HSIDIV */ 1994 if (stm32mp1_osc[_HSI] != 0U) { 1995 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1996 if (ret != 0) { 1997 return ret; 1998 } 1999 stm32mp1_stgen_config(); 2000 } 2001 2002 /* Select DIV */ 2003 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 2004 mmio_write_32(rcc_base + RCC_MPCKDIVR, 2005 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 2006 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 2007 if (ret != 0) { 2008 return ret; 2009 } 2010 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 2011 if (ret != 0) { 2012 return ret; 2013 } 2014 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 2015 if (ret != 0) { 2016 return ret; 2017 } 2018 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 2019 if (ret != 0) { 2020 return ret; 2021 } 2022 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 2023 if (ret != 0) { 2024 return ret; 2025 } 2026 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 2027 if (ret != 0) { 2028 return ret; 2029 } 2030 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 2031 if (ret != 0) { 2032 return ret; 2033 } 2034 2035 /* No ready bit for RTC */ 2036 mmio_write_32(rcc_base + RCC_RTCDIVR, 2037 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2038 2039 /* Configure PLLs source */ 2040 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2041 if (ret != 0) { 2042 return ret; 2043 } 2044 2045 if (!pll3_preserve) { 2046 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2047 if (ret != 0) { 2048 return ret; 2049 } 2050 } 2051 2052 if (!pll4_preserve) { 2053 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2054 if (ret != 0) { 2055 return ret; 2056 } 2057 } 2058 2059 /* Configure and start PLLs */ 2060 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2061 if (((i == _PLL3) && pll3_preserve) || 2062 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2063 continue; 2064 } 2065 2066 if (!pllcfg_valid[i]) { 2067 continue; 2068 } 2069 2070 if ((i == _PLL4) && pll4_bootrom) { 2071 /* Set output divider if not done by the Bootrom */ 2072 stm32mp1_pll_config_output(i, pllcfg[i]); 2073 continue; 2074 } 2075 2076 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2077 if (ret != 0) { 2078 return ret; 2079 } 2080 2081 if (pllcsg_set[i]) { 2082 stm32mp1_pll_csg(i, pllcsg[i]); 2083 } 2084 2085 stm32mp1_pll_start(i); 2086 } 2087 /* Wait and start PLLs ouptut when ready */ 2088 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2089 if (!pllcfg_valid[i]) { 2090 continue; 2091 } 2092 2093 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2094 if (ret != 0) { 2095 return ret; 2096 } 2097 } 2098 /* Wait LSE ready before to use it */ 2099 if (stm32mp1_osc[_LSE] != 0U) { 2100 stm32mp1_lse_wait(); 2101 } 2102 2103 /* Configure with expected clock source */ 2104 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2105 if (ret != 0) { 2106 return ret; 2107 } 2108 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2109 if (ret != 0) { 2110 return ret; 2111 } 2112 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2113 if (ret != 0) { 2114 return ret; 2115 } 2116 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2117 2118 /* Configure PKCK */ 2119 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2120 if (pkcs_cell != NULL) { 2121 bool ckper_disabled = false; 2122 uint32_t j; 2123 uint32_t usbreg_bootrom = 0U; 2124 2125 if (pll4_bootrom) { 2126 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2127 } 2128 2129 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2130 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2131 2132 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2133 ckper_disabled = true; 2134 continue; 2135 } 2136 stm32mp1_pkcs_config(pkcs); 2137 } 2138 2139 /* 2140 * CKPER is source for some peripheral clocks 2141 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2142 * only if previous clock is still ON 2143 * => deactivated CKPER only after switching clock 2144 */ 2145 if (ckper_disabled) { 2146 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2147 } 2148 2149 if (pll4_bootrom) { 2150 uint32_t usbreg_value, usbreg_mask; 2151 const struct stm32mp1_clk_sel *sel; 2152 2153 sel = clk_sel_ref(_USBPHY_SEL); 2154 usbreg_mask = (uint32_t)sel->msk << sel->src; 2155 sel = clk_sel_ref(_USBO_SEL); 2156 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2157 2158 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2159 usbreg_mask; 2160 usbreg_bootrom &= usbreg_mask; 2161 if (usbreg_bootrom != usbreg_value) { 2162 VERBOSE("forbidden new USB clk path\n"); 2163 VERBOSE("vs bootrom on USB boot\n"); 2164 return -FDT_ERR_BADVALUE; 2165 } 2166 } 2167 } 2168 2169 /* Switch OFF HSI if not found in device-tree */ 2170 if (stm32mp1_osc[_HSI] == 0U) { 2171 stm32mp1_hsi_set(false); 2172 } 2173 stm32mp1_stgen_config(); 2174 2175 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2176 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2177 RCC_DDRITFCR_DDRCKMOD_MASK, 2178 RCC_DDRITFCR_DDRCKMOD_SSR << 2179 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2180 2181 return 0; 2182 } 2183 2184 static void stm32mp1_osc_clk_init(const char *name, 2185 enum stm32mp_osc_id index) 2186 { 2187 uint32_t frequency; 2188 2189 if (fdt_osc_read_freq(name, &frequency) == 0) { 2190 stm32mp1_osc[index] = frequency; 2191 } 2192 } 2193 2194 static void stm32mp1_osc_init(void) 2195 { 2196 enum stm32mp_osc_id i; 2197 2198 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2199 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2200 } 2201 } 2202 2203 #ifdef STM32MP_SHARED_RESOURCES 2204 /* 2205 * Get the parent ID of the target parent clock, for tagging as secure 2206 * shared clock dependencies. 2207 */ 2208 static int get_parent_id_parent(unsigned int parent_id) 2209 { 2210 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2211 enum stm32mp1_pll_id pll_id; 2212 uint32_t p_sel; 2213 uintptr_t rcc_base = stm32mp_rcc_base(); 2214 2215 switch (parent_id) { 2216 case _ACLK: 2217 case _PCLK4: 2218 case _PCLK5: 2219 s = _AXIS_SEL; 2220 break; 2221 case _PLL1_P: 2222 case _PLL1_Q: 2223 case _PLL1_R: 2224 pll_id = _PLL1; 2225 break; 2226 case _PLL2_P: 2227 case _PLL2_Q: 2228 case _PLL2_R: 2229 pll_id = _PLL2; 2230 break; 2231 case _PLL3_P: 2232 case _PLL3_Q: 2233 case _PLL3_R: 2234 pll_id = _PLL3; 2235 break; 2236 case _PLL4_P: 2237 case _PLL4_Q: 2238 case _PLL4_R: 2239 pll_id = _PLL4; 2240 break; 2241 case _PCLK1: 2242 case _PCLK2: 2243 case _HCLK2: 2244 case _HCLK6: 2245 case _CK_PER: 2246 case _CK_MPU: 2247 case _CK_MCU: 2248 case _USB_PHY_48: 2249 /* We do not expect to access these */ 2250 panic(); 2251 break; 2252 default: 2253 /* Other parents have no parent */ 2254 return -1; 2255 } 2256 2257 if (s != _UNKNOWN_SEL) { 2258 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2259 2260 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2261 sel->msk; 2262 2263 if (p_sel < sel->nb_parent) { 2264 return (int)sel->parent[p_sel]; 2265 } 2266 } else { 2267 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2268 2269 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2270 RCC_SELR_REFCLK_SRC_MASK; 2271 2272 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2273 return (int)pll->refclk[p_sel]; 2274 } 2275 } 2276 2277 VERBOSE("No parent selected for %s\n", 2278 stm32mp1_clk_parent_name[parent_id]); 2279 2280 return -1; 2281 } 2282 2283 static void secure_parent_clocks(unsigned long parent_id) 2284 { 2285 int grandparent_id; 2286 2287 switch (parent_id) { 2288 case _PLL3_P: 2289 case _PLL3_Q: 2290 case _PLL3_R: 2291 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2292 break; 2293 2294 /* These clocks are always secure when RCC is secure */ 2295 case _ACLK: 2296 case _HCLK2: 2297 case _HCLK6: 2298 case _PCLK4: 2299 case _PCLK5: 2300 case _PLL1_P: 2301 case _PLL1_Q: 2302 case _PLL1_R: 2303 case _PLL2_P: 2304 case _PLL2_Q: 2305 case _PLL2_R: 2306 case _HSI: 2307 case _HSI_KER: 2308 case _LSI: 2309 case _CSI: 2310 case _CSI_KER: 2311 case _HSE: 2312 case _HSE_KER: 2313 case _HSE_KER_DIV2: 2314 case _HSE_RTC: 2315 case _LSE: 2316 break; 2317 2318 default: 2319 VERBOSE("Cannot secure parent clock %s\n", 2320 stm32mp1_clk_parent_name[parent_id]); 2321 panic(); 2322 } 2323 2324 grandparent_id = get_parent_id_parent(parent_id); 2325 if (grandparent_id >= 0) { 2326 secure_parent_clocks(grandparent_id); 2327 } 2328 } 2329 2330 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2331 { 2332 int parent_id; 2333 2334 if (!stm32mp1_rcc_is_secure()) { 2335 return; 2336 } 2337 2338 switch (clock_id) { 2339 case PLL1: 2340 case PLL2: 2341 /* PLL1/PLL2 are always secure: nothing to do */ 2342 break; 2343 case PLL3: 2344 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2345 break; 2346 case PLL4: 2347 ERROR("PLL4 cannot be secured\n"); 2348 panic(); 2349 break; 2350 default: 2351 /* Others are expected gateable clock */ 2352 parent_id = stm32mp1_clk_get_parent(clock_id); 2353 if (parent_id < 0) { 2354 INFO("No parent found for clock %lu\n", clock_id); 2355 } else { 2356 secure_parent_clocks(parent_id); 2357 } 2358 break; 2359 } 2360 } 2361 #endif /* STM32MP_SHARED_RESOURCES */ 2362 2363 static void sync_earlyboot_clocks_state(void) 2364 { 2365 unsigned int idx; 2366 const unsigned long secure_enable[] = { 2367 AXIDCG, 2368 BSEC, 2369 DDRC1, DDRC1LP, 2370 DDRC2, DDRC2LP, 2371 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2372 DDRPHYC, DDRPHYCLP, 2373 RTCAPB, 2374 TZC1, TZC2, 2375 TZPC, 2376 STGEN_K, 2377 }; 2378 2379 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2380 stm32mp_clk_enable(secure_enable[idx]); 2381 } 2382 } 2383 2384 static const struct clk_ops stm32mp_clk_ops = { 2385 .enable = stm32mp_clk_enable, 2386 .disable = stm32mp_clk_disable, 2387 .is_enabled = stm32mp_clk_is_enabled, 2388 .get_rate = stm32mp_clk_get_rate, 2389 .get_parent = stm32mp1_clk_get_parent, 2390 }; 2391 2392 int stm32mp1_clk_probe(void) 2393 { 2394 stm32mp1_osc_init(); 2395 2396 sync_earlyboot_clocks_state(); 2397 2398 clk_register(&stm32mp_clk_ops); 2399 2400 return 0; 2401 } 2402