1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_rcc.h> 21 #include <dt-bindings/clock/stm32mp1-clksrc.h> 22 #include <lib/mmio.h> 23 #include <lib/spinlock.h> 24 #include <lib/utils_def.h> 25 #include <libfdt.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 30 #define MAX_HSI_HZ 64000000 31 #define USB_PHY_48_MHZ 48000000 32 33 #define TIMEOUT_US_200MS U(200000) 34 #define TIMEOUT_US_1S U(1000000) 35 36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 41 42 const char *stm32mp_osc_node_label[NB_OSC] = { 43 [_LSI] = "clk-lsi", 44 [_LSE] = "clk-lse", 45 [_HSI] = "clk-hsi", 46 [_HSE] = "clk-hse", 47 [_CSI] = "clk-csi", 48 [_I2S_CKIN] = "i2s_ckin", 49 }; 50 51 enum stm32mp1_parent_id { 52 /* Oscillators are defined in enum stm32mp_osc_id */ 53 54 /* Other parent source */ 55 _HSI_KER = NB_OSC, 56 _HSE_KER, 57 _HSE_KER_DIV2, 58 _HSE_RTC, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _CKPER_SEL, 111 _RTC_SEL, 112 _PARENT_SEL_NB, 113 _UNKNOWN_SEL = 0xff, 114 }; 115 116 /* State the parent clock ID straight related to a clock */ 117 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 118 [_HSE] = CK_HSE, 119 [_HSI] = CK_HSI, 120 [_CSI] = CK_CSI, 121 [_LSE] = CK_LSE, 122 [_LSI] = CK_LSI, 123 [_I2S_CKIN] = _UNKNOWN_ID, 124 [_USB_PHY_48] = _UNKNOWN_ID, 125 [_HSI_KER] = CK_HSI, 126 [_HSE_KER] = CK_HSE, 127 [_HSE_KER_DIV2] = CK_HSE_DIV2, 128 [_HSE_RTC] = _UNKNOWN_ID, 129 [_CSI_KER] = CK_CSI, 130 [_PLL1_P] = PLL1_P, 131 [_PLL1_Q] = PLL1_Q, 132 [_PLL1_R] = PLL1_R, 133 [_PLL2_P] = PLL2_P, 134 [_PLL2_Q] = PLL2_Q, 135 [_PLL2_R] = PLL2_R, 136 [_PLL3_P] = PLL3_P, 137 [_PLL3_Q] = PLL3_Q, 138 [_PLL3_R] = PLL3_R, 139 [_PLL4_P] = PLL4_P, 140 [_PLL4_Q] = PLL4_Q, 141 [_PLL4_R] = PLL4_R, 142 [_ACLK] = CK_AXI, 143 [_PCLK1] = CK_AXI, 144 [_PCLK2] = CK_AXI, 145 [_PCLK3] = CK_AXI, 146 [_PCLK4] = CK_AXI, 147 [_PCLK5] = CK_AXI, 148 [_CK_PER] = CK_PER, 149 [_CK_MPU] = CK_MPU, 150 [_CK_MCU] = CK_MCU, 151 }; 152 153 static unsigned int clock_id2parent_id(unsigned long id) 154 { 155 unsigned int n; 156 157 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 158 if (parent_id_clock_id[n] == id) { 159 return n; 160 } 161 } 162 163 return _UNKNOWN_ID; 164 } 165 166 enum stm32mp1_pll_id { 167 _PLL1, 168 _PLL2, 169 _PLL3, 170 _PLL4, 171 _PLL_NB 172 }; 173 174 enum stm32mp1_div_id { 175 _DIV_P, 176 _DIV_Q, 177 _DIV_R, 178 _DIV_NB, 179 }; 180 181 enum stm32mp1_clksrc_id { 182 CLKSRC_MPU, 183 CLKSRC_AXI, 184 CLKSRC_MCU, 185 CLKSRC_PLL12, 186 CLKSRC_PLL3, 187 CLKSRC_PLL4, 188 CLKSRC_RTC, 189 CLKSRC_MCO1, 190 CLKSRC_MCO2, 191 CLKSRC_NB 192 }; 193 194 enum stm32mp1_clkdiv_id { 195 CLKDIV_MPU, 196 CLKDIV_AXI, 197 CLKDIV_MCU, 198 CLKDIV_APB1, 199 CLKDIV_APB2, 200 CLKDIV_APB3, 201 CLKDIV_APB4, 202 CLKDIV_APB5, 203 CLKDIV_RTC, 204 CLKDIV_MCO1, 205 CLKDIV_MCO2, 206 CLKDIV_NB 207 }; 208 209 enum stm32mp1_pllcfg { 210 PLLCFG_M, 211 PLLCFG_N, 212 PLLCFG_P, 213 PLLCFG_Q, 214 PLLCFG_R, 215 PLLCFG_O, 216 PLLCFG_NB 217 }; 218 219 enum stm32mp1_pllcsg { 220 PLLCSG_MOD_PER, 221 PLLCSG_INC_STEP, 222 PLLCSG_SSCG_MODE, 223 PLLCSG_NB 224 }; 225 226 enum stm32mp1_plltype { 227 PLL_800, 228 PLL_1600, 229 PLL_TYPE_NB 230 }; 231 232 struct stm32mp1_pll { 233 uint8_t refclk_min; 234 uint8_t refclk_max; 235 uint8_t divn_max; 236 }; 237 238 struct stm32mp1_clk_gate { 239 uint16_t offset; 240 uint8_t bit; 241 uint8_t index; 242 uint8_t set_clr; 243 uint8_t secure; 244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 245 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 246 }; 247 248 struct stm32mp1_clk_sel { 249 uint16_t offset; 250 uint8_t src; 251 uint8_t msk; 252 uint8_t nb_parent; 253 const uint8_t *parent; 254 }; 255 256 #define REFCLK_SIZE 4 257 struct stm32mp1_clk_pll { 258 enum stm32mp1_plltype plltype; 259 uint16_t rckxselr; 260 uint16_t pllxcfgr1; 261 uint16_t pllxcfgr2; 262 uint16_t pllxfracr; 263 uint16_t pllxcr; 264 uint16_t pllxcsgr; 265 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 266 }; 267 268 /* Clocks with selectable source and non set/clr register access */ 269 #define _CLK_SELEC(sec, off, b, idx, s) \ 270 { \ 271 .offset = (off), \ 272 .bit = (b), \ 273 .index = (idx), \ 274 .set_clr = 0, \ 275 .secure = (sec), \ 276 .sel = (s), \ 277 .fixed = _UNKNOWN_ID, \ 278 } 279 280 /* Clocks with fixed source and non set/clr register access */ 281 #define _CLK_FIXED(sec, off, b, idx, f) \ 282 { \ 283 .offset = (off), \ 284 .bit = (b), \ 285 .index = (idx), \ 286 .set_clr = 0, \ 287 .secure = (sec), \ 288 .sel = _UNKNOWN_SEL, \ 289 .fixed = (f), \ 290 } 291 292 /* Clocks with selectable source and set/clr register access */ 293 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 294 { \ 295 .offset = (off), \ 296 .bit = (b), \ 297 .index = (idx), \ 298 .set_clr = 1, \ 299 .secure = (sec), \ 300 .sel = (s), \ 301 .fixed = _UNKNOWN_ID, \ 302 } 303 304 /* Clocks with fixed source and set/clr register access */ 305 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 306 { \ 307 .offset = (off), \ 308 .bit = (b), \ 309 .index = (idx), \ 310 .set_clr = 1, \ 311 .secure = (sec), \ 312 .sel = _UNKNOWN_SEL, \ 313 .fixed = (f), \ 314 } 315 316 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 317 [_ ## _label ## _SEL] = { \ 318 .offset = _rcc_selr, \ 319 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 320 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 321 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 322 .parent = (_parents), \ 323 .nb_parent = ARRAY_SIZE(_parents) \ 324 } 325 326 #define _CLK_PLL(idx, type, off1, off2, off3, \ 327 off4, off5, off6, \ 328 p1, p2, p3, p4) \ 329 [(idx)] = { \ 330 .plltype = (type), \ 331 .rckxselr = (off1), \ 332 .pllxcfgr1 = (off2), \ 333 .pllxcfgr2 = (off3), \ 334 .pllxfracr = (off4), \ 335 .pllxcr = (off5), \ 336 .pllxcsgr = (off6), \ 337 .refclk[0] = (p1), \ 338 .refclk[1] = (p2), \ 339 .refclk[2] = (p3), \ 340 .refclk[3] = (p4), \ 341 } 342 343 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 344 345 #define SEC 1 346 #define N_S 0 347 348 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 359 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 360 361 #if defined(IMAGE_BL32) 362 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 363 #endif 364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 373 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 374 375 #if defined(IMAGE_BL32) 376 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 377 #endif 378 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 379 380 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 381 382 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 384 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 385 386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 389 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 395 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 396 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 397 398 #if defined(IMAGE_BL32) 399 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 400 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 401 #endif 402 403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 413 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 414 415 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 417 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 418 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 419 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 420 421 #if defined(IMAGE_BL2) 422 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 423 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 424 #endif 425 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 426 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 427 #if defined(IMAGE_BL32) 428 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 429 #endif 430 431 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 432 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 433 }; 434 435 static const uint8_t i2c12_parents[] = { 436 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 437 }; 438 439 static const uint8_t i2c35_parents[] = { 440 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 441 }; 442 443 static const uint8_t stgen_parents[] = { 444 _HSI_KER, _HSE_KER 445 }; 446 447 static const uint8_t i2c46_parents[] = { 448 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 449 }; 450 451 static const uint8_t spi6_parents[] = { 452 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 453 }; 454 455 static const uint8_t usart1_parents[] = { 456 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 457 }; 458 459 static const uint8_t rng1_parents[] = { 460 _CSI, _PLL4_R, _LSE, _LSI 461 }; 462 463 static const uint8_t uart6_parents[] = { 464 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 465 }; 466 467 static const uint8_t uart234578_parents[] = { 468 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 469 }; 470 471 static const uint8_t sdmmc12_parents[] = { 472 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 473 }; 474 475 static const uint8_t sdmmc3_parents[] = { 476 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 477 }; 478 479 static const uint8_t qspi_parents[] = { 480 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 481 }; 482 483 static const uint8_t fmc_parents[] = { 484 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 485 }; 486 487 static const uint8_t axiss_parents[] = { 488 _HSI, _HSE, _PLL2_P 489 }; 490 491 static const uint8_t mcuss_parents[] = { 492 _HSI, _HSE, _CSI, _PLL3_P 493 }; 494 495 static const uint8_t usbphy_parents[] = { 496 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 497 }; 498 499 static const uint8_t usbo_parents[] = { 500 _PLL4_R, _USB_PHY_48 501 }; 502 503 static const uint8_t mpu_parents[] = { 504 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 505 }; 506 507 static const uint8_t per_parents[] = { 508 _HSI, _HSE, _CSI, 509 }; 510 511 static const uint8_t rtc_parents[] = { 512 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 513 }; 514 515 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 516 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 517 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 518 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 519 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 520 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 521 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 522 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 523 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 524 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 525 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 526 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 527 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 528 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 529 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 530 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 531 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 532 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 533 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 534 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 535 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 536 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 537 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 538 }; 539 540 /* Define characteristic of PLL according type */ 541 #define DIVN_MIN 24 542 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 543 [PLL_800] = { 544 .refclk_min = 4, 545 .refclk_max = 16, 546 .divn_max = 99, 547 }, 548 [PLL_1600] = { 549 .refclk_min = 8, 550 .refclk_max = 16, 551 .divn_max = 199, 552 }, 553 }; 554 555 /* PLLNCFGR2 register divider by output */ 556 static const uint8_t pllncfgr2[_DIV_NB] = { 557 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 558 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 559 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 560 }; 561 562 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 563 _CLK_PLL(_PLL1, PLL_1600, 564 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 565 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 566 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 567 _CLK_PLL(_PLL2, PLL_1600, 568 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 569 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 570 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 571 _CLK_PLL(_PLL3, PLL_800, 572 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 573 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 574 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 575 _CLK_PLL(_PLL4, PLL_800, 576 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 577 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 578 _HSI, _HSE, _CSI, _I2S_CKIN), 579 }; 580 581 /* Prescaler table lookups for clock computation */ 582 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 583 static const uint8_t stm32mp1_mcu_div[16] = { 584 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 585 }; 586 587 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 588 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 589 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 590 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 591 0, 1, 2, 3, 4, 4, 4, 4 592 }; 593 594 /* div = /1 /2 /3 /4 */ 595 static const uint8_t stm32mp1_axi_div[8] = { 596 1, 2, 3, 4, 4, 4, 4, 4 597 }; 598 599 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 600 [_HSI] = "HSI", 601 [_HSE] = "HSE", 602 [_CSI] = "CSI", 603 [_LSI] = "LSI", 604 [_LSE] = "LSE", 605 [_I2S_CKIN] = "I2S_CKIN", 606 [_HSI_KER] = "HSI_KER", 607 [_HSE_KER] = "HSE_KER", 608 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 609 [_HSE_RTC] = "HSE_RTC", 610 [_CSI_KER] = "CSI_KER", 611 [_PLL1_P] = "PLL1_P", 612 [_PLL1_Q] = "PLL1_Q", 613 [_PLL1_R] = "PLL1_R", 614 [_PLL2_P] = "PLL2_P", 615 [_PLL2_Q] = "PLL2_Q", 616 [_PLL2_R] = "PLL2_R", 617 [_PLL3_P] = "PLL3_P", 618 [_PLL3_Q] = "PLL3_Q", 619 [_PLL3_R] = "PLL3_R", 620 [_PLL4_P] = "PLL4_P", 621 [_PLL4_Q] = "PLL4_Q", 622 [_PLL4_R] = "PLL4_R", 623 [_ACLK] = "ACLK", 624 [_PCLK1] = "PCLK1", 625 [_PCLK2] = "PCLK2", 626 [_PCLK3] = "PCLK3", 627 [_PCLK4] = "PCLK4", 628 [_PCLK5] = "PCLK5", 629 [_HCLK6] = "KCLK6", 630 [_HCLK2] = "HCLK2", 631 [_CK_PER] = "CK_PER", 632 [_CK_MPU] = "CK_MPU", 633 [_CK_MCU] = "CK_MCU", 634 [_USB_PHY_48] = "USB_PHY_48", 635 }; 636 637 /* RCC clock device driver private */ 638 static unsigned long stm32mp1_osc[NB_OSC]; 639 static struct spinlock reg_lock; 640 static unsigned int gate_refcounts[NB_GATES]; 641 static struct spinlock refcount_lock; 642 643 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 644 { 645 return &stm32mp1_clk_gate[idx]; 646 } 647 648 #if defined(IMAGE_BL32) 649 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 650 { 651 return gate->secure == N_S; 652 } 653 #endif 654 655 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 656 { 657 return &stm32mp1_clk_sel[idx]; 658 } 659 660 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 661 { 662 return &stm32mp1_clk_pll[idx]; 663 } 664 665 static void stm32mp1_clk_lock(struct spinlock *lock) 666 { 667 if (stm32mp_lock_available()) { 668 /* Assume interrupts are masked */ 669 spin_lock(lock); 670 } 671 } 672 673 static void stm32mp1_clk_unlock(struct spinlock *lock) 674 { 675 if (stm32mp_lock_available()) { 676 spin_unlock(lock); 677 } 678 } 679 680 bool stm32mp1_rcc_is_secure(void) 681 { 682 uintptr_t rcc_base = stm32mp_rcc_base(); 683 uint32_t mask = RCC_TZCR_TZEN; 684 685 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 686 } 687 688 bool stm32mp1_rcc_is_mckprot(void) 689 { 690 uintptr_t rcc_base = stm32mp_rcc_base(); 691 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 692 693 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 694 } 695 696 void stm32mp1_clk_rcc_regs_lock(void) 697 { 698 stm32mp1_clk_lock(®_lock); 699 } 700 701 void stm32mp1_clk_rcc_regs_unlock(void) 702 { 703 stm32mp1_clk_unlock(®_lock); 704 } 705 706 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 707 { 708 if (idx >= NB_OSC) { 709 return 0; 710 } 711 712 return stm32mp1_osc[idx]; 713 } 714 715 static int stm32mp1_clk_get_gated_id(unsigned long id) 716 { 717 unsigned int i; 718 719 for (i = 0U; i < NB_GATES; i++) { 720 if (gate_ref(i)->index == id) { 721 return i; 722 } 723 } 724 725 ERROR("%s: clk id %lu not found\n", __func__, id); 726 727 return -EINVAL; 728 } 729 730 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 731 { 732 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 733 } 734 735 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 736 { 737 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 738 } 739 740 static int stm32mp1_clk_get_parent(unsigned long id) 741 { 742 const struct stm32mp1_clk_sel *sel; 743 uint32_t p_sel; 744 int i; 745 enum stm32mp1_parent_id p; 746 enum stm32mp1_parent_sel s; 747 uintptr_t rcc_base = stm32mp_rcc_base(); 748 749 /* Few non gateable clock have a static parent ID, find them */ 750 i = (int)clock_id2parent_id(id); 751 if (i != _UNKNOWN_ID) { 752 return i; 753 } 754 755 i = stm32mp1_clk_get_gated_id(id); 756 if (i < 0) { 757 panic(); 758 } 759 760 p = stm32mp1_clk_get_fixed_parent(i); 761 if (p < _PARENT_NB) { 762 return (int)p; 763 } 764 765 s = stm32mp1_clk_get_sel(i); 766 if (s == _UNKNOWN_SEL) { 767 return -EINVAL; 768 } 769 if (s >= _PARENT_SEL_NB) { 770 panic(); 771 } 772 773 sel = clk_sel_ref(s); 774 p_sel = (mmio_read_32(rcc_base + sel->offset) & 775 (sel->msk << sel->src)) >> sel->src; 776 if (p_sel < sel->nb_parent) { 777 return (int)sel->parent[p_sel]; 778 } 779 780 return -EINVAL; 781 } 782 783 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 784 { 785 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 786 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 787 788 return stm32mp1_clk_get_fixed(pll->refclk[src]); 789 } 790 791 /* 792 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 793 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 794 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 795 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 796 */ 797 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 798 { 799 unsigned long refclk, fvco; 800 uint32_t cfgr1, fracr, divm, divn; 801 uintptr_t rcc_base = stm32mp_rcc_base(); 802 803 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 804 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 805 806 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 807 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 808 809 refclk = stm32mp1_pll_get_fref(pll); 810 811 /* 812 * With FRACV : 813 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 814 * Without FRACV 815 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 816 */ 817 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 818 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 819 RCC_PLLNFRACR_FRACV_SHIFT; 820 unsigned long long numerator, denominator; 821 822 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 823 numerator = refclk * numerator; 824 denominator = ((unsigned long long)divm + 1U) << 13; 825 fvco = (unsigned long)(numerator / denominator); 826 } else { 827 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 828 } 829 830 return fvco; 831 } 832 833 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 834 enum stm32mp1_div_id div_id) 835 { 836 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 837 unsigned long dfout; 838 uint32_t cfgr2, divy; 839 840 if (div_id >= _DIV_NB) { 841 return 0; 842 } 843 844 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 845 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 846 847 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 848 849 return dfout; 850 } 851 852 static unsigned long get_clock_rate(int p) 853 { 854 uint32_t reg, clkdiv; 855 unsigned long clock = 0; 856 uintptr_t rcc_base = stm32mp_rcc_base(); 857 858 switch (p) { 859 case _CK_MPU: 860 /* MPU sub system */ 861 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 862 switch (reg & RCC_SELR_SRC_MASK) { 863 case RCC_MPCKSELR_HSI: 864 clock = stm32mp1_clk_get_fixed(_HSI); 865 break; 866 case RCC_MPCKSELR_HSE: 867 clock = stm32mp1_clk_get_fixed(_HSE); 868 break; 869 case RCC_MPCKSELR_PLL: 870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 871 break; 872 case RCC_MPCKSELR_PLL_MPUDIV: 873 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 874 875 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 876 clkdiv = reg & RCC_MPUDIV_MASK; 877 clock >>= stm32mp1_mpu_div[clkdiv]; 878 break; 879 default: 880 break; 881 } 882 break; 883 /* AXI sub system */ 884 case _ACLK: 885 case _HCLK2: 886 case _HCLK6: 887 case _PCLK4: 888 case _PCLK5: 889 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 890 switch (reg & RCC_SELR_SRC_MASK) { 891 case RCC_ASSCKSELR_HSI: 892 clock = stm32mp1_clk_get_fixed(_HSI); 893 break; 894 case RCC_ASSCKSELR_HSE: 895 clock = stm32mp1_clk_get_fixed(_HSE); 896 break; 897 case RCC_ASSCKSELR_PLL: 898 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 899 break; 900 default: 901 break; 902 } 903 904 /* System clock divider */ 905 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 906 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 907 908 switch (p) { 909 case _PCLK4: 910 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 911 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 912 break; 913 case _PCLK5: 914 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 915 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 916 break; 917 default: 918 break; 919 } 920 break; 921 /* MCU sub system */ 922 case _CK_MCU: 923 case _PCLK1: 924 case _PCLK2: 925 case _PCLK3: 926 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 927 switch (reg & RCC_SELR_SRC_MASK) { 928 case RCC_MSSCKSELR_HSI: 929 clock = stm32mp1_clk_get_fixed(_HSI); 930 break; 931 case RCC_MSSCKSELR_HSE: 932 clock = stm32mp1_clk_get_fixed(_HSE); 933 break; 934 case RCC_MSSCKSELR_CSI: 935 clock = stm32mp1_clk_get_fixed(_CSI); 936 break; 937 case RCC_MSSCKSELR_PLL: 938 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 939 break; 940 default: 941 break; 942 } 943 944 /* MCU clock divider */ 945 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 946 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 947 948 switch (p) { 949 case _PCLK1: 950 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 951 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 952 break; 953 case _PCLK2: 954 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 955 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 956 break; 957 case _PCLK3: 958 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 959 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 960 break; 961 case _CK_MCU: 962 default: 963 break; 964 } 965 break; 966 case _CK_PER: 967 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 968 switch (reg & RCC_SELR_SRC_MASK) { 969 case RCC_CPERCKSELR_HSI: 970 clock = stm32mp1_clk_get_fixed(_HSI); 971 break; 972 case RCC_CPERCKSELR_HSE: 973 clock = stm32mp1_clk_get_fixed(_HSE); 974 break; 975 case RCC_CPERCKSELR_CSI: 976 clock = stm32mp1_clk_get_fixed(_CSI); 977 break; 978 default: 979 break; 980 } 981 break; 982 case _HSI: 983 case _HSI_KER: 984 clock = stm32mp1_clk_get_fixed(_HSI); 985 break; 986 case _CSI: 987 case _CSI_KER: 988 clock = stm32mp1_clk_get_fixed(_CSI); 989 break; 990 case _HSE: 991 case _HSE_KER: 992 clock = stm32mp1_clk_get_fixed(_HSE); 993 break; 994 case _HSE_KER_DIV2: 995 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 996 break; 997 case _HSE_RTC: 998 clock = stm32mp1_clk_get_fixed(_HSE); 999 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 1000 break; 1001 case _LSI: 1002 clock = stm32mp1_clk_get_fixed(_LSI); 1003 break; 1004 case _LSE: 1005 clock = stm32mp1_clk_get_fixed(_LSE); 1006 break; 1007 /* PLL */ 1008 case _PLL1_P: 1009 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1010 break; 1011 case _PLL1_Q: 1012 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1013 break; 1014 case _PLL1_R: 1015 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1016 break; 1017 case _PLL2_P: 1018 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1019 break; 1020 case _PLL2_Q: 1021 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1022 break; 1023 case _PLL2_R: 1024 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1025 break; 1026 case _PLL3_P: 1027 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1028 break; 1029 case _PLL3_Q: 1030 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1031 break; 1032 case _PLL3_R: 1033 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1034 break; 1035 case _PLL4_P: 1036 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1037 break; 1038 case _PLL4_Q: 1039 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1040 break; 1041 case _PLL4_R: 1042 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1043 break; 1044 /* Other */ 1045 case _USB_PHY_48: 1046 clock = USB_PHY_48_MHZ; 1047 break; 1048 default: 1049 break; 1050 } 1051 1052 return clock; 1053 } 1054 1055 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1056 { 1057 uintptr_t rcc_base = stm32mp_rcc_base(); 1058 1059 VERBOSE("Enable clock %u\n", gate->index); 1060 1061 if (gate->set_clr != 0U) { 1062 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1063 } else { 1064 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1065 } 1066 } 1067 1068 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1069 { 1070 uintptr_t rcc_base = stm32mp_rcc_base(); 1071 1072 VERBOSE("Disable clock %u\n", gate->index); 1073 1074 if (gate->set_clr != 0U) { 1075 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1076 BIT(gate->bit)); 1077 } else { 1078 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1079 } 1080 } 1081 1082 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1083 { 1084 uintptr_t rcc_base = stm32mp_rcc_base(); 1085 1086 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1087 } 1088 1089 /* Oscillators and PLLs are not gated at runtime */ 1090 static bool clock_is_always_on(unsigned long id) 1091 { 1092 switch (id) { 1093 case CK_HSE: 1094 case CK_CSI: 1095 case CK_LSI: 1096 case CK_LSE: 1097 case CK_HSI: 1098 case CK_HSE_DIV2: 1099 case PLL1_Q: 1100 case PLL1_R: 1101 case PLL2_P: 1102 case PLL2_Q: 1103 case PLL2_R: 1104 case PLL3_P: 1105 case PLL3_Q: 1106 case PLL3_R: 1107 case CK_AXI: 1108 case CK_MPU: 1109 case CK_MCU: 1110 case RTC: 1111 return true; 1112 default: 1113 return false; 1114 } 1115 } 1116 1117 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1118 { 1119 const struct stm32mp1_clk_gate *gate; 1120 int i; 1121 1122 if (clock_is_always_on(id)) { 1123 return; 1124 } 1125 1126 i = stm32mp1_clk_get_gated_id(id); 1127 if (i < 0) { 1128 ERROR("Clock %lu can't be enabled\n", id); 1129 panic(); 1130 } 1131 1132 gate = gate_ref(i); 1133 1134 if (!with_refcnt) { 1135 __clk_enable(gate); 1136 return; 1137 } 1138 1139 #if defined(IMAGE_BL32) 1140 if (gate_is_non_secure(gate)) { 1141 /* Enable non-secure clock w/o any refcounting */ 1142 __clk_enable(gate); 1143 return; 1144 } 1145 #endif 1146 1147 stm32mp1_clk_lock(&refcount_lock); 1148 1149 if (gate_refcounts[i] == 0U) { 1150 __clk_enable(gate); 1151 } 1152 1153 gate_refcounts[i]++; 1154 if (gate_refcounts[i] == UINT_MAX) { 1155 ERROR("Clock %lu refcount reached max value\n", id); 1156 panic(); 1157 } 1158 1159 stm32mp1_clk_unlock(&refcount_lock); 1160 } 1161 1162 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1163 { 1164 const struct stm32mp1_clk_gate *gate; 1165 int i; 1166 1167 if (clock_is_always_on(id)) { 1168 return; 1169 } 1170 1171 i = stm32mp1_clk_get_gated_id(id); 1172 if (i < 0) { 1173 ERROR("Clock %lu can't be disabled\n", id); 1174 panic(); 1175 } 1176 1177 gate = gate_ref(i); 1178 1179 if (!with_refcnt) { 1180 __clk_disable(gate); 1181 return; 1182 } 1183 1184 #if defined(IMAGE_BL32) 1185 if (gate_is_non_secure(gate)) { 1186 /* Don't disable non-secure clocks */ 1187 return; 1188 } 1189 #endif 1190 1191 stm32mp1_clk_lock(&refcount_lock); 1192 1193 if (gate_refcounts[i] == 0U) { 1194 ERROR("Clock %lu refcount reached 0\n", id); 1195 panic(); 1196 } 1197 gate_refcounts[i]--; 1198 1199 if (gate_refcounts[i] == 0U) { 1200 __clk_disable(gate); 1201 } 1202 1203 stm32mp1_clk_unlock(&refcount_lock); 1204 } 1205 1206 static int stm32mp_clk_enable(unsigned long id) 1207 { 1208 __stm32mp1_clk_enable(id, true); 1209 1210 return 0; 1211 } 1212 1213 static void stm32mp_clk_disable(unsigned long id) 1214 { 1215 __stm32mp1_clk_disable(id, true); 1216 } 1217 1218 static bool stm32mp_clk_is_enabled(unsigned long id) 1219 { 1220 int i; 1221 1222 if (clock_is_always_on(id)) { 1223 return true; 1224 } 1225 1226 i = stm32mp1_clk_get_gated_id(id); 1227 if (i < 0) { 1228 panic(); 1229 } 1230 1231 return __clk_is_enabled(gate_ref(i)); 1232 } 1233 1234 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1235 { 1236 uintptr_t rcc_base = stm32mp_rcc_base(); 1237 int p = stm32mp1_clk_get_parent(id); 1238 uint32_t prescaler, timpre; 1239 unsigned long parent_rate; 1240 1241 if (p < 0) { 1242 return 0; 1243 } 1244 1245 parent_rate = get_clock_rate(p); 1246 1247 switch (id) { 1248 case TIM2_K: 1249 case TIM3_K: 1250 case TIM4_K: 1251 case TIM5_K: 1252 case TIM6_K: 1253 case TIM7_K: 1254 case TIM12_K: 1255 case TIM13_K: 1256 case TIM14_K: 1257 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1258 RCC_APBXDIV_MASK; 1259 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1260 RCC_TIMGXPRER_TIMGXPRE; 1261 break; 1262 1263 case TIM1_K: 1264 case TIM8_K: 1265 case TIM15_K: 1266 case TIM16_K: 1267 case TIM17_K: 1268 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1269 RCC_APBXDIV_MASK; 1270 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1271 RCC_TIMGXPRER_TIMGXPRE; 1272 break; 1273 1274 default: 1275 return parent_rate; 1276 } 1277 1278 if (prescaler == 0U) { 1279 return parent_rate; 1280 } 1281 1282 return parent_rate * (timpre + 1U) * 2U; 1283 } 1284 1285 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1286 { 1287 uintptr_t address = stm32mp_rcc_base() + offset; 1288 1289 if (enable) { 1290 mmio_setbits_32(address, mask_on); 1291 } else { 1292 mmio_clrbits_32(address, mask_on); 1293 } 1294 } 1295 1296 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1297 { 1298 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1299 uintptr_t address = stm32mp_rcc_base() + offset; 1300 1301 mmio_write_32(address, mask_on); 1302 } 1303 1304 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1305 { 1306 uint64_t timeout; 1307 uint32_t mask_test; 1308 uintptr_t address = stm32mp_rcc_base() + offset; 1309 1310 if (enable) { 1311 mask_test = mask_rdy; 1312 } else { 1313 mask_test = 0; 1314 } 1315 1316 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1317 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1318 if (timeout_elapsed(timeout)) { 1319 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1320 mask_rdy, address, enable, mmio_read_32(address)); 1321 return -ETIMEDOUT; 1322 } 1323 } 1324 1325 return 0; 1326 } 1327 1328 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1329 { 1330 uint32_t value; 1331 uintptr_t rcc_base = stm32mp_rcc_base(); 1332 1333 if (digbyp) { 1334 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1335 } 1336 1337 if (bypass || digbyp) { 1338 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1339 } 1340 1341 /* 1342 * Warning: not recommended to switch directly from "high drive" 1343 * to "medium low drive", and vice-versa. 1344 */ 1345 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1346 RCC_BDCR_LSEDRV_SHIFT; 1347 1348 while (value != lsedrv) { 1349 if (value > lsedrv) { 1350 value--; 1351 } else { 1352 value++; 1353 } 1354 1355 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1356 RCC_BDCR_LSEDRV_MASK, 1357 value << RCC_BDCR_LSEDRV_SHIFT); 1358 } 1359 1360 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1361 } 1362 1363 static void stm32mp1_lse_wait(void) 1364 { 1365 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1366 VERBOSE("%s: failed\n", __func__); 1367 } 1368 } 1369 1370 static void stm32mp1_lsi_set(bool enable) 1371 { 1372 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1373 1374 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1375 VERBOSE("%s: failed\n", __func__); 1376 } 1377 } 1378 1379 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1380 { 1381 uintptr_t rcc_base = stm32mp_rcc_base(); 1382 1383 if (digbyp) { 1384 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1385 } 1386 1387 if (bypass || digbyp) { 1388 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1389 } 1390 1391 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1392 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1393 VERBOSE("%s: failed\n", __func__); 1394 } 1395 1396 if (css) { 1397 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1398 } 1399 1400 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1401 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1402 (!(digbyp || bypass))) { 1403 panic(); 1404 } 1405 #endif 1406 } 1407 1408 static void stm32mp1_csi_set(bool enable) 1409 { 1410 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1411 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1412 VERBOSE("%s: failed\n", __func__); 1413 } 1414 } 1415 1416 static void stm32mp1_hsi_set(bool enable) 1417 { 1418 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1419 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1420 VERBOSE("%s: failed\n", __func__); 1421 } 1422 } 1423 1424 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1425 { 1426 uint64_t timeout; 1427 uintptr_t rcc_base = stm32mp_rcc_base(); 1428 uintptr_t address = rcc_base + RCC_OCRDYR; 1429 1430 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1431 RCC_HSICFGR_HSIDIV_MASK, 1432 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1433 1434 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1435 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1436 if (timeout_elapsed(timeout)) { 1437 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1438 address, mmio_read_32(address)); 1439 return -ETIMEDOUT; 1440 } 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int stm32mp1_hsidiv(unsigned long hsifreq) 1447 { 1448 uint8_t hsidiv; 1449 uint32_t hsidivfreq = MAX_HSI_HZ; 1450 1451 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1452 if (hsidivfreq == hsifreq) { 1453 break; 1454 } 1455 1456 hsidivfreq /= 2U; 1457 } 1458 1459 if (hsidiv == 4U) { 1460 ERROR("Invalid clk-hsi frequency\n"); 1461 return -1; 1462 } 1463 1464 if (hsidiv != 0U) { 1465 return stm32mp1_set_hsidiv(hsidiv); 1466 } 1467 1468 return 0; 1469 } 1470 1471 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1472 unsigned int clksrc, 1473 uint32_t *pllcfg, int plloff) 1474 { 1475 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1476 uintptr_t rcc_base = stm32mp_rcc_base(); 1477 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1478 enum stm32mp1_plltype type = pll->plltype; 1479 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1480 unsigned long refclk; 1481 uint32_t ifrge = 0U; 1482 uint32_t src, value, fracv = 0; 1483 void *fdt; 1484 1485 /* Check PLL output */ 1486 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1487 return false; 1488 } 1489 1490 /* Check current clksrc */ 1491 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1492 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1493 return false; 1494 } 1495 1496 /* Check Div */ 1497 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1498 1499 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1500 (pllcfg[PLLCFG_M] + 1U); 1501 1502 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1503 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1504 return false; 1505 } 1506 1507 if ((type == PLL_800) && (refclk >= 8000000U)) { 1508 ifrge = 1U; 1509 } 1510 1511 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1512 RCC_PLLNCFGR1_DIVN_MASK; 1513 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1514 RCC_PLLNCFGR1_DIVM_MASK; 1515 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1516 RCC_PLLNCFGR1_IFRGE_MASK; 1517 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1518 return false; 1519 } 1520 1521 /* Fractional configuration */ 1522 if (fdt_get_address(&fdt) == 1) { 1523 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1524 } 1525 1526 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1527 value |= RCC_PLLNFRACR_FRACLE; 1528 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1529 return false; 1530 } 1531 1532 /* Output config */ 1533 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1534 RCC_PLLNCFGR2_DIVP_MASK; 1535 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1536 RCC_PLLNCFGR2_DIVQ_MASK; 1537 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1538 RCC_PLLNCFGR2_DIVR_MASK; 1539 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1540 return false; 1541 } 1542 1543 return true; 1544 } 1545 1546 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1547 { 1548 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1549 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1550 1551 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1552 mmio_clrsetbits_32(pllxcr, 1553 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1554 RCC_PLLNCR_DIVREN, 1555 RCC_PLLNCR_PLLON); 1556 } 1557 1558 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1559 { 1560 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1561 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1562 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1563 1564 /* Wait PLL lock */ 1565 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1566 if (timeout_elapsed(timeout)) { 1567 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1568 pll_id, pllxcr, mmio_read_32(pllxcr)); 1569 return -ETIMEDOUT; 1570 } 1571 } 1572 1573 /* Start the requested output */ 1574 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1575 1576 return 0; 1577 } 1578 1579 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1580 { 1581 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1582 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1583 uint64_t timeout; 1584 1585 /* Stop all output */ 1586 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1587 RCC_PLLNCR_DIVREN); 1588 1589 /* Stop PLL */ 1590 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1591 1592 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1593 /* Wait PLL stopped */ 1594 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1595 if (timeout_elapsed(timeout)) { 1596 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1597 pll_id, pllxcr, mmio_read_32(pllxcr)); 1598 return -ETIMEDOUT; 1599 } 1600 } 1601 1602 return 0; 1603 } 1604 1605 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1606 uint32_t *pllcfg) 1607 { 1608 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1609 uintptr_t rcc_base = stm32mp_rcc_base(); 1610 uint32_t value; 1611 1612 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1613 RCC_PLLNCFGR2_DIVP_MASK; 1614 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1615 RCC_PLLNCFGR2_DIVQ_MASK; 1616 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1617 RCC_PLLNCFGR2_DIVR_MASK; 1618 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1619 } 1620 1621 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1622 uint32_t *pllcfg, uint32_t fracv) 1623 { 1624 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1625 uintptr_t rcc_base = stm32mp_rcc_base(); 1626 enum stm32mp1_plltype type = pll->plltype; 1627 unsigned long refclk; 1628 uint32_t ifrge = 0; 1629 uint32_t src, value; 1630 1631 src = mmio_read_32(rcc_base + pll->rckxselr) & 1632 RCC_SELR_REFCLK_SRC_MASK; 1633 1634 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1635 (pllcfg[PLLCFG_M] + 1U); 1636 1637 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1638 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1639 return -EINVAL; 1640 } 1641 1642 if ((type == PLL_800) && (refclk >= 8000000U)) { 1643 ifrge = 1U; 1644 } 1645 1646 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1647 RCC_PLLNCFGR1_DIVN_MASK; 1648 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1649 RCC_PLLNCFGR1_DIVM_MASK; 1650 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1651 RCC_PLLNCFGR1_IFRGE_MASK; 1652 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1653 1654 /* Fractional configuration */ 1655 value = 0; 1656 mmio_write_32(rcc_base + pll->pllxfracr, value); 1657 1658 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1659 mmio_write_32(rcc_base + pll->pllxfracr, value); 1660 1661 value |= RCC_PLLNFRACR_FRACLE; 1662 mmio_write_32(rcc_base + pll->pllxfracr, value); 1663 1664 stm32mp1_pll_config_output(pll_id, pllcfg); 1665 1666 return 0; 1667 } 1668 1669 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1670 { 1671 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1672 uint32_t pllxcsg = 0; 1673 1674 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1675 RCC_PLLNCSGR_MOD_PER_MASK; 1676 1677 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1678 RCC_PLLNCSGR_INC_STEP_MASK; 1679 1680 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1681 RCC_PLLNCSGR_SSCG_MODE_MASK; 1682 1683 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1684 1685 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1686 RCC_PLLNCR_SSCG_CTRL); 1687 } 1688 1689 static int stm32mp1_set_clksrc(unsigned int clksrc) 1690 { 1691 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1692 uint64_t timeout; 1693 1694 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1695 clksrc & RCC_SELR_SRC_MASK); 1696 1697 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1698 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1699 if (timeout_elapsed(timeout)) { 1700 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1701 clksrc_address, mmio_read_32(clksrc_address)); 1702 return -ETIMEDOUT; 1703 } 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1710 { 1711 uint64_t timeout; 1712 1713 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1714 clkdiv & RCC_DIVR_DIV_MASK); 1715 1716 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1717 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1718 if (timeout_elapsed(timeout)) { 1719 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1720 clkdiv, address, mmio_read_32(address)); 1721 return -ETIMEDOUT; 1722 } 1723 } 1724 1725 return 0; 1726 } 1727 1728 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1729 { 1730 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1731 1732 /* 1733 * Binding clksrc : 1734 * bit15-4 offset 1735 * bit3: disable 1736 * bit2-0: MCOSEL[2:0] 1737 */ 1738 if ((clksrc & 0x8U) != 0U) { 1739 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1740 } else { 1741 mmio_clrsetbits_32(clksrc_address, 1742 RCC_MCOCFG_MCOSRC_MASK, 1743 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1744 mmio_clrsetbits_32(clksrc_address, 1745 RCC_MCOCFG_MCODIV_MASK, 1746 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1747 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1748 } 1749 } 1750 1751 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1752 { 1753 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1754 1755 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1756 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1757 mmio_clrsetbits_32(address, 1758 RCC_BDCR_RTCSRC_MASK, 1759 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1760 1761 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1762 } 1763 1764 if (lse_css) { 1765 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1766 } 1767 } 1768 1769 static void stm32mp1_pkcs_config(uint32_t pkcs) 1770 { 1771 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1772 uint32_t value = pkcs & 0xFU; 1773 uint32_t mask = 0xFU; 1774 1775 if ((pkcs & BIT(31)) != 0U) { 1776 mask <<= 4; 1777 value <<= 4; 1778 } 1779 1780 mmio_clrsetbits_32(address, mask, value); 1781 } 1782 1783 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1784 uint32_t *fracv, uint32_t *csg, 1785 bool *csg_set) 1786 { 1787 void *fdt; 1788 int ret; 1789 1790 if (fdt_get_address(&fdt) == 0) { 1791 return -FDT_ERR_NOTFOUND; 1792 } 1793 1794 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1795 pllcfg); 1796 if (ret < 0) { 1797 return -FDT_ERR_NOTFOUND; 1798 } 1799 1800 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1801 1802 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1803 csg); 1804 1805 *csg_set = (ret == 0); 1806 1807 if (ret == -FDT_ERR_NOTFOUND) { 1808 ret = 0; 1809 } 1810 1811 return ret; 1812 } 1813 1814 int stm32mp1_clk_init(void) 1815 { 1816 uintptr_t rcc_base = stm32mp_rcc_base(); 1817 uint32_t pllfracv[_PLL_NB]; 1818 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1819 unsigned int clksrc[CLKSRC_NB]; 1820 unsigned int clkdiv[CLKDIV_NB]; 1821 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1822 int plloff[_PLL_NB]; 1823 int ret, len; 1824 enum stm32mp1_pll_id i; 1825 bool pllcsg_set[_PLL_NB]; 1826 bool pllcfg_valid[_PLL_NB]; 1827 bool lse_css = false; 1828 bool pll3_preserve = false; 1829 bool pll4_preserve = false; 1830 bool pll4_bootrom = false; 1831 const fdt32_t *pkcs_cell; 1832 void *fdt; 1833 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1834 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1835 1836 if (fdt_get_address(&fdt) == 0) { 1837 return -FDT_ERR_NOTFOUND; 1838 } 1839 1840 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1841 clksrc); 1842 if (ret < 0) { 1843 return -FDT_ERR_NOTFOUND; 1844 } 1845 1846 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1847 clkdiv); 1848 if (ret < 0) { 1849 return -FDT_ERR_NOTFOUND; 1850 } 1851 1852 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1853 char name[12]; 1854 1855 snprintf(name, sizeof(name), "st,pll@%d", i); 1856 plloff[i] = fdt_rcc_subnode_offset(name); 1857 1858 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1859 if (!pllcfg_valid[i]) { 1860 continue; 1861 } 1862 1863 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1864 &pllfracv[i], pllcsg[i], 1865 &pllcsg_set[i]); 1866 if (ret != 0) { 1867 return ret; 1868 } 1869 } 1870 1871 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1872 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1873 1874 /* 1875 * Switch ON oscillator found in device-tree. 1876 * Note: HSI already ON after BootROM stage. 1877 */ 1878 if (stm32mp1_osc[_LSI] != 0U) { 1879 stm32mp1_lsi_set(true); 1880 } 1881 if (stm32mp1_osc[_LSE] != 0U) { 1882 const char *name = stm32mp_osc_node_label[_LSE]; 1883 bool bypass, digbyp; 1884 uint32_t lsedrv; 1885 1886 bypass = fdt_clk_read_bool(name, "st,bypass"); 1887 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1888 lse_css = fdt_clk_read_bool(name, "st,css"); 1889 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1890 LSEDRV_MEDIUM_HIGH); 1891 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1892 } 1893 if (stm32mp1_osc[_HSE] != 0U) { 1894 const char *name = stm32mp_osc_node_label[_HSE]; 1895 bool bypass, digbyp, css; 1896 1897 bypass = fdt_clk_read_bool(name, "st,bypass"); 1898 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1899 css = fdt_clk_read_bool(name, "st,css"); 1900 stm32mp1_hse_enable(bypass, digbyp, css); 1901 } 1902 /* 1903 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1904 * => switch on CSI even if node is not present in device tree 1905 */ 1906 stm32mp1_csi_set(true); 1907 1908 /* Come back to HSI */ 1909 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1910 if (ret != 0) { 1911 return ret; 1912 } 1913 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1914 if (ret != 0) { 1915 return ret; 1916 } 1917 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1918 if (ret != 0) { 1919 return ret; 1920 } 1921 1922 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1923 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1924 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1925 clksrc[CLKSRC_PLL3], 1926 pllcfg[_PLL3], 1927 plloff[_PLL3]); 1928 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1929 clksrc[CLKSRC_PLL4], 1930 pllcfg[_PLL4], 1931 plloff[_PLL4]); 1932 } 1933 /* Don't initialize PLL4, when used by BOOTROM */ 1934 if ((stm32mp_get_boot_itf_selected() == 1935 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1936 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1937 pll4_bootrom = true; 1938 pll4_preserve = true; 1939 } 1940 1941 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1942 if (((i == _PLL3) && pll3_preserve) || 1943 ((i == _PLL4) && pll4_preserve)) { 1944 continue; 1945 } 1946 1947 ret = stm32mp1_pll_stop(i); 1948 if (ret != 0) { 1949 return ret; 1950 } 1951 } 1952 1953 /* Configure HSIDIV */ 1954 if (stm32mp1_osc[_HSI] != 0U) { 1955 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1956 if (ret != 0) { 1957 return ret; 1958 } 1959 1960 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 1961 } 1962 1963 /* Select DIV */ 1964 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1965 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1966 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1967 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1968 if (ret != 0) { 1969 return ret; 1970 } 1971 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1972 if (ret != 0) { 1973 return ret; 1974 } 1975 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1976 if (ret != 0) { 1977 return ret; 1978 } 1979 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1980 if (ret != 0) { 1981 return ret; 1982 } 1983 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1984 if (ret != 0) { 1985 return ret; 1986 } 1987 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1988 if (ret != 0) { 1989 return ret; 1990 } 1991 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1992 if (ret != 0) { 1993 return ret; 1994 } 1995 1996 /* No ready bit for RTC */ 1997 mmio_write_32(rcc_base + RCC_RTCDIVR, 1998 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1999 2000 /* Configure PLLs source */ 2001 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2002 if (ret != 0) { 2003 return ret; 2004 } 2005 2006 if (!pll3_preserve) { 2007 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2008 if (ret != 0) { 2009 return ret; 2010 } 2011 } 2012 2013 if (!pll4_preserve) { 2014 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2015 if (ret != 0) { 2016 return ret; 2017 } 2018 } 2019 2020 /* Configure and start PLLs */ 2021 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2022 if (((i == _PLL3) && pll3_preserve) || 2023 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2024 continue; 2025 } 2026 2027 if (!pllcfg_valid[i]) { 2028 continue; 2029 } 2030 2031 if ((i == _PLL4) && pll4_bootrom) { 2032 /* Set output divider if not done by the Bootrom */ 2033 stm32mp1_pll_config_output(i, pllcfg[i]); 2034 continue; 2035 } 2036 2037 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2038 if (ret != 0) { 2039 return ret; 2040 } 2041 2042 if (pllcsg_set[i]) { 2043 stm32mp1_pll_csg(i, pllcsg[i]); 2044 } 2045 2046 stm32mp1_pll_start(i); 2047 } 2048 /* Wait and start PLLs ouptut when ready */ 2049 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2050 if (!pllcfg_valid[i]) { 2051 continue; 2052 } 2053 2054 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2055 if (ret != 0) { 2056 return ret; 2057 } 2058 } 2059 /* Wait LSE ready before to use it */ 2060 if (stm32mp1_osc[_LSE] != 0U) { 2061 stm32mp1_lse_wait(); 2062 } 2063 2064 /* Configure with expected clock source */ 2065 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2066 if (ret != 0) { 2067 return ret; 2068 } 2069 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2070 if (ret != 0) { 2071 return ret; 2072 } 2073 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2074 if (ret != 0) { 2075 return ret; 2076 } 2077 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2078 2079 /* Configure PKCK */ 2080 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2081 if (pkcs_cell != NULL) { 2082 bool ckper_disabled = false; 2083 uint32_t j; 2084 uint32_t usbreg_bootrom = 0U; 2085 2086 if (pll4_bootrom) { 2087 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2088 } 2089 2090 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2091 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2092 2093 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2094 ckper_disabled = true; 2095 continue; 2096 } 2097 stm32mp1_pkcs_config(pkcs); 2098 } 2099 2100 /* 2101 * CKPER is source for some peripheral clocks 2102 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2103 * only if previous clock is still ON 2104 * => deactivated CKPER only after switching clock 2105 */ 2106 if (ckper_disabled) { 2107 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2108 } 2109 2110 if (pll4_bootrom) { 2111 uint32_t usbreg_value, usbreg_mask; 2112 const struct stm32mp1_clk_sel *sel; 2113 2114 sel = clk_sel_ref(_USBPHY_SEL); 2115 usbreg_mask = (uint32_t)sel->msk << sel->src; 2116 sel = clk_sel_ref(_USBO_SEL); 2117 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2118 2119 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2120 usbreg_mask; 2121 usbreg_bootrom &= usbreg_mask; 2122 if (usbreg_bootrom != usbreg_value) { 2123 VERBOSE("forbidden new USB clk path\n"); 2124 VERBOSE("vs bootrom on USB boot\n"); 2125 return -FDT_ERR_BADVALUE; 2126 } 2127 } 2128 } 2129 2130 /* Switch OFF HSI if not found in device-tree */ 2131 if (stm32mp1_osc[_HSI] == 0U) { 2132 stm32mp1_hsi_set(false); 2133 } 2134 2135 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2136 2137 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2138 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2139 RCC_DDRITFCR_DDRCKMOD_MASK, 2140 RCC_DDRITFCR_DDRCKMOD_SSR << 2141 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2142 2143 return 0; 2144 } 2145 2146 static void stm32mp1_osc_clk_init(const char *name, 2147 enum stm32mp_osc_id index) 2148 { 2149 uint32_t frequency; 2150 2151 if (fdt_osc_read_freq(name, &frequency) == 0) { 2152 stm32mp1_osc[index] = frequency; 2153 } 2154 } 2155 2156 static void stm32mp1_osc_init(void) 2157 { 2158 enum stm32mp_osc_id i; 2159 2160 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2161 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2162 } 2163 } 2164 2165 #ifdef STM32MP_SHARED_RESOURCES 2166 /* 2167 * Get the parent ID of the target parent clock, for tagging as secure 2168 * shared clock dependencies. 2169 */ 2170 static int get_parent_id_parent(unsigned int parent_id) 2171 { 2172 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2173 enum stm32mp1_pll_id pll_id; 2174 uint32_t p_sel; 2175 uintptr_t rcc_base = stm32mp_rcc_base(); 2176 2177 switch (parent_id) { 2178 case _ACLK: 2179 case _PCLK4: 2180 case _PCLK5: 2181 s = _AXIS_SEL; 2182 break; 2183 case _PLL1_P: 2184 case _PLL1_Q: 2185 case _PLL1_R: 2186 pll_id = _PLL1; 2187 break; 2188 case _PLL2_P: 2189 case _PLL2_Q: 2190 case _PLL2_R: 2191 pll_id = _PLL2; 2192 break; 2193 case _PLL3_P: 2194 case _PLL3_Q: 2195 case _PLL3_R: 2196 pll_id = _PLL3; 2197 break; 2198 case _PLL4_P: 2199 case _PLL4_Q: 2200 case _PLL4_R: 2201 pll_id = _PLL4; 2202 break; 2203 case _PCLK1: 2204 case _PCLK2: 2205 case _HCLK2: 2206 case _HCLK6: 2207 case _CK_PER: 2208 case _CK_MPU: 2209 case _CK_MCU: 2210 case _USB_PHY_48: 2211 /* We do not expect to access these */ 2212 panic(); 2213 break; 2214 default: 2215 /* Other parents have no parent */ 2216 return -1; 2217 } 2218 2219 if (s != _UNKNOWN_SEL) { 2220 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2221 2222 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2223 sel->msk; 2224 2225 if (p_sel < sel->nb_parent) { 2226 return (int)sel->parent[p_sel]; 2227 } 2228 } else { 2229 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2230 2231 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2232 RCC_SELR_REFCLK_SRC_MASK; 2233 2234 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2235 return (int)pll->refclk[p_sel]; 2236 } 2237 } 2238 2239 VERBOSE("No parent selected for %s\n", 2240 stm32mp1_clk_parent_name[parent_id]); 2241 2242 return -1; 2243 } 2244 2245 static void secure_parent_clocks(unsigned long parent_id) 2246 { 2247 int grandparent_id; 2248 2249 switch (parent_id) { 2250 case _PLL3_P: 2251 case _PLL3_Q: 2252 case _PLL3_R: 2253 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2254 break; 2255 2256 /* These clocks are always secure when RCC is secure */ 2257 case _ACLK: 2258 case _HCLK2: 2259 case _HCLK6: 2260 case _PCLK4: 2261 case _PCLK5: 2262 case _PLL1_P: 2263 case _PLL1_Q: 2264 case _PLL1_R: 2265 case _PLL2_P: 2266 case _PLL2_Q: 2267 case _PLL2_R: 2268 case _HSI: 2269 case _HSI_KER: 2270 case _LSI: 2271 case _CSI: 2272 case _CSI_KER: 2273 case _HSE: 2274 case _HSE_KER: 2275 case _HSE_KER_DIV2: 2276 case _HSE_RTC: 2277 case _LSE: 2278 break; 2279 2280 default: 2281 VERBOSE("Cannot secure parent clock %s\n", 2282 stm32mp1_clk_parent_name[parent_id]); 2283 panic(); 2284 } 2285 2286 grandparent_id = get_parent_id_parent(parent_id); 2287 if (grandparent_id >= 0) { 2288 secure_parent_clocks(grandparent_id); 2289 } 2290 } 2291 2292 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2293 { 2294 int parent_id; 2295 2296 if (!stm32mp1_rcc_is_secure()) { 2297 return; 2298 } 2299 2300 switch (clock_id) { 2301 case PLL1: 2302 case PLL2: 2303 /* PLL1/PLL2 are always secure: nothing to do */ 2304 break; 2305 case PLL3: 2306 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2307 break; 2308 case PLL4: 2309 ERROR("PLL4 cannot be secured\n"); 2310 panic(); 2311 break; 2312 default: 2313 /* Others are expected gateable clock */ 2314 parent_id = stm32mp1_clk_get_parent(clock_id); 2315 if (parent_id < 0) { 2316 INFO("No parent found for clock %lu\n", clock_id); 2317 } else { 2318 secure_parent_clocks(parent_id); 2319 } 2320 break; 2321 } 2322 } 2323 #endif /* STM32MP_SHARED_RESOURCES */ 2324 2325 static void sync_earlyboot_clocks_state(void) 2326 { 2327 unsigned int idx; 2328 const unsigned long secure_enable[] = { 2329 AXIDCG, 2330 BSEC, 2331 DDRC1, DDRC1LP, 2332 DDRC2, DDRC2LP, 2333 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2334 DDRPHYC, DDRPHYCLP, 2335 RTCAPB, 2336 TZC1, TZC2, 2337 TZPC, 2338 STGEN_K, 2339 }; 2340 2341 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2342 stm32mp_clk_enable(secure_enable[idx]); 2343 } 2344 } 2345 2346 static const struct clk_ops stm32mp_clk_ops = { 2347 .enable = stm32mp_clk_enable, 2348 .disable = stm32mp_clk_disable, 2349 .is_enabled = stm32mp_clk_is_enabled, 2350 .get_rate = stm32mp_clk_get_rate, 2351 .get_parent = stm32mp1_clk_get_parent, 2352 }; 2353 2354 int stm32mp1_clk_probe(void) 2355 { 2356 #if defined(IMAGE_BL32) 2357 if (!fdt_get_rcc_secure_state()) { 2358 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); 2359 } 2360 #endif 2361 2362 stm32mp1_osc_init(); 2363 2364 sync_earlyboot_clocks_state(); 2365 2366 clk_register(&stm32mp_clk_ops); 2367 2368 return 0; 2369 } 2370